microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Paul Mackerras 5422007f83 Plumb loadstore1 input from execute1 not decode2 This allows us to use the bypass at the input of execute1 for the address and data operands for loadstore1. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		5 years ago
fpga	Fix some ghdlsynth issues with fpga_bram	5 years ago
hello_world	Move bin2hex.py to scripts/	5 years ago
media	…
scripts	Move bin2hex.py to scripts/	5 years ago
sim-unisim	…
tests	…
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	Make divider hang off the side of execute1	5 years ago
README.md	…
cache_ram.vhdl	…
common.vhdl	Plumb loadstore1 input from execute1 not decode2	5 years ago
control.vhdl	execute: Implement bypass from output of execute1 to input	5 years ago
core.vhdl	Plumb loadstore1 input from execute1 not decode2	5 years ago
core_debug.vhdl	…
core_tb.vhdl	…
countzero.vhdl	…
countzero_tb.vhdl	…
cr_file.vhdl	…
cr_hazard.vhdl	…
crhelpers.vhdl	…
dcache.vhdl	…
dcache_tb.vhdl	…
decode1.vhdl	execute: Move popcnt and prty instructions into the logical unit	5 years ago
decode2.vhdl	Plumb loadstore1 input from execute1 not decode2	5 years ago
decode_types.vhdl	execute: Move popcnt and prty instructions into the logical unit	5 years ago
divider.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
divider_tb.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
execute1.vhdl	Plumb loadstore1 input from execute1 not decode2	5 years ago
fetch1.vhdl	…
fetch2.vhdl	…
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	execute: Implement bypass from output of execute1 to input	5 years ago
helpers.vhdl	…
icache.vhdl	Fix a ghdlsynth issue in icache	5 years ago
icache_tb.vhdl	…
icache_test.bin	…
insn_helpers.vhdl	…
loadstore1.vhdl	Plumb loadstore1 input from execute1 not decode2	5 years ago
logical.vhdl	execute: Move popcnt and prty instructions into the logical unit	5 years ago
microwatt.core	…
multiply.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
multiply_tb.vhdl	execute1: Remember dest GPR, RC, OE, XER for slow operations	5 years ago
plru.vhdl	…
plru_tb.vhdl	…
ppc_fx_insns.vhdl	…
register_file.vhdl	…
rotator.vhdl	…
rotator_tb.vhdl	…
sim_bram.vhdl	…
sim_bram_helpers.vhdl	…
sim_bram_helpers_c.c	…
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_uart.vhdl	…
soc.vhdl	Removed unused core_terminated signal	5 years ago
utils.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
wishbone_bram_tb.vhdl	…
wishbone_bram_wrapper.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	…
writeback.vhdl	execute1: Move EXTS* instruction back into execute1	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)