A tiny Open POWER ISA softcore written in VHDL 2008
 
 
 
 
 
 
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Anton Blanchard 561d6af6f0 Use VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator targets
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
.github/workflows ci: use job.container
constraints Initial support for ghdl synthesis
fpga fetch1: Implement a simple branch target cache
hello_world Reduce hello_world footprint to fit in 8kB
include syscon: Add flag to indicate the timebase frequency
lib console: Add support for the 16550 UART
litedram fpga: Add support for Genesys2
liteeth liteeth: Hook up LiteX LiteEth ethernet controller
media Add title image
micropython tests: Add updated micropython build with 16550 support
openocd flash-arty: update error message ()
rust_lib_demo console: Cleanup console API
scripts decode: Add a facility field to the instruction decode tables
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
tests Add a test to read from all SPRs
uart16550 Add uart16550 files from fusesoc
verilator Pass clock frequency to UART sim wrapper
.gitignore Add yosys builds files to gitignore
LICENSE Initial import of microwatt
Makefile Use VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator targets
README.md Add Makefile command line variables to enable docker and podman
cache_ram.vhdl dcache: Rework RAM wrapper to synthetize better on Xilinx
common.vhdl core: Allow multiple loadstore instructions to be in flight
control.vhdl core: Allow multiple loadstore instructions to be in flight
core.vhdl core: Move redirect and interrupt delivery logic to writeback
core_debug.vhdl core_debug: Stop logging 256 cycles after trigger
core_dram_tb.vhdl litedram: l2: Add support for more geometries
core_flash_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel
core_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel
countzero.vhdl core: Add support for single-precision FP loads and stores
countzero_tb.vhdl Exit cleanly from testbench on success
cr_file.vhdl core: Don't generate logic for log data when LOG_LENGTH = 0
crhelpers.vhdl crhelpers: Constraint "crnum" integer
dcache.vhdl dcache: Fix bugs in pipelined operation
dcache_tb.vhdl Exit cleanly from testbench on success
decode1.vhdl core: Track CR hazards and bypasses using tags
decode2.vhdl core: Allow multiple loadstore instructions to be in flight
decode_types.vhdl core: Crack update-form loads into two internal ops
divider.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
divider_tb.vhdl Exit cleanly from testbench on success
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl ram: Rework main RAM interface
dmi_dtm_xilinx.vhdl Reset JTAG/DMI
dram_tb.vhdl litedram: l2: Add support for more geometries
execute1.vhdl core: Allow multiple loadstore instructions to be in flight
fetch1.vhdl core: Move redirect and interrupt delivery logic to writeback
fpu.vhdl core: Send FPU interrupts to writeback rather than execute1
glibc_random.vhdl Reformat glibc_random
glibc_random_helpers.vhdl Reformat glibc_random
helpers.vhdl core: Add support for single-precision FP loads and stores
icache.vhdl fetch1: Implement a simple branch target cache
icache_tb.vhdl core: Remove fetch2 pipeline stage
icache_test.bin icache_tb: Improve test and include test file
insn_helpers.vhdl core: Implement quadword loads and stores
loadstore1.vhdl Fix DAR/DSISR reading before they are written
logical.vhdl core: Make result multiplexing explicit
microwatt.core core: Track CR hazards and bypasses using tags
mmu.vhdl Initialize PID register
multiply.vhdl execute1: Take an extra cycle for OE=1 multiply instructions
multiply_tb.vhdl multiplier: Generalize interface to the multiplier
nonrandom.vhdl Add random number generator and implement the darn instruction
plru.vhdl plru: Improve sensitivity list
plru_tb.vhdl Exit cleanly from testbench on success
ppc_fx_insns.vhdl core: Implement the cmpeqb and cmprb instructions
random.vhdl Add random number generator and implement the darn instruction
register_file.vhdl core: Add support for floating-point loads and stores
rotator.vhdl Implement the extswsli instruction
rotator_tb.vhdl Exit cleanly from testbench on success
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART
sim_bram.vhdl ram: Rework main RAM interface
sim_bram_helpers.vhdl ram: Rework main RAM interface
sim_bram_helpers_c.c Consolidate VHPI code
sim_console.vhdl Reformat sim_console
sim_console_c.c sim_console: Fix polling to check for POLLIN
sim_jtag.vhdl Add jtag support in simulation via a socket
sim_jtag_socket.vhdl Add jtag support in simulation via a socket
sim_jtag_socket_c.c Consolidate VHPI code
sim_no_flash.vhdl spi: Add simulation support
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
sim_vhpi_c.c Consolidate VHPI code
sim_vhpi_c.h Consolidate VHPI code
soc.vhdl Allow SPI BOOT_CLOCKS to be overridden by top level
spi_flash_ctrl.vhdl Fix an issue in flash controller when BOOT_CLOCKS is false
spi_rxtx.vhdl Merge pull request from antonblanchard/another-spi-rxtx-reset-issu
sync_fifo.vhdl litedram: Add an L2 cache with store queue
syscon.vhdl syscon: Add flag to indicate the timebase frequency
utils.vhdl litedram: Add support for booting without BRAM
wishbone_arbiter.vhdl wb_arbiter: Early master selection
wishbone_bram_tb.bin ram: Rework main RAM interface
wishbone_bram_tb.vhdl Exit cleanly from testbench on success
wishbone_bram_wrapper.vhdl Add log2ceil and use it in bram code
wishbone_debug_master.vhdl wishbone_debug_master: Fix address auto-increment for memory writes
wishbone_types.vhdl Make wishbone_master_out and wb_io_master_out match
writeback.vhdl core: Send FPU interrupts to writeback rather than execute1
xics.vhdl xics: Add support for reduced priority field size
xilinx-mult.vhdl execute1: Take an extra cycle for OE=1 multiply instructions

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)