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A tiny Open POWER ISA softcore written in VHDL 2008
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Benjamin Herrenschmidt 8bb3c8f8b6 soc: Add DRAM address decoding 
Still not attached to any board

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
constraints Initial support for ghdl synthesis
fpga soc: Add DRAM address decoding
hello_world Update hello_world for 100Mhz clock
litedram litedram: Add basic support for LiteX LiteDRAM
media
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micropython Update micropython
openocd Initial support for ghdl synthesis
rust_lib_demo Merge remote-tracking branch 'remotes/origin/master'
scripts litedram: Add basic support for LiteX LiteDRAM
sim-unisim
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tests Merge remote-tracking branch 'remotes/origin/master'
.gitignore Add VHDL TAGS
.travis.yml
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LICENSE
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Makefile litedram: Add basic support for LiteX LiteDRAM
Makefile.synth make the sources volume mount SELinux friendly
README.md Change the default cross compiler prefix to powerpc64le-linux-gnu-
cache_ram.vhdl
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common.vhdl Merge remote-tracking branch 'remotes/origin/master'
control.vhdl core: Improve core reset
core.vhdl core: Add alternate reset address
core_debug.vhdl
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core_tb.vhdl soc: Add DRAM address decoding
countzero.vhdl countzero: Add a register to help make timing
countzero_tb.vhdl countzero: Add a register to help make timing
cr_file.vhdl Dump CTR, LR and CR on sim termination, and update our tests
cr_hazard.vhdl sprs: Store common SPRs in register file
crhelpers.vhdl
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dcache.vhdl dcache: Don't assert on dcbz cache hit
dcache_tb.vhdl loadstore1: Move logic from dcache to loadstore1
decode1.vhdl dcache: Implement the dcbz instruction
decode2.vhdl Plumb insn_type through to loadstore1
decode_types.vhdl Remove sim_config instruction
divider.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
divider_tb.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
dmi_dtm_dummy.vhdl
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dmi_dtm_tb.vhdl
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dmi_dtm_xilinx.vhdl
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execute1.vhdl execute1: Fix interrupt delivery during slow instructions
fetch1.vhdl core: Add alternate reset address
fetch2.vhdl core: Improve core reset
glibc_random.vhdl
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glibc_random_helpers.vhdl
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gpr_hazard.vhdl execute: Implement bypass from output of execute1 to input
helpers.vhdl
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icache.vhdl core: Improve core reset
icache_tb.vhdl
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icache_test.bin
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insn_helpers.vhdl Implement CRNOR and friends
loadstore1.vhdl dcache: Implement the dcbz instruction
logical.vhdl execute: Move popcnt and prty instructions into the logical unit
microwatt.core litedram: Add basic support for LiteX LiteDRAM
multiply.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
multiply_tb.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
plru.vhdl
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plru_tb.vhdl
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ppc_fx_insns.vhdl sprs: Store common SPRs in register file
register_file.vhdl Fix ghdlsynth issue in register file
rotator.vhdl
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rotator_tb.vhdl
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sim_bram.vhdl
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sim_bram_helpers.vhdl
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sim_bram_helpers_c.c Consolidate VHPI code
sim_console.vhdl
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sim_console_c.c Consolidate VHPI code
sim_jtag.vhdl
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sim_jtag_socket.vhdl
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sim_jtag_socket_c.c Consolidate VHPI code
sim_uart.vhdl Wire up sim uart TX interrupt
sim_vhpi_c.c Consolidate VHPI code
sim_vhpi_c.h Consolidate VHPI code
soc.vhdl soc: Add DRAM address decoding
utils.vhdl Add log2ceil and use it in bram code
wishbone_arbiter.vhdl
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wishbone_bram_tb.bin
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wishbone_bram_tb.vhdl
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wishbone_bram_wrapper.vhdl Add log2ceil and use it in bram code
wishbone_debug_master.vhdl wishbone_debug_master: Fix address auto-increment for memory writes
wishbone_types.vhdl
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writeback.vhdl execute1: Simplify the interrupt logic a little
xics.vhdl XICS interrupt controller

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or podman images. Read through the Makefile for details.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)