microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Paul Mackerras 9b40b5a77b logical: Only do output inversion for OP_AND, OP_OR and OP_XOR It's not needed for the other ops (popcnt, parity, etc.) and the logical unit shows up as a critical path from time to time. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		5 years ago
.github/workflows	…
constraints	…
fpga	uart: Make 16550 the default	5 years ago
hello_world	console: Add support for the 16550 UART	5 years ago
include	syscon: Add flag to indicate the timebase frequency	5 years ago
lib	console: Add support for the 16550 UART	5 years ago
litedram	Merge pull request #213 from ozbenh/uart16550	5 years ago
liteeth	liteeth: Hook up LiteX LiteEth ethernet controller	5 years ago
media	…
micropython	tests: Add updated micropython build with 16550 support	5 years ago
openocd	…
rust_lib_demo	console: Cleanup console API	5 years ago
scripts	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	5 years ago
sim-unisim	…
tests	tests: Add updated micropython build with 16550 support	5 years ago
verilator	…
.gitignore	…
LICENSE	…
Makefile	uart: Add a simulation model for the 16550 compatible UART	5 years ago
README.md	…
cache_ram.vhdl	…
common.vhdl	core: Implement CFAR register	5 years ago
control.vhdl	core: Use a busy signal rather than a stall	5 years ago
core.vhdl	Make LOG_LENGTH configurable per FPGA variant	5 years ago
core_debug.vhdl	Make LOG_LENGTH configurable per FPGA variant	5 years ago
core_dram_tb.vhdl	soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding	5 years ago
core_flash_tb.vhdl	soc: Don't require dram wishbones signals to be wired by toplevel	5 years ago
core_tb.vhdl	soc: Don't require dram wishbones signals to be wired by toplevel	5 years ago
countzero.vhdl	…
countzero_tb.vhdl	…
cr_file.vhdl	Add core logging	5 years ago
cr_hazard.vhdl	core: Use a busy signal rather than a stall	5 years ago
crhelpers.vhdl	…
dcache.vhdl	dcache: Reduce back-to-back store latency from 3 cycles to 2	5 years ago
dcache_tb.vhdl	…
decode1.vhdl	core: Implement CFAR register	5 years ago
decode2.vhdl	core: Implement a simple branch predictor	5 years ago
decode_types.vhdl	…
divider.vhdl	…
divider_tb.vhdl	…
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
dram_tb.vhdl	…
execute1.vhdl	core: Implement CFAR register	5 years ago
fetch1.vhdl	core: Implement CFAR register	5 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	core: Use a busy signal rather than a stall	5 years ago
helpers.vhdl	…
icache.vhdl	icache: Improve latencies when reloading cache lines	5 years ago
icache_tb.vhdl	core: Remove fetch2 pipeline stage	5 years ago
icache_test.bin	…
insn_helpers.vhdl	…
loadstore1.vhdl	loadstore1: Reduce busy cycles	5 years ago
logical.vhdl	logical: Only do output inversion for OP_AND, OP_OR and OP_XOR	5 years ago
microwatt.core	uart: Make 16550 the default	5 years ago
mmu.vhdl	mmu: Take an extra cycle to do TLB invalidations	5 years ago
multiply.vhdl	multiply: Move selection of result bits into execute1	5 years ago
multiply_tb.vhdl	multiply: Move selection of result bits into execute1	5 years ago
plru.vhdl	…
plru_tb.vhdl	…
ppc_fx_insns.vhdl	core: Implement a simple branch predictor	5 years ago
register_file.vhdl	Add core logging	5 years ago
rotator.vhdl	…
rotator_tb.vhdl	…
sim_16550_uart.vhdl	uart: Add a simulation model for the 16550 compatible UART	5 years ago
sim_bram.vhdl	…
sim_bram_helpers.vhdl	…
sim_bram_helpers_c.c	…
sim_console.vhdl	…
sim_console_c.c	sim_console: Fix polling to check for POLLIN	5 years ago
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_no_flash.vhdl	…
sim_pp_uart.vhdl	uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl	5 years ago
sim_vhpi_c.c	…
sim_vhpi_c.h	…
soc.vhdl	uart: Make 16550 the default	5 years ago
spi_flash_ctrl.vhdl	…
spi_rxtx.vhdl	…
sync_fifo.vhdl	…
syscon.vhdl	syscon: Add flag to indicate the timebase frequency	5 years ago
utils.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
wishbone_bram_tb.vhdl	…
wishbone_bram_wrapper.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	soc: Don't require dram wishbones signals to be wired by toplevel	5 years ago
writeback.vhdl	core: Use a busy signal rather than a stall	5 years ago
xics.vhdl	xics: Add support for reduced priority field size	5 years ago
xilinx-mult.vhdl	multiply: Use DSP48 slices for multiplication on Xilinx FPGAs	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)