A tiny Open POWER ISA softcore written in VHDL 2008

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Anton Blanchard a061924a78 Move byte reversal of stores to first cycle We are seeing some timing issues with the second cycle of loadstore, and we aren't doing much in the first cycle, so move it here. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>		5 years ago
fpga	SOC memory wishbone should clear ACK regardless of STB	5 years ago
hello_world	…
scripts	…
tests	…
.gitignore	…
.travis.yml	…
LICENSE	…
Makefile	Fix multiply_tb	5 years ago
README.md	…
common.vhdl	Add a simple direct mapped icache	5 years ago
core.vhdl	Add a simple direct mapped icache	5 years ago
core_tb.vhdl	Add a simple direct mapped icache	5 years ago
cr_file.vhdl	…
crhelpers.vhdl	…
decode1.vhdl	Merge pull request #59 from antonblanchard/trap-decode	5 years ago
decode2.vhdl	Fix spurious outstanding assert	5 years ago
decode_types.vhdl	Add a decode for the nop instruction	5 years ago
execute1.vhdl	…
execute2.vhdl	…
fetch1.vhdl	Add a default value for RESET_ADDRESS	5 years ago
fetch2.vhdl	Add a simple direct mapped icache	5 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
helpers.vhdl	…
icache.vhdl	Add a simple direct mapped icache	5 years ago
icache_tb.vhdl	Add an icache testbench	5 years ago
insn_helpers.vhdl	…
loadstore1.vhdl	Move byte reversal of stores to first cycle	5 years ago
loadstore2.vhdl	Move byte reversal of stores to first cycle	5 years ago
microwatt.core	Add a simple direct mapped icache	5 years ago
multiply.vhdl	…
multiply_tb.vhdl	Fix multiply_tb	5 years ago
ppc_fx_insns.vhdl	…
register_file.vhdl	…
sim_console.vhdl	…
sim_console_c.c	…
sim_uart.vhdl	…
simple_ram_behavioural.vhdl	…
simple_ram_behavioural_helpers.vhdl	…
simple_ram_behavioural_helpers_c.c	…
simple_ram_behavioural_tb.bin	…
simple_ram_behavioural_tb.vhdl	…
soc.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_types.vhdl	…
writeback.vhdl	Remove cycle in writeback	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com

git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin simple_ram_behavioural.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board):

fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

Need to implement a simple non pipelined divide
There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)