microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Benjamin Herrenschmidt acbdd396a5 soc/core: Add reset latches This adds one-cycle latches to the various resets out of the soc and into the various core modules. It seems to help vivado P&R a bit and has shown to avoid timing violations under some circumstances. Interestingly those resets never seem to appear in the bad timing path. It looks like those long resets simply impose placement constraints that Vivado satisfies at the expense of timing elsewhere. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		5 years ago
constraints	Initial support for ghdl synthesis	5 years ago
fpga	arty/nexys: Rework reset with litedram	5 years ago
hello_world	Makefile: Improve clean a bit	5 years ago
include	litedram: Update to new LiteX/LiteDRAM version	5 years ago
lib	litedram: Update to new LiteX/LiteDRAM version	5 years ago
litedram	litedram: Forward system reset signal	5 years ago
media	…
micropython	…
openocd	Initial support for ghdl synthesis	5 years ago
rust_lib_demo	console: Move console files	5 years ago
scripts	litedram: Add basic support for LiteX LiteDRAM	5 years ago
sim-unisim	…
tests	console: Move console files	5 years ago
.gitignore	Add VHDL TAGS	5 years ago
.travis.yml	…
LICENSE	…
Makefile	Makefile: Improve clean a bit	5 years ago
Makefile.synth	make the sources volume mount SELinux friendly	5 years ago
README.md	Change the default cross compiler prefix to powerpc64le-linux-gnu-	5 years ago
cache_ram.vhdl	…
common.vhdl	Merge remote-tracking branch 'remotes/origin/master'	5 years ago
control.vhdl	core: Improve core reset	5 years ago
core.vhdl	soc/core: Add reset latches	5 years ago
core_debug.vhdl	…
core_tb.vhdl	syscon: Add syscon registers	5 years ago
countzero.vhdl	…
countzero_tb.vhdl	…
cr_file.vhdl	…
cr_hazard.vhdl	…
crhelpers.vhdl	…
dcache.vhdl	dcache: Don't assert on dcbz cache hit	5 years ago
dcache_tb.vhdl	loadstore1: Move logic from dcache to loadstore1	5 years ago
decode1.vhdl	dcache: Implement the dcbz instruction	5 years ago
decode2.vhdl	Plumb insn_type through to loadstore1	5 years ago
decode_types.vhdl	Remove sim_config instruction	5 years ago
divider.vhdl	…
divider_tb.vhdl	…
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
execute1.vhdl	execute1: Fix interrupt delivery during slow instructions	5 years ago
fetch1.vhdl	core: Add alternate reset address	5 years ago
fetch2.vhdl	core: Improve core reset	5 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	…
helpers.vhdl	…
icache.vhdl	core: Improve core reset	5 years ago
icache_tb.vhdl	…
icache_test.bin	…
insn_helpers.vhdl	…
loadstore1.vhdl	dcache: Implement the dcbz instruction	5 years ago
logical.vhdl	…
microwatt.core	syscon: Add syscon registers	5 years ago
multiply.vhdl	…
multiply_tb.vhdl	…
plru.vhdl	…
plru_tb.vhdl	…
ppc_fx_insns.vhdl	…
register_file.vhdl	…
rotator.vhdl	…
rotator_tb.vhdl	…
sim_bram.vhdl	…
sim_bram_helpers.vhdl	…
sim_bram_helpers_c.c	Consolidate VHPI code	5 years ago
sim_console.vhdl	…
sim_console_c.c	Consolidate VHPI code	5 years ago
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	Consolidate VHPI code	5 years ago
sim_uart.vhdl	Wire up sim uart TX interrupt	5 years ago
sim_vhpi_c.c	Consolidate VHPI code	5 years ago
sim_vhpi_c.h	Consolidate VHPI code	5 years ago
soc.vhdl	soc/core: Add reset latches	5 years ago
syscon.vhdl	syscon: Add syscon registers	5 years ago
utils.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
wishbone_bram_tb.vhdl	…
wishbone_bram_wrapper.vhdl	…
wishbone_debug_master.vhdl	wishbone_debug_master: Fix address auto-increment for memory writes	5 years ago
wishbone_types.vhdl	…
writeback.vhdl	execute1: Simplify the interrupt logic a little	5 years ago
xics.vhdl	XICS interrupt controller	5 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or podman images. Read through the Makefile for details.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)