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Paul Mackerras
b14d982011
This enables back-to-back execution of integer instructions where the first instruction writes a GPR and the second reads the same GPR. This is done with a set of multiplexers at the start of execute1 which enable any of the three input operands to be taken from the output of execute1 (i.e. r.e.write_data) rather than the input from decode2 (i.e. e_in.read_data[123]). This also requires changes to the hazard detection and handling. Decode2 generates a signal indicating that the GPR being written is available for bypass, which is true for instructions that are executed in execute1 (rather than loadstore1/dcache). The gpr_hazard module stores this "bypassable" bit, and if the same GPR needs to be read by a subsequent instruction, it outputs a "use_bypass" signal rather than generating a stall. The use_bypass signal is then latched at the output of decode2 and passed down to execute1 to control the input multiplexer. At the moment there is no bypass on the inputs to loadstore1, but that is OK because all load and store instructions are marked as single-issue. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
5 years ago | |
|---|---|---|
| fpga | 5 years ago | |
| hello_world | 5 years ago | |
| media | ||
| scripts | 5 years ago | |
| sim-unisim | ||
| tests | 5 years ago | |
| .gitignore | ||
| .travis.yml | ||
| LICENSE | ||
| Makefile | 5 years ago | |
| README.md | 5 years ago | |
| cache_ram.vhdl | ||
| common.vhdl | 5 years ago | |
| control.vhdl | 5 years ago | |
| core.vhdl | 5 years ago | |
| core_debug.vhdl | ||
| core_tb.vhdl | 5 years ago | |
| countzero.vhdl | ||
| countzero_tb.vhdl | ||
| cr_file.vhdl | 5 years ago | |
| cr_hazard.vhdl | 5 years ago | |
| crhelpers.vhdl | ||
| dcache.vhdl | 5 years ago | |
| dcache_tb.vhdl | 5 years ago | |
| decode1.vhdl | 5 years ago | |
| decode2.vhdl | 5 years ago | |
| decode_types.vhdl | 5 years ago | |
| divider.vhdl | 5 years ago | |
| divider_tb.vhdl | 5 years ago | |
| dmi_dtm_dummy.vhdl | ||
| dmi_dtm_tb.vhdl | 5 years ago | |
| dmi_dtm_xilinx.vhdl | ||
| execute1.vhdl | 5 years ago | |
| fetch1.vhdl | ||
| fetch2.vhdl | ||
| glibc_random.vhdl | ||
| glibc_random_helpers.vhdl | ||
| gpr_hazard.vhdl | 5 years ago | |
| helpers.vhdl | 5 years ago | |
| icache.vhdl | 5 years ago | |
| icache_tb.vhdl | 5 years ago | |
| icache_test.bin | ||
| insn_helpers.vhdl | 5 years ago | |
| loadstore1.vhdl | 5 years ago | |
| logical.vhdl | 5 years ago | |
| microwatt.core | 5 years ago | |
| multiply.vhdl | 5 years ago | |
| multiply_tb.vhdl | 5 years ago | |
| plru.vhdl | ||
| plru_tb.vhdl | ||
| ppc_fx_insns.vhdl | 5 years ago | |
| register_file.vhdl | 5 years ago | |
| rotator.vhdl | ||
| rotator_tb.vhdl | ||
| sim_bram.vhdl | 5 years ago | |
| sim_bram_helpers.vhdl | 5 years ago | |
| sim_bram_helpers_c.c | 5 years ago | |
| sim_console.vhdl | ||
| sim_console_c.c | ||
| sim_jtag.vhdl | ||
| sim_jtag_socket.vhdl | ||
| sim_jtag_socket_c.c | ||
| sim_uart.vhdl | ||
| soc.vhdl | 5 years ago | |
| utils.vhdl | ||
| wishbone_arbiter.vhdl | 5 years ago | |
| wishbone_bram_tb.bin | 5 years ago | |
| wishbone_bram_tb.vhdl | 5 years ago | |
| wishbone_bram_wrapper.vhdl | 5 years ago | |
| wishbone_debug_master.vhdl | ||
| wishbone_types.vhdl | 5 years ago | |
| writeback.vhdl | 5 years ago | |
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../
- Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
Fedora users can get FuseSoC package via
sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button on your board if you don't see anything.
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)