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d2762e70e5
Vivado by default tries to flatten the module hierarchy to improve placement and timing. However this makes debugging timing issues really hard as the net names in the timing report can be pretty bogus. This adds a generic that can be used to control attributes to stop vivado from flattening the main core components. The resulting design will have worst timing overall but it will be easier to understand what the worst timing path are and address them. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
5 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| arty_a7.xdc | 5 years ago | |
| clk_gen_bypass.vhd | 5 years ago | |
| clk_gen_mcmm.vhd | 5 years ago | |
| clk_gen_plle2.vhd | 5 years ago | |
| cmod_a7-35.xdc | 5 years ago | |
| firmware.hex | ||
| hello_world.hex | ||
| mw_soc_memory.vhdl | 5 years ago | |
| nexys-video.xdc | ||
| nexys_a7.xdc | 5 years ago | |
| pp_fifo.vhd | 5 years ago | |
| pp_soc_uart.vhd | 5 years ago | |
| pp_utilities.vhd | ||
| soc_reset.vhdl | 5 years ago | |
| soc_reset_tb.vhdl | 5 years ago | |
| toplevel.vhdl | 5 years ago | |