microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

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Paul Mackerras dc1544db69 FPU: Implement floating multiply-add instructions This implements fmadd, fmsub, fnmadd, fnmsub and their single-precision counterparts. The single-precision versions operate the same as the double-precision versions until the final rounding and overflow/underflow steps. This adds an S register to store the low bits of the product. S shifts into R on left shifts, and can be negated, but doesn't do any other arithmetic. This adds a test for the double-precision versions of these instructions. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>		4 years ago
.github/workflows	…
constraints	…
fpga	core: Add support for floating-point loads and stores	4 years ago
hello_world	Enhance hello_world	5 years ago
include	…
lib	…
litedram	fpga: Add support for Genesys2	4 years ago
liteeth	…
media	…
micropython	…
openocd	…
rust_lib_demo	…
scripts	core: Add framework for an FPU	4 years ago
sim-unisim	…
tests	FPU: Implement floating multiply-add instructions	4 years ago
uart16550	…
verilator	…
.gitignore	…
LICENSE	…
Makefile	core: Add framework for an FPU	4 years ago
README.md	…
cache_ram.vhdl	…
common.vhdl	core: Add framework for an FPU	4 years ago
control.vhdl	core: Add support for floating-point loads and stores	4 years ago
core.vhdl	core: Add framework for an FPU	4 years ago
core_debug.vhdl	…
core_dram_tb.vhdl	litedram: l2: Add support for more geometries	5 years ago
core_flash_tb.vhdl	…
core_tb.vhdl	…
countzero.vhdl	core: Add support for single-precision FP loads and stores	4 years ago
countzero_tb.vhdl	…
cr_file.vhdl	core: Don't generate logic for log data when LOG_LENGTH = 0	5 years ago
cr_hazard.vhdl	…
crhelpers.vhdl	…
dcache.vhdl	dcache: Ease timing on wishbone data and byte selects	4 years ago
dcache_tb.vhdl	…
decode1.vhdl	FPU: Implement floating multiply-add instructions	4 years ago
decode2.vhdl	FPU: Implement fmul[s]	4 years ago
decode_types.vhdl	FPU: Implement fmul[s]	4 years ago
divider.vhdl	…
divider_tb.vhdl	…
dmi_dtm_dummy.vhdl	…
dmi_dtm_tb.vhdl	…
dmi_dtm_xilinx.vhdl	…
dram_tb.vhdl	litedram: l2: Add support for more geometries	5 years ago
execute1.vhdl	core: Add framework for an FPU	4 years ago
fetch1.vhdl	core: Implement 32-bit mode	4 years ago
fpu.vhdl	FPU: Implement floating multiply-add instructions	4 years ago
glibc_random.vhdl	…
glibc_random_helpers.vhdl	…
gpr_hazard.vhdl	core: Add support for floating-point loads and stores	4 years ago
helpers.vhdl	core: Add support for single-precision FP loads and stores	4 years ago
icache.vhdl	core: Implement big-endian mode	4 years ago
icache_tb.vhdl	…
icache_test.bin	…
insn_helpers.vhdl	FPU: Implement remaining FPSCR-related instructions	4 years ago
loadstore1.vhdl	core: Add support for single-precision FP loads and stores	4 years ago
logical.vhdl	core: Implement BCD Assist instructions addg6s, cdtbcd, cbcdtod	4 years ago
microwatt.core	core: Add framework for an FPU	4 years ago
mmu.vhdl	loadstore1: Generate busy signal earlier	4 years ago
multiply.vhdl	execute1: Take an extra cycle for OE=1 multiply instructions	4 years ago
multiply_tb.vhdl	multiplier: Generalize interface to the multiplier	4 years ago
nonrandom.vhdl	Add random number generator and implement the darn instruction	4 years ago
plru.vhdl	…
plru_tb.vhdl	…
ppc_fx_insns.vhdl	core: Implement the cmpeqb and cmprb instructions	4 years ago
random.vhdl	Add random number generator and implement the darn instruction	4 years ago
register_file.vhdl	core: Add support for floating-point loads and stores	4 years ago
rotator.vhdl	…
rotator_tb.vhdl	…
sim_16550_uart.vhdl	…
sim_bram.vhdl	…
sim_bram_helpers.vhdl	…
sim_bram_helpers_c.c	…
sim_console.vhdl	…
sim_console_c.c	…
sim_jtag.vhdl	…
sim_jtag_socket.vhdl	…
sim_jtag_socket_c.c	…
sim_no_flash.vhdl	…
sim_pp_uart.vhdl	…
sim_vhpi_c.c	…
sim_vhpi_c.h	…
soc.vhdl	core: Add support for floating-point loads and stores	4 years ago
spi_flash_ctrl.vhdl	…
spi_rxtx.vhdl	…
sync_fifo.vhdl	…
syscon.vhdl	…
utils.vhdl	…
wishbone_arbiter.vhdl	…
wishbone_bram_tb.bin	…
wishbone_bram_tb.vhdl	…
wishbone_bram_wrapper.vhdl	…
wishbone_debug_master.vhdl	…
wishbone_types.vhdl	…
writeback.vhdl	core: Add framework for an FPU	4 years ago
xics.vhdl	…
xilinx-mult.vhdl	execute1: Take an extra cycle for OE=1 multiply instructions	4 years ago

README.md

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.

git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1

Link in the micropython image:

ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin

Now run microwatt, sending debug output to /dev/null:

./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

Install Vivado (I'm using the free 2019.1 webpack edition).
Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh

Install FuseSoC:

pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc

Create a working directory and point FuseSoC at microwatt:

mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/

Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):

fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):

fusesoc run --target=nexys_video microwatt

Testing

A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:

make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

There are a few instructions still to be implemented
Need to add caches and bypassing (in progress)
Need to add supervisor state (in progress)