Comply with latest branding guidelines

Also includes a few fixes for comments from Paul Clarke.

Signed-off-by: Bill Schmidt <wschmidt@linux.ibm.com>

Intrinsics_Reference/ch_intro.xml

@@ -23,13 +23,17 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
   <section>
     <title>A Brief History</title>
     <para>
-      The history of vector programming on Power processors begins
+      The history of vector programming on <phrase
+      revisionflag="changed"><trademark
+      class="registered">Power</trademark></phrase> processors begins
       with the AIM (Apple, IBM, Motorola) alliance in the 1990s.  The
       AIM partners developed the Power Vector Media Extension (VMX) to
       accelerate multimedia applications, particularly image
       processing.  VMX is the name still used by IBM for this
       instruction set.  Freescale (formerly Motorola) used the
-      trademark "AltiVec," while Apple at one time called it "Velocity
+      trademark <phrase revisionflag="changed"><trademark
+      class="trade">AltiVec</trademark>,</phrase> while Apple at one
+      time called it "Velocity
       Engine."  While VMX remains the most official name, the term
       AltiVec is still in common use today.  Freescale's AltiVec
       Technology Programming Interface Manual (the "AltiVec PIM") is
@@ -68,11 +72,14 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
       also included AltiVec support, and was used in the Apple
       PowerMac G5.  IBM initially omitted support for VMX from its
       server-class computers, but added support for it in the POWER6
-      server family.
+      <phrase revisionflag="added">processor-based</phrase> server
+      family.
     </para>
     <para>
       IBM extended VMX by introducing the Vector-Scalar Extension
-      (VSX) for the POWER7 family of processors.  VSX adds sixty-four
+      (VSX) for the <phrase revisionflag="changed"><trademark
+      class="registered">POWER7</trademark></phrase> family of
+      processors.  VSX adds sixty-four
       128-bit vector-scalar registers (VSRs); however, to optimize the amount
       of per-process register state, the registers overlap with the
       VRs and the scalar floating-point registers (FPRs) (see <xref
@@ -80,13 +87,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
       the data types representable by the VRs, and can also be treated
       as containing two 64-bit integers or two 64-bit double-precision
       floating-point values.  However, ISA support for two 64-bit
-      integers in VSRs was limited until Version 2.07 (POWER8) of the
+      integers in VSRs was limited until Version 2.07 (<phrase
+      revisionflag="changed"><trademark
+      class="registered">POWER8</trademark></phrase>) of the
       Power ISA, and only the VRs are supported for these
       instructions.
     </para>
     <para>
       Both the VMX and VSX instruction sets have been expanded for the
-      POWER8 and POWER9 processor families.  Starting with POWER8,
+      <phrase revisionflag="changed">POWER8, <trademark
+      class="registered">POWER9</trademark>, and <trademark
+      class="registered">Power10</trademark></phrase> processor
+      families.  Starting with POWER8,
       a VSR can now contain a single 128-bit integer; and starting
       with POWER9, a VSR can contain a single 128-bit IEEE floating-point
       value.  Again, the ISA currently only supports 128-bit
@@ -103,7 +115,10 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
 	The Power architecture has supported operation in either
 	big-endian (BE) or little-endian (LE) mode from the
 	beginning.  However, IBM's Power servers were only shipped
-	with big-endian operating systems (AIX, Linux, i5/OS) prior to
+	with big-endian operating systems (<phrase
+	revisionflag="changed"><trademark
+	class="registered">AIX</trademark>, IBM i, <trademark
+	class="registered">Linux</trademark></phrase>) prior to
 	the introduction of POWER8.  With POWER8, IBM began
 	supporting little-endian Linux distributions for the first
 	time, and introduced a new application binary interface (the
@@ -135,7 +150,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
   <section xml:id="VIPR.intro.unified">
     <title>The Unified Vector Register Set</title>
     <para>
-      In OpenPOWER-compliant processors, floating-point and vector
+      In <phrase revisionflag="changed"><trademark
+      class="trade">OpenPOWER</trademark>-compliant</phrase>
+      processors, floating-point and vector
       operations are implemented using a unified vector-scalar model.
       As shown in <xref linkend="FPR-VSR" /> and <xref
       linkend="VR-VSR" />, there are 64 vector-scalar registers; each
@@ -202,13 +219,13 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
       <listitem>
 	<para>
 	  <emphasis role="underline">The XL <phrase
-	  revisionflag="added">and OpenXL</phrase>
+	  revisionflag="added">and Open XL</phrase>
 	  compilers</emphasis>.  For XL <phrase
-	  revisionflag="added">and OpenXL</phrase> compilers provided
+	  revisionflag="added">and Open XL</phrase> compilers provided
 	  with the Linux Community Edition, you can provide feedback
 	  to the XL compiler team via email
 	  (<email>compinfo@cn.ibm.com</email>); for other editions of
-	  XL <phrase revisionflag="added">and OpenXL</phrase>
+	  XL <phrase revisionflag="added">and Open XL</phrase>
 	  compilers, please open a <link
 	  xlink:href="https://www.ibm.com/mysupport/s/">Case</link>.
 	</para>
@@ -291,7 +308,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
       </listitem>
       <listitem revisionflag="added">
 	<para>
-	  <emphasis>POWER10 Processor User's Manual.</emphasis>
+	  <emphasis>Power10 Processor User's Manual.</emphasis>
 	  <emphasis>
 	    <link
 		xlink:href="https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k">Not
@@ -358,6 +375,18 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
     </itemizedlist>
   </section>
 
+  <section xml:id="VIPR.intro.marks" revisionflag="added">
+    <title>Trademarks</title>
+    <para>
+      AIX, POWER7, POWER8, POWER9, and Power10 are trademarks or
+      registered trademarks of International Business Machines
+      Corporation.  Linux is a registered trademark of Linus
+      Torvalds.  Intel is s registered trademark of Intel Corporation
+      or its subsidiaries.  AltiVec is a trademark of Freescale
+      Semiconductor, Inc.
+    </para>
+  </section>
+
   <section xml:id="VIPR.intro.conf">
     <title>Conformance to this Specification</title>
     <orderedlist>

Intrinsics_Reference/ch_mma_reference.xml

@@ -109,7 +109,7 @@
 	      <row>
 		<entry>
 		  <programlisting>
-  __vector_pair __builtin_vsx_lxvp (long long a, const __vector_pair* b)
+  __vector_pair __builtin_vsx_lxvp (signed long a, const __vector_pair* b)
 		  </programlisting>
 		</entry>
 		<entry>
@@ -121,7 +121,7 @@
 	      <row>
 		<entry>
 		  <programlisting>
-  void __builtin_vsx_stxvp (__vector_pair s, long long a, const __vector_pair* b)
+  void __builtin_vsx_stxvp (__vector_pair s, signed long a, const __vector_pair* b)
 		  </programlisting>
 		</entry>
 		<entry>

Intrinsics_Reference/ch_techniques.xml

@@ -229,7 +229,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_techniques">
 	Recent versions of the <phrase revisionflag="changed">GCC,
 	Clang, and Open XL</phrase> compilers
 	for Power provide "drop-in" portability headers for portions
-	of the Intel Architecture Instruction Set Extensions (see <xref
+	of the <phrase revisionflag="changed"><trademark
+	class="registered">Intel</trademark></phrase> Architecture
+	Instruction Set Extensions (see <xref
 	linkend="VIPR.intro.links" />).  These headers mirror the APIs
 	of Intel headers having the same names.  As of this writing,
 	support is provided for the MMX and SSE layers, up through

Intrinsics_Reference/ch_vec_reference.xml

@@ -125,8 +125,9 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
 	<para>
 	  <emphasis role="bold">ISA 3.0 or later</emphasis>.  This
 	  form is only available starting with PowerISA 3.0,
-	  corresponding to POWER9 servers.  The Power Vector Library
+	  corresponding to Power servers built with POWER9
-	  (see <xref linkend="VIPR.intro.links" /> provides equivalent
+	  architecture.  The Power Vector Library (see <xref
+	  linkend="VIPR.intro.links" /> provides equivalent
 	  POWER7/POWER8 implementations for many ISA 3.0 vector
 	  instructions, which may be preferred for portability.
 	</para>
@@ -135,10 +136,11 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
 	<para>
 	  <emphasis role="bold">ISA 3.1 or later</emphasis>.  This form
 	  is only available starting with PowerISA 3.1, corresponding to
-	  POWER10 servers.  The Power Vector Library (see <xref
+	  Power servers built with Power10 architecture.  The Power
-	  linkend="VIPR.intro.links" /> provides equivalent
+	  Vector Library (see <xref linkend="VIPR.intro.links" />
-	  POWER7/POWER8/POWER9 implementations for many ISA 3.1 vector
+	  provides equivalent POWER7/POWER8/POWER9 implementations for
-	  instructions, which may be preferred for portability.
+	  many ISA 3.1 vector instructions, which may be preferred for
+	  portability.
 	</para>
       </listitem>
       <listitem>
@@ -44622,8 +44624,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
       </programlisting>
 
       <para><emphasis role="bold">Purpose:</emphasis>
-      Return a non-zero value if and only if the input vector contains
+      Tests whether the input vector contains a zero element.
-      a zero element.
       </para>
       <para><emphasis role="bold">Result value:</emphasis>
       <emphasis role="bold">r</emphasis> is given a non-zero value if
@@ -44637,12 +44638,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
       </para>
       <para>
 	<emphasis role="bold">Notes:</emphasis>
-	Use this built-in in preference to <code>vec_nez</code> when
+	Use this built-in in preference to <code>vec_cmpnez</code>
-	the test guards a call to <code>vec_stril</code>.  This allows
+	when the test guards a call to <code>vec_stril</code>.  This
-	compilers to generate the most efficient code.
+	allows compilers to generate the most efficient code.
       </para>
       <para><emphasis role="bold">Review status:</emphasis>
-      Not yet reviewed.
+      Reviewed by Paul Clarke.
       </para>
       
       <indexterm>
@@ -44987,8 +44988,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
       </programlisting>
 
       <para><emphasis role="bold">Purpose:</emphasis>
-      Return a non-zero value if and only if the input vector contains
+      Tests whether the input vector contains a zero element.
-      a zero element.
       </para>
       <para><emphasis role="bold">Result value:</emphasis>
       <emphasis role="bold">r</emphasis> is given a non-zero value if
@@ -45002,12 +45002,12 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
       </para>
       <para>
 	<emphasis role="bold">Notes:</emphasis>
-	Use this built-in in preference to <code>vec_nez</code> when
+	Use this built-in in preference to <code>vec_cmpnez</code>
-	the test guards a call to <code>vec_strir</code>.  This allows
+	when the test guards a call to <code>vec_strir</code>.  This
-	compilers to generate the most efficient code.
+	allows compilers to generate the most efficient code.
       </para>
       <para><emphasis role="bold">Review status:</emphasis>
-      Not yet reviewed.
+      Reviewed by Paul Clarke.
       </para>
       
       <indexterm>