add source

rel/build/bd/ila.tcl

@@ -0,0 +1,138 @@
+# ila parms
+set ila u_ila_0
+
+set depth 32768
+set stages 3
+
+set trigin false
+set trigout false
+
+set basic true
+set advanced true
+# F/F 1-16 T/F 2-16 F/T 1-16 T/T 2-16
+set comp 4
+
+# make sure synth is open
+open_run synth_1
+
+# delete if exists
+# delete_debug_core -quiet [get_debug_cores -quiet $ila]
+catch {delete_debug_core [get_debug_cores $ila]}
+
+# add
+create_debug_core $ila ila
+set_property C_DATA_DEPTH $depth [get_debug_cores $ila]
+set_property C_INPUT_PIPE_STAGES $stages [get_debug_cores $ila]
+set_property C_TRIGIN_EN $trigin [get_debug_cores $ila]
+set_property C_TRIGOUT_EN $trigout [get_debug_cores $ila]
+set_property C_EN_STRG_QUAL $basic [get_debug_cores $ila]
+set_property C_ADV_TRIGGER $advanced [get_debug_cores $ila]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores $ila]
+set_property ALL_PROBE_SAME_MU_CNT $comp [get_debug_cores $ila]
+
+# add nets
+connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_0/inst/clk ]]
+set_property port_width 128 [get_debug_ports u_ila_0/probe0]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {a2l2_axi_0_an_ac_reld_data[127]} {a2l2_axi_0_an_ac_reld_data[126]} {a2l2_axi_0_an_ac_reld_data[125]} {a2l2_axi_0_an_ac_reld_data[124]} {a2l2_axi_0_an_ac_reld_data[123]} {a2l2_axi_0_an_ac_reld_data[122]} {a2l2_axi_0_an_ac_reld_data[121]} {a2l2_axi_0_an_ac_reld_data[120]} {a2l2_axi_0_an_ac_reld_data[119]} {a2l2_axi_0_an_ac_reld_data[118]} {a2l2_axi_0_an_ac_reld_data[117]} {a2l2_axi_0_an_ac_reld_data[116]} {a2l2_axi_0_an_ac_reld_data[115]} {a2l2_axi_0_an_ac_reld_data[114]} {a2l2_axi_0_an_ac_reld_data[113]} {a2l2_axi_0_an_ac_reld_data[112]} {a2l2_axi_0_an_ac_reld_data[111]} {a2l2_axi_0_an_ac_reld_data[110]} {a2l2_axi_0_an_ac_reld_data[109]} {a2l2_axi_0_an_ac_reld_data[108]} {a2l2_axi_0_an_ac_reld_data[107]} {a2l2_axi_0_an_ac_reld_data[106]} {a2l2_axi_0_an_ac_reld_data[105]} {a2l2_axi_0_an_ac_reld_data[104]} {a2l2_axi_0_an_ac_reld_data[103]} {a2l2_axi_0_an_ac_reld_data[102]} {a2l2_axi_0_an_ac_reld_data[101]} {a2l2_axi_0_an_ac_reld_data[100]} {a2l2_axi_0_an_ac_reld_data[99]} {a2l2_axi_0_an_ac_reld_data[98]} {a2l2_axi_0_an_ac_reld_data[97]} {a2l2_axi_0_an_ac_reld_data[96]} {a2l2_axi_0_an_ac_reld_data[95]} {a2l2_axi_0_an_ac_reld_data[94]} {a2l2_axi_0_an_ac_reld_data[93]} {a2l2_axi_0_an_ac_reld_data[92]} {a2l2_axi_0_an_ac_reld_data[91]} {a2l2_axi_0_an_ac_reld_data[90]} {a2l2_axi_0_an_ac_reld_data[89]} {a2l2_axi_0_an_ac_reld_data[88]} {a2l2_axi_0_an_ac_reld_data[87]} {a2l2_axi_0_an_ac_reld_data[86]} {a2l2_axi_0_an_ac_reld_data[85]} {a2l2_axi_0_an_ac_reld_data[84]} {a2l2_axi_0_an_ac_reld_data[83]} {a2l2_axi_0_an_ac_reld_data[82]} {a2l2_axi_0_an_ac_reld_data[81]} {a2l2_axi_0_an_ac_reld_data[80]} {a2l2_axi_0_an_ac_reld_data[79]} {a2l2_axi_0_an_ac_reld_data[78]} {a2l2_axi_0_an_ac_reld_data[77]} {a2l2_axi_0_an_ac_reld_data[76]} {a2l2_axi_0_an_ac_reld_data[75]} {a2l2_axi_0_an_ac_reld_data[74]} {a2l2_axi_0_an_ac_reld_data[73]} {a2l2_axi_0_an_ac_reld_data[72]} {a2l2_axi_0_an_ac_reld_data[71]} {a2l2_axi_0_an_ac_reld_data[70]} {a2l2_axi_0_an_ac_reld_data[69]} {a2l2_axi_0_an_ac_reld_data[68]} {a2l2_axi_0_an_ac_reld_data[67]} {a2l2_axi_0_an_ac_reld_data[66]} {a2l2_axi_0_an_ac_reld_data[65]} {a2l2_axi_0_an_ac_reld_data[64]} {a2l2_axi_0_an_ac_reld_data[63]} {a2l2_axi_0_an_ac_reld_data[62]} {a2l2_axi_0_an_ac_reld_data[61]} {a2l2_axi_0_an_ac_reld_data[60]} {a2l2_axi_0_an_ac_reld_data[59]} {a2l2_axi_0_an_ac_reld_data[58]} {a2l2_axi_0_an_ac_reld_data[57]} {a2l2_axi_0_an_ac_reld_data[56]} {a2l2_axi_0_an_ac_reld_data[55]} {a2l2_axi_0_an_ac_reld_data[54]} {a2l2_axi_0_an_ac_reld_data[53]} {a2l2_axi_0_an_ac_reld_data[52]} {a2l2_axi_0_an_ac_reld_data[51]} {a2l2_axi_0_an_ac_reld_data[50]} {a2l2_axi_0_an_ac_reld_data[49]} {a2l2_axi_0_an_ac_reld_data[48]} {a2l2_axi_0_an_ac_reld_data[47]} {a2l2_axi_0_an_ac_reld_data[46]} {a2l2_axi_0_an_ac_reld_data[45]} {a2l2_axi_0_an_ac_reld_data[44]} {a2l2_axi_0_an_ac_reld_data[43]} {a2l2_axi_0_an_ac_reld_data[42]} {a2l2_axi_0_an_ac_reld_data[41]} {a2l2_axi_0_an_ac_reld_data[40]} {a2l2_axi_0_an_ac_reld_data[39]} {a2l2_axi_0_an_ac_reld_data[38]} {a2l2_axi_0_an_ac_reld_data[37]} {a2l2_axi_0_an_ac_reld_data[36]} {a2l2_axi_0_an_ac_reld_data[35]} {a2l2_axi_0_an_ac_reld_data[34]} {a2l2_axi_0_an_ac_reld_data[33]} {a2l2_axi_0_an_ac_reld_data[32]} {a2l2_axi_0_an_ac_reld_data[31]} {a2l2_axi_0_an_ac_reld_data[30]} {a2l2_axi_0_an_ac_reld_data[29]} {a2l2_axi_0_an_ac_reld_data[28]} {a2l2_axi_0_an_ac_reld_data[27]} {a2l2_axi_0_an_ac_reld_data[26]} {a2l2_axi_0_an_ac_reld_data[25]} {a2l2_axi_0_an_ac_reld_data[24]} {a2l2_axi_0_an_ac_reld_data[23]} {a2l2_axi_0_an_ac_reld_data[22]} {a2l2_axi_0_an_ac_reld_data[21]} {a2l2_axi_0_an_ac_reld_data[20]} {a2l2_axi_0_an_ac_reld_data[19]} {a2l2_axi_0_an_ac_reld_data[18]} {a2l2_axi_0_an_ac_reld_data[17]} {a2l2_axi_0_an_ac_reld_data[16]} {a2l2_axi_0_an_ac_reld_data[15]} {a2l2_axi_0_an_ac_reld_data[14]} {a2l2_axi_0_an_ac_reld_data[13]} {a2l2_axi_0_an_ac_reld_data[12]} {a2l2_axi_0_an_ac_reld_data[11]} {a2l2_axi_0_an_ac_reld_data[10]} {a2l2_axi_0_an_ac_reld_data[9]} {a2l2_axi_0_an_ac_reld_data[8]} {a2l2_axi_0_an_ac_reld_data[7]} {a2l2_axi_0_an_ac_reld_data[6]} {a2l2_axi_0_an_ac_reld_data[5]} {a2l2_axi_0_an_ac_reld_data[4]} {a2l2_axi_0_an_ac_reld_data[3]} {a2l2_axi_0_an_ac_reld_data[2]} {a2l2_axi_0_an_ac_reld_data[1]} {a2l2_axi_0_an_ac_reld_data[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe1]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {a2l2_axi_0_an_ac_sync_ack[3]} {a2l2_axi_0_an_ac_sync_ack[2]} {a2l2_axi_0_an_ac_sync_ack[1]} {a2l2_axi_0_an_ac_sync_ack[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe2]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {a2l2_axi_0_an_ac_reld_qw[59]} {a2l2_axi_0_an_ac_reld_qw[58]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 128 [get_debug_ports u_ila_0/probe3]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {c_wrapper_0_ac_an_st_data[127]} {c_wrapper_0_ac_an_st_data[126]} {c_wrapper_0_ac_an_st_data[125]} {c_wrapper_0_ac_an_st_data[124]} {c_wrapper_0_ac_an_st_data[123]} {c_wrapper_0_ac_an_st_data[122]} {c_wrapper_0_ac_an_st_data[121]} {c_wrapper_0_ac_an_st_data[120]} {c_wrapper_0_ac_an_st_data[119]} {c_wrapper_0_ac_an_st_data[118]} {c_wrapper_0_ac_an_st_data[117]} {c_wrapper_0_ac_an_st_data[116]} {c_wrapper_0_ac_an_st_data[115]} {c_wrapper_0_ac_an_st_data[114]} {c_wrapper_0_ac_an_st_data[113]} {c_wrapper_0_ac_an_st_data[112]} {c_wrapper_0_ac_an_st_data[111]} {c_wrapper_0_ac_an_st_data[110]} {c_wrapper_0_ac_an_st_data[109]} {c_wrapper_0_ac_an_st_data[108]} {c_wrapper_0_ac_an_st_data[107]} {c_wrapper_0_ac_an_st_data[106]} {c_wrapper_0_ac_an_st_data[105]} {c_wrapper_0_ac_an_st_data[104]} {c_wrapper_0_ac_an_st_data[103]} {c_wrapper_0_ac_an_st_data[102]} {c_wrapper_0_ac_an_st_data[101]} {c_wrapper_0_ac_an_st_data[100]} {c_wrapper_0_ac_an_st_data[99]} {c_wrapper_0_ac_an_st_data[98]} {c_wrapper_0_ac_an_st_data[97]} {c_wrapper_0_ac_an_st_data[96]} {c_wrapper_0_ac_an_st_data[95]} {c_wrapper_0_ac_an_st_data[94]} {c_wrapper_0_ac_an_st_data[93]} {c_wrapper_0_ac_an_st_data[92]} {c_wrapper_0_ac_an_st_data[91]} {c_wrapper_0_ac_an_st_data[90]} {c_wrapper_0_ac_an_st_data[89]} {c_wrapper_0_ac_an_st_data[88]} {c_wrapper_0_ac_an_st_data[87]} {c_wrapper_0_ac_an_st_data[86]} {c_wrapper_0_ac_an_st_data[85]} {c_wrapper_0_ac_an_st_data[84]} {c_wrapper_0_ac_an_st_data[83]} {c_wrapper_0_ac_an_st_data[82]} {c_wrapper_0_ac_an_st_data[81]} {c_wrapper_0_ac_an_st_data[80]} {c_wrapper_0_ac_an_st_data[79]} {c_wrapper_0_ac_an_st_data[78]} {c_wrapper_0_ac_an_st_data[77]} {c_wrapper_0_ac_an_st_data[76]} {c_wrapper_0_ac_an_st_data[75]} {c_wrapper_0_ac_an_st_data[74]} {c_wrapper_0_ac_an_st_data[73]} {c_wrapper_0_ac_an_st_data[72]} {c_wrapper_0_ac_an_st_data[71]} {c_wrapper_0_ac_an_st_data[70]} {c_wrapper_0_ac_an_st_data[69]} {c_wrapper_0_ac_an_st_data[68]} {c_wrapper_0_ac_an_st_data[67]} {c_wrapper_0_ac_an_st_data[66]} {c_wrapper_0_ac_an_st_data[65]} {c_wrapper_0_ac_an_st_data[64]} {c_wrapper_0_ac_an_st_data[63]} {c_wrapper_0_ac_an_st_data[62]} {c_wrapper_0_ac_an_st_data[61]} {c_wrapper_0_ac_an_st_data[60]} {c_wrapper_0_ac_an_st_data[59]} {c_wrapper_0_ac_an_st_data[58]} {c_wrapper_0_ac_an_st_data[57]} {c_wrapper_0_ac_an_st_data[56]} {c_wrapper_0_ac_an_st_data[55]} {c_wrapper_0_ac_an_st_data[54]} {c_wrapper_0_ac_an_st_data[53]} {c_wrapper_0_ac_an_st_data[52]} {c_wrapper_0_ac_an_st_data[51]} {c_wrapper_0_ac_an_st_data[50]} {c_wrapper_0_ac_an_st_data[49]} {c_wrapper_0_ac_an_st_data[48]} {c_wrapper_0_ac_an_st_data[47]} {c_wrapper_0_ac_an_st_data[46]} {c_wrapper_0_ac_an_st_data[45]} {c_wrapper_0_ac_an_st_data[44]} {c_wrapper_0_ac_an_st_data[43]} {c_wrapper_0_ac_an_st_data[42]} {c_wrapper_0_ac_an_st_data[41]} {c_wrapper_0_ac_an_st_data[40]} {c_wrapper_0_ac_an_st_data[39]} {c_wrapper_0_ac_an_st_data[38]} {c_wrapper_0_ac_an_st_data[37]} {c_wrapper_0_ac_an_st_data[36]} {c_wrapper_0_ac_an_st_data[35]} {c_wrapper_0_ac_an_st_data[34]} {c_wrapper_0_ac_an_st_data[33]} {c_wrapper_0_ac_an_st_data[32]} {c_wrapper_0_ac_an_st_data[31]} {c_wrapper_0_ac_an_st_data[30]} {c_wrapper_0_ac_an_st_data[29]} {c_wrapper_0_ac_an_st_data[28]} {c_wrapper_0_ac_an_st_data[27]} {c_wrapper_0_ac_an_st_data[26]} {c_wrapper_0_ac_an_st_data[25]} {c_wrapper_0_ac_an_st_data[24]} {c_wrapper_0_ac_an_st_data[23]} {c_wrapper_0_ac_an_st_data[22]} {c_wrapper_0_ac_an_st_data[21]} {c_wrapper_0_ac_an_st_data[20]} {c_wrapper_0_ac_an_st_data[19]} {c_wrapper_0_ac_an_st_data[18]} {c_wrapper_0_ac_an_st_data[17]} {c_wrapper_0_ac_an_st_data[16]} {c_wrapper_0_ac_an_st_data[15]} {c_wrapper_0_ac_an_st_data[14]} {c_wrapper_0_ac_an_st_data[13]} {c_wrapper_0_ac_an_st_data[12]} {c_wrapper_0_ac_an_st_data[11]} {c_wrapper_0_ac_an_st_data[10]} {c_wrapper_0_ac_an_st_data[9]} {c_wrapper_0_ac_an_st_data[8]} {c_wrapper_0_ac_an_st_data[7]} {c_wrapper_0_ac_an_st_data[6]} {c_wrapper_0_ac_an_st_data[5]} {c_wrapper_0_ac_an_st_data[4]} {c_wrapper_0_ac_an_st_data[3]} {c_wrapper_0_ac_an_st_data[2]} {c_wrapper_0_ac_an_st_data[1]} {c_wrapper_0_ac_an_st_data[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe4]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {c_wrapper_0_ac_an_req_ttype[5]} {c_wrapper_0_ac_an_req_ttype[4]} {c_wrapper_0_ac_an_req_ttype[3]} {c_wrapper_0_ac_an_req_ttype[2]} {c_wrapper_0_ac_an_req_ttype[1]} {c_wrapper_0_ac_an_req_ttype[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/icd_icm_addr_real[51]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe6]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {a2l2_axi_0/inst/ldq_count_q_reg[3]} {a2l2_axi_0/inst/ldq_count_q_reg[2]} {a2l2_axi_0/inst/ldq_count_q_reg[1]} {a2l2_axi_0/inst/ldq_count_q_reg[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 22 [get_debug_ports u_ila_0/probe7]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[32]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe8]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[63]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[55]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[53]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[49]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[45]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[43]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[41]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[39]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[37]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[33]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[32]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe9]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {c_wrapper_0_ac_an_req_ra[63]} {c_wrapper_0_ac_an_req_ra[62]} {c_wrapper_0_ac_an_req_ra[61]} {c_wrapper_0_ac_an_req_ra[60]} {c_wrapper_0_ac_an_req_ra[59]} {c_wrapper_0_ac_an_req_ra[58]} {c_wrapper_0_ac_an_req_ra[57]} {c_wrapper_0_ac_an_req_ra[56]} {c_wrapper_0_ac_an_req_ra[55]} {c_wrapper_0_ac_an_req_ra[54]} {c_wrapper_0_ac_an_req_ra[53]} {c_wrapper_0_ac_an_req_ra[52]} {c_wrapper_0_ac_an_req_ra[51]} {c_wrapper_0_ac_an_req_ra[50]} {c_wrapper_0_ac_an_req_ra[49]} {c_wrapper_0_ac_an_req_ra[48]} {c_wrapper_0_ac_an_req_ra[47]} {c_wrapper_0_ac_an_req_ra[46]} {c_wrapper_0_ac_an_req_ra[45]} {c_wrapper_0_ac_an_req_ra[44]} {c_wrapper_0_ac_an_req_ra[43]} {c_wrapper_0_ac_an_req_ra[42]} {c_wrapper_0_ac_an_req_ra[41]} {c_wrapper_0_ac_an_req_ra[40]} {c_wrapper_0_ac_an_req_ra[39]} {c_wrapper_0_ac_an_req_ra[38]} {c_wrapper_0_ac_an_req_ra[37]} {c_wrapper_0_ac_an_req_ra[36]} {c_wrapper_0_ac_an_req_ra[35]} {c_wrapper_0_ac_an_req_ra[34]} {c_wrapper_0_ac_an_req_ra[33]} {c_wrapper_0_ac_an_req_ra[32]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe10]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {c_wrapper_0_ac_an_req_ld_xfr_len[2]} {c_wrapper_0_ac_an_req_ld_xfr_len[1]} {c_wrapper_0_ac_an_req_ld_xfr_len[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 62 [get_debug_ports u_ila_0/probe11]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[61]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[60]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[59]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[58]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[57]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[56]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[55]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[54]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[53]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[52]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[51]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[50]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[49]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[48]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[47]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[46]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[45]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[44]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[43]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[42]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[41]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[40]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[39]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[38]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[37]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[36]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[35]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[34]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[33]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[32]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[31]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[30]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[29]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[28]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[27]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[26]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[25]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[24]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[23]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[22]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[21]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[20]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[19]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[18]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[17]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[16]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[15]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[14]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[13]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[12]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[11]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[10]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[9]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[8]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[7]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[6]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[5]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[4]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[3]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[2]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[1]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 5 [get_debug_ports u_ila_0/probe12]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {c_wrapper_0_ac_an_req_ld_core_tag[4]} {c_wrapper_0_ac_an_req_ld_core_tag[3]} {c_wrapper_0_ac_an_req_ld_core_tag[2]} {c_wrapper_0_ac_an_req_ld_core_tag[1]} {c_wrapper_0_ac_an_req_ld_core_tag[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 58 [get_debug_ports u_ila_0/probe13]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[29]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[28]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[27]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[26]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[25]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[24]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[23]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[22]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[21]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[20]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[19]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[18]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[17]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[16]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[15]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[14]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[13]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[12]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[11]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[10]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[9]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[8]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[7]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[6]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[5]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[4]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[3]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[2]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[1]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe14]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[53]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[59]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[60]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[61]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe15]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {a2l2_axi_0/inst/stq_count_q_reg[5]} {a2l2_axi_0/inst/stq_count_q_reg[4]} {a2l2_axi_0/inst/stq_count_q_reg[3]} {a2l2_axi_0/inst/stq_count_q_reg[2]} {a2l2_axi_0/inst/stq_count_q_reg[1]} {a2l2_axi_0/inst/stq_count_q_reg[0]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list a2l2_axi_0_an_ac_reld_crit_qw ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list a2l2_axi_0_an_ac_reld_data_vld ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list a2l2_axi_0_an_ac_req_ld_pop ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list a2l2_axi_0_an_ac_req_st_pop ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list c_wrapper_0_ac_an_req ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe21]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list c_wrapper_0_ac_an_req_wimg_i ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe22]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/icd_icm_miss ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe23]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/ics_icd_iu1_flush ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_enable_q ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_pulse_q ]]
+

rel/build/bd/impl.tcl

@@ -0,0 +1,44 @@
+#synth_design -top a2o_bd -part xcvu3p-ffvc1517-2-e -verbose
+#source ila_axi.tcl
+
+# ----------------------------------------------------------------------------------------
+#       opt             place             phys_opt          route            phys_opt
+# ----------------------------------------------------------------------------------------
+# v0   (1)              Explore           Explore           Explore          Explore
+# v1   Explore          Explore           Explore           Explore          Explore    
+# ----------------------------------------------------------------------------------------
+# (1) -retarget -propconst -bram_power_opt
+#         
+set version v0
+
+# make sure synth is open
+open_run synth_1
+
+write_checkpoint -force a2o_synth_${version}.dcp
+
+if {$version == {v0}} {
+   opt_design -retarget -propconst -bram_power_opt -debug_log
+} elseif {$version == {v1}} {
+   opt_design -directive Explore -debug_log
+} else {
+   opt_design -debug_log
+}
+
+place_design -directive Explore
+#place_design -directive Explore -no_bufg_opt
+
+phys_opt_design -directive Explore
+route_design -directive Explore
+phys_opt_design -directive Explore
+
+write_checkpoint -force a2o_routed_${version}.dcp 
+
+report_utilization -file utilization_route_design_${version}.rpt
+report_timing_summary -max_paths 100 -file timing_routed_summary_${version}.rpt
+report_bus_skew -file timing_bus_skew_${version}.rpt
+report_qor_suggestions -file qor_suggestions_${version}.rpt
+
+write_bitstream -force -bin_file a2o_${version}
+write_debug_probes -force a2o_${version}
+write_cfgmem -force -format BIN -interface SPIx8 -size 256 -loadbit "up 0 a2o_${version}.bit" a2o_${version}
+

rel/build/bd/readme.md

@@ -0,0 +1,31 @@
+# create/build project
+
+```
+$VIVADO -mode tcl -source create_project.tcl
+
+$VIVADO a2o_bd/a2o_bd.xpr
+
+>run synthesis
+
+source ./ila.tcl ;# to update ila_0, or set up debug manually
+
+source ./impl.tcl
+```
+
+```
+a2o_bd_routed_v0.dcp
+a2o_bd_synth_v0.dcp
+
+utilization_route_design_v0.rpt
+timing_routed_summary_v0.rpt
+timing_bus_skew_v0.rpt
+qor_suggestions_v0.rpt
+
+a2o_bd_v0.bin
+a2o_bd_v0.bit
+a2o_bd_v0.ltx
+a2o_bd_v0_primary.bin
+a2o_bd_v0_primary.prm
+a2o_bd_v0_secondary.bin
+a2o_bd_v0_secondary.prm
+```

rel/build/bd/xdc/main_extras.xdc

@@ -0,0 +1,126 @@
+set_property DONT_TOUCH true [get_cells a2l2_axi_0]
+# added by vivado...
+
+
+
+
+
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 32768 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_0_clk]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 128 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {a2l2_axi_0_an_ac_reld_data[127]} {a2l2_axi_0_an_ac_reld_data[126]} {a2l2_axi_0_an_ac_reld_data[125]} {a2l2_axi_0_an_ac_reld_data[124]} {a2l2_axi_0_an_ac_reld_data[123]} {a2l2_axi_0_an_ac_reld_data[122]} {a2l2_axi_0_an_ac_reld_data[121]} {a2l2_axi_0_an_ac_reld_data[120]} {a2l2_axi_0_an_ac_reld_data[119]} {a2l2_axi_0_an_ac_reld_data[118]} {a2l2_axi_0_an_ac_reld_data[117]} {a2l2_axi_0_an_ac_reld_data[116]} {a2l2_axi_0_an_ac_reld_data[115]} {a2l2_axi_0_an_ac_reld_data[114]} {a2l2_axi_0_an_ac_reld_data[113]} {a2l2_axi_0_an_ac_reld_data[112]} {a2l2_axi_0_an_ac_reld_data[111]} {a2l2_axi_0_an_ac_reld_data[110]} {a2l2_axi_0_an_ac_reld_data[109]} {a2l2_axi_0_an_ac_reld_data[108]} {a2l2_axi_0_an_ac_reld_data[107]} {a2l2_axi_0_an_ac_reld_data[106]} {a2l2_axi_0_an_ac_reld_data[105]} {a2l2_axi_0_an_ac_reld_data[104]} {a2l2_axi_0_an_ac_reld_data[103]} {a2l2_axi_0_an_ac_reld_data[102]} {a2l2_axi_0_an_ac_reld_data[101]} {a2l2_axi_0_an_ac_reld_data[100]} {a2l2_axi_0_an_ac_reld_data[99]} {a2l2_axi_0_an_ac_reld_data[98]} {a2l2_axi_0_an_ac_reld_data[97]} {a2l2_axi_0_an_ac_reld_data[96]} {a2l2_axi_0_an_ac_reld_data[95]} {a2l2_axi_0_an_ac_reld_data[94]} {a2l2_axi_0_an_ac_reld_data[93]} {a2l2_axi_0_an_ac_reld_data[92]} {a2l2_axi_0_an_ac_reld_data[91]} {a2l2_axi_0_an_ac_reld_data[90]} {a2l2_axi_0_an_ac_reld_data[89]} {a2l2_axi_0_an_ac_reld_data[88]} {a2l2_axi_0_an_ac_reld_data[87]} {a2l2_axi_0_an_ac_reld_data[86]} {a2l2_axi_0_an_ac_reld_data[85]} {a2l2_axi_0_an_ac_reld_data[84]} {a2l2_axi_0_an_ac_reld_data[83]} {a2l2_axi_0_an_ac_reld_data[82]} {a2l2_axi_0_an_ac_reld_data[81]} {a2l2_axi_0_an_ac_reld_data[80]} {a2l2_axi_0_an_ac_reld_data[79]} {a2l2_axi_0_an_ac_reld_data[78]} {a2l2_axi_0_an_ac_reld_data[77]} {a2l2_axi_0_an_ac_reld_data[76]} {a2l2_axi_0_an_ac_reld_data[75]} {a2l2_axi_0_an_ac_reld_data[74]} {a2l2_axi_0_an_ac_reld_data[73]} {a2l2_axi_0_an_ac_reld_data[72]} {a2l2_axi_0_an_ac_reld_data[71]} {a2l2_axi_0_an_ac_reld_data[70]} {a2l2_axi_0_an_ac_reld_data[69]} {a2l2_axi_0_an_ac_reld_data[68]} {a2l2_axi_0_an_ac_reld_data[67]} {a2l2_axi_0_an_ac_reld_data[66]} {a2l2_axi_0_an_ac_reld_data[65]} {a2l2_axi_0_an_ac_reld_data[64]} {a2l2_axi_0_an_ac_reld_data[63]} {a2l2_axi_0_an_ac_reld_data[62]} {a2l2_axi_0_an_ac_reld_data[61]} {a2l2_axi_0_an_ac_reld_data[60]} {a2l2_axi_0_an_ac_reld_data[59]} {a2l2_axi_0_an_ac_reld_data[58]} {a2l2_axi_0_an_ac_reld_data[57]} {a2l2_axi_0_an_ac_reld_data[56]} {a2l2_axi_0_an_ac_reld_data[55]} {a2l2_axi_0_an_ac_reld_data[54]} {a2l2_axi_0_an_ac_reld_data[53]} {a2l2_axi_0_an_ac_reld_data[52]} {a2l2_axi_0_an_ac_reld_data[51]} {a2l2_axi_0_an_ac_reld_data[50]} {a2l2_axi_0_an_ac_reld_data[49]} {a2l2_axi_0_an_ac_reld_data[48]} {a2l2_axi_0_an_ac_reld_data[47]} {a2l2_axi_0_an_ac_reld_data[46]} {a2l2_axi_0_an_ac_reld_data[45]} {a2l2_axi_0_an_ac_reld_data[44]} {a2l2_axi_0_an_ac_reld_data[43]} {a2l2_axi_0_an_ac_reld_data[42]} {a2l2_axi_0_an_ac_reld_data[41]} {a2l2_axi_0_an_ac_reld_data[40]} {a2l2_axi_0_an_ac_reld_data[39]} {a2l2_axi_0_an_ac_reld_data[38]} {a2l2_axi_0_an_ac_reld_data[37]} {a2l2_axi_0_an_ac_reld_data[36]} {a2l2_axi_0_an_ac_reld_data[35]} {a2l2_axi_0_an_ac_reld_data[34]} {a2l2_axi_0_an_ac_reld_data[33]} {a2l2_axi_0_an_ac_reld_data[32]} {a2l2_axi_0_an_ac_reld_data[31]} {a2l2_axi_0_an_ac_reld_data[30]} {a2l2_axi_0_an_ac_reld_data[29]} {a2l2_axi_0_an_ac_reld_data[28]} {a2l2_axi_0_an_ac_reld_data[27]} {a2l2_axi_0_an_ac_reld_data[26]} {a2l2_axi_0_an_ac_reld_data[25]} {a2l2_axi_0_an_ac_reld_data[24]} {a2l2_axi_0_an_ac_reld_data[23]} {a2l2_axi_0_an_ac_reld_data[22]} {a2l2_axi_0_an_ac_reld_data[21]} {a2l2_axi_0_an_ac_reld_data[20]} {a2l2_axi_0_an_ac_reld_data[19]} {a2l2_axi_0_an_ac_reld_data[18]} {a2l2_axi_0_an_ac_reld_data[17]} {a2l2_axi_0_an_ac_reld_data[16]} {a2l2_axi_0_an_ac_reld_data[15]} {a2l2_axi_0_an_ac_reld_data[14]} {a2l2_axi_0_an_ac_reld_data[13]} {a2l2_axi_0_an_ac_reld_data[12]} {a2l2_axi_0_an_ac_reld_data[11]} {a2l2_axi_0_an_ac_reld_data[10]} {a2l2_axi_0_an_ac_reld_data[9]} {a2l2_axi_0_an_ac_reld_data[8]} {a2l2_axi_0_an_ac_reld_data[7]} {a2l2_axi_0_an_ac_reld_data[6]} {a2l2_axi_0_an_ac_reld_data[5]} {a2l2_axi_0_an_ac_reld_data[4]} {a2l2_axi_0_an_ac_reld_data[3]} {a2l2_axi_0_an_ac_reld_data[2]} {a2l2_axi_0_an_ac_reld_data[1]} {a2l2_axi_0_an_ac_reld_data[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 4 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {a2l2_axi_0_an_ac_sync_ack[3]} {a2l2_axi_0_an_ac_sync_ack[2]} {a2l2_axi_0_an_ac_sync_ack[1]} {a2l2_axi_0_an_ac_sync_ack[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 2 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {a2l2_axi_0_an_ac_reld_qw[59]} {a2l2_axi_0_an_ac_reld_qw[58]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 128 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {c_wrapper_0_ac_an_st_data[127]} {c_wrapper_0_ac_an_st_data[126]} {c_wrapper_0_ac_an_st_data[125]} {c_wrapper_0_ac_an_st_data[124]} {c_wrapper_0_ac_an_st_data[123]} {c_wrapper_0_ac_an_st_data[122]} {c_wrapper_0_ac_an_st_data[121]} {c_wrapper_0_ac_an_st_data[120]} {c_wrapper_0_ac_an_st_data[119]} {c_wrapper_0_ac_an_st_data[118]} {c_wrapper_0_ac_an_st_data[117]} {c_wrapper_0_ac_an_st_data[116]} {c_wrapper_0_ac_an_st_data[115]} {c_wrapper_0_ac_an_st_data[114]} {c_wrapper_0_ac_an_st_data[113]} {c_wrapper_0_ac_an_st_data[112]} {c_wrapper_0_ac_an_st_data[111]} {c_wrapper_0_ac_an_st_data[110]} {c_wrapper_0_ac_an_st_data[109]} {c_wrapper_0_ac_an_st_data[108]} {c_wrapper_0_ac_an_st_data[107]} {c_wrapper_0_ac_an_st_data[106]} {c_wrapper_0_ac_an_st_data[105]} {c_wrapper_0_ac_an_st_data[104]} {c_wrapper_0_ac_an_st_data[103]} {c_wrapper_0_ac_an_st_data[102]} {c_wrapper_0_ac_an_st_data[101]} {c_wrapper_0_ac_an_st_data[100]} {c_wrapper_0_ac_an_st_data[99]} {c_wrapper_0_ac_an_st_data[98]} {c_wrapper_0_ac_an_st_data[97]} {c_wrapper_0_ac_an_st_data[96]} {c_wrapper_0_ac_an_st_data[95]} {c_wrapper_0_ac_an_st_data[94]} {c_wrapper_0_ac_an_st_data[93]} {c_wrapper_0_ac_an_st_data[92]} {c_wrapper_0_ac_an_st_data[91]} {c_wrapper_0_ac_an_st_data[90]} {c_wrapper_0_ac_an_st_data[89]} {c_wrapper_0_ac_an_st_data[88]} {c_wrapper_0_ac_an_st_data[87]} {c_wrapper_0_ac_an_st_data[86]} {c_wrapper_0_ac_an_st_data[85]} {c_wrapper_0_ac_an_st_data[84]} {c_wrapper_0_ac_an_st_data[83]} {c_wrapper_0_ac_an_st_data[82]} {c_wrapper_0_ac_an_st_data[81]} {c_wrapper_0_ac_an_st_data[80]} {c_wrapper_0_ac_an_st_data[79]} {c_wrapper_0_ac_an_st_data[78]} {c_wrapper_0_ac_an_st_data[77]} {c_wrapper_0_ac_an_st_data[76]} {c_wrapper_0_ac_an_st_data[75]} {c_wrapper_0_ac_an_st_data[74]} {c_wrapper_0_ac_an_st_data[73]} {c_wrapper_0_ac_an_st_data[72]} {c_wrapper_0_ac_an_st_data[71]} {c_wrapper_0_ac_an_st_data[70]} {c_wrapper_0_ac_an_st_data[69]} {c_wrapper_0_ac_an_st_data[68]} {c_wrapper_0_ac_an_st_data[67]} {c_wrapper_0_ac_an_st_data[66]} {c_wrapper_0_ac_an_st_data[65]} {c_wrapper_0_ac_an_st_data[64]} {c_wrapper_0_ac_an_st_data[63]} {c_wrapper_0_ac_an_st_data[62]} {c_wrapper_0_ac_an_st_data[61]} {c_wrapper_0_ac_an_st_data[60]} {c_wrapper_0_ac_an_st_data[59]} {c_wrapper_0_ac_an_st_data[58]} {c_wrapper_0_ac_an_st_data[57]} {c_wrapper_0_ac_an_st_data[56]} {c_wrapper_0_ac_an_st_data[55]} {c_wrapper_0_ac_an_st_data[54]} {c_wrapper_0_ac_an_st_data[53]} {c_wrapper_0_ac_an_st_data[52]} {c_wrapper_0_ac_an_st_data[51]} {c_wrapper_0_ac_an_st_data[50]} {c_wrapper_0_ac_an_st_data[49]} {c_wrapper_0_ac_an_st_data[48]} {c_wrapper_0_ac_an_st_data[47]} {c_wrapper_0_ac_an_st_data[46]} {c_wrapper_0_ac_an_st_data[45]} {c_wrapper_0_ac_an_st_data[44]} {c_wrapper_0_ac_an_st_data[43]} {c_wrapper_0_ac_an_st_data[42]} {c_wrapper_0_ac_an_st_data[41]} {c_wrapper_0_ac_an_st_data[40]} {c_wrapper_0_ac_an_st_data[39]} {c_wrapper_0_ac_an_st_data[38]} {c_wrapper_0_ac_an_st_data[37]} {c_wrapper_0_ac_an_st_data[36]} {c_wrapper_0_ac_an_st_data[35]} {c_wrapper_0_ac_an_st_data[34]} {c_wrapper_0_ac_an_st_data[33]} {c_wrapper_0_ac_an_st_data[32]} {c_wrapper_0_ac_an_st_data[31]} {c_wrapper_0_ac_an_st_data[30]} {c_wrapper_0_ac_an_st_data[29]} {c_wrapper_0_ac_an_st_data[28]} {c_wrapper_0_ac_an_st_data[27]} {c_wrapper_0_ac_an_st_data[26]} {c_wrapper_0_ac_an_st_data[25]} {c_wrapper_0_ac_an_st_data[24]} {c_wrapper_0_ac_an_st_data[23]} {c_wrapper_0_ac_an_st_data[22]} {c_wrapper_0_ac_an_st_data[21]} {c_wrapper_0_ac_an_st_data[20]} {c_wrapper_0_ac_an_st_data[19]} {c_wrapper_0_ac_an_st_data[18]} {c_wrapper_0_ac_an_st_data[17]} {c_wrapper_0_ac_an_st_data[16]} {c_wrapper_0_ac_an_st_data[15]} {c_wrapper_0_ac_an_st_data[14]} {c_wrapper_0_ac_an_st_data[13]} {c_wrapper_0_ac_an_st_data[12]} {c_wrapper_0_ac_an_st_data[11]} {c_wrapper_0_ac_an_st_data[10]} {c_wrapper_0_ac_an_st_data[9]} {c_wrapper_0_ac_an_st_data[8]} {c_wrapper_0_ac_an_st_data[7]} {c_wrapper_0_ac_an_st_data[6]} {c_wrapper_0_ac_an_st_data[5]} {c_wrapper_0_ac_an_st_data[4]} {c_wrapper_0_ac_an_st_data[3]} {c_wrapper_0_ac_an_st_data[2]} {c_wrapper_0_ac_an_st_data[1]} {c_wrapper_0_ac_an_st_data[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 6 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {c_wrapper_0_ac_an_req_ttype[5]} {c_wrapper_0_ac_an_req_ttype[4]} {c_wrapper_0_ac_an_req_ttype[3]} {c_wrapper_0_ac_an_req_ttype[2]} {c_wrapper_0_ac_an_req_ttype[1]} {c_wrapper_0_ac_an_req_ttype[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/icd_icm_addr_real[51]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 4 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {a2l2_axi_0/inst/ldq_count_q_reg[3]} {a2l2_axi_0/inst/ldq_count_q_reg[2]} {a2l2_axi_0/inst/ldq_count_q_reg[1]} {a2l2_axi_0/inst/ldq_count_q_reg[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 22 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[32]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 32 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[63]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[55]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[53]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[49]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[45]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[43]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[41]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[39]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[37]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[33]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[32]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 32 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {c_wrapper_0_ac_an_req_ra[63]} {c_wrapper_0_ac_an_req_ra[62]} {c_wrapper_0_ac_an_req_ra[61]} {c_wrapper_0_ac_an_req_ra[60]} {c_wrapper_0_ac_an_req_ra[59]} {c_wrapper_0_ac_an_req_ra[58]} {c_wrapper_0_ac_an_req_ra[57]} {c_wrapper_0_ac_an_req_ra[56]} {c_wrapper_0_ac_an_req_ra[55]} {c_wrapper_0_ac_an_req_ra[54]} {c_wrapper_0_ac_an_req_ra[53]} {c_wrapper_0_ac_an_req_ra[52]} {c_wrapper_0_ac_an_req_ra[51]} {c_wrapper_0_ac_an_req_ra[50]} {c_wrapper_0_ac_an_req_ra[49]} {c_wrapper_0_ac_an_req_ra[48]} {c_wrapper_0_ac_an_req_ra[47]} {c_wrapper_0_ac_an_req_ra[46]} {c_wrapper_0_ac_an_req_ra[45]} {c_wrapper_0_ac_an_req_ra[44]} {c_wrapper_0_ac_an_req_ra[43]} {c_wrapper_0_ac_an_req_ra[42]} {c_wrapper_0_ac_an_req_ra[41]} {c_wrapper_0_ac_an_req_ra[40]} {c_wrapper_0_ac_an_req_ra[39]} {c_wrapper_0_ac_an_req_ra[38]} {c_wrapper_0_ac_an_req_ra[37]} {c_wrapper_0_ac_an_req_ra[36]} {c_wrapper_0_ac_an_req_ra[35]} {c_wrapper_0_ac_an_req_ra[34]} {c_wrapper_0_ac_an_req_ra[33]} {c_wrapper_0_ac_an_req_ra[32]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 3 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {c_wrapper_0_ac_an_req_ld_xfr_len[2]} {c_wrapper_0_ac_an_req_ld_xfr_len[1]} {c_wrapper_0_ac_an_req_ld_xfr_len[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 62 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[61]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[60]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[59]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[58]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[57]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[56]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[55]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[54]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[53]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[52]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[51]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[50]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[49]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[48]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[47]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[46]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[45]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[44]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[43]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[42]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[41]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[40]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[39]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[38]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[37]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[36]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[35]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[34]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[33]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[32]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[31]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[30]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[29]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[28]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[27]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[26]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[25]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[24]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[23]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[22]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[21]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[20]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[19]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[18]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[17]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[16]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[15]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[14]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[13]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[12]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[11]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[10]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[9]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[8]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[7]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[6]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[5]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[4]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[3]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[2]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[1]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 5 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {c_wrapper_0_ac_an_req_ld_core_tag[4]} {c_wrapper_0_ac_an_req_ld_core_tag[3]} {c_wrapper_0_ac_an_req_ld_core_tag[2]} {c_wrapper_0_ac_an_req_ld_core_tag[1]} {c_wrapper_0_ac_an_req_ld_core_tag[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 58 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[29]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[28]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[27]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[26]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[25]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[24]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[23]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[22]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[21]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[20]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[19]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[18]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[17]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[16]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[15]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[14]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[13]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[12]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[11]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[10]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[9]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[8]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[7]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[6]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[5]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[4]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[3]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[2]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[1]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 32 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[53]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[59]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[60]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[61]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 6 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {a2l2_axi_0/inst/stq_count_q_reg[5]} {a2l2_axi_0/inst/stq_count_q_reg[4]} {a2l2_axi_0/inst/stq_count_q_reg[3]} {a2l2_axi_0/inst/stq_count_q_reg[2]} {a2l2_axi_0/inst/stq_count_q_reg[1]} {a2l2_axi_0/inst/stq_count_q_reg[0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list a2l2_axi_0_an_ac_reld_crit_qw]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list a2l2_axi_0_an_ac_reld_data_vld]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list a2l2_axi_0_an_ac_req_ld_pop]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list a2l2_axi_0_an_ac_req_st_pop]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list c_wrapper_0_ac_an_req]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 1 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list c_wrapper_0_ac_an_req_wimg_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 1 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/icd_icm_miss]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 1 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/ics_icd_iu1_flush]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_enable_q]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_pulse_q]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets clk_wiz_0_clk]

rel/build/bd/xdc/main_pinout.xdc

@@ -0,0 +1,5 @@
+set_property IOSTANDARD LVDS [get_ports clk_in1_n_0]
+set_property PACKAGE_PIN AP26 [get_ports clk_in1_p_0]
+set_property PACKAGE_PIN AP27 [get_ports clk_in1_n_0]
+set_property IOSTANDARD LVDS [get_ports clk_in1_p_0]
+

rel/build/bd/xdc/main_spi.xdc

@@ -0,0 +1,14 @@
+## Settings to generate MSC file
+# Configuration from SPI Flash as per XAPP1233
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-1 [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+# Set CFGBVS to GND to match schematics
+set_property CFGBVS GND [current_design]
+# Set CONFIG_VOLTAGE to 1.8V to match schematics
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+# Set safety trigger to power down FPGA at 125degC
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
+

rel/build/bd/xdc/main_timing.xdc

@@ -0,0 +1,4 @@
+create_generated_clock -name clk   [get_pins clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0]
+create_generated_clock -name clk2x [get_pins clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1]
+create_generated_clock -name clk4x [get_pins clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT2]
+

rel/build/ip_user/a2l2_axi/readme.md

@@ -0,0 +1,8 @@
+# create IP: a2l2_axi
+
+```
+$VIVADO -mode tcl -source tcl/create_ip_a2l2_axi.tcl
+rm -r ../../ip_repo/a2l2_axi
+cp -r a2l2_axi ../../ip_repo
+```
+

rel/build/ip_user/a2l2_axi/tcl

@@ -0,0 +1 @@
+../../tcl

rel/build/ip_user/a2l2_axi/verilog

@@ -0,0 +1 @@
+../../../src/vhdl

rel/build/ip_user/a2l2_axi/vhdl

@@ -0,0 +1 @@
+../../../src/vhdl

rel/build/ip_user/a2o_axi_reg/readme.md

@@ -0,0 +1,8 @@
+# create IP: a2o_axi_reg
+
+```
+$VIVADO -mode tcl -source tcl/create_ip_a2o_axi_reg.tcl
+rm -r ../../ip_repo/a2o_axi_reg
+cp -r a2o_axi_reg ../../ip_repo
+```
+

rel/build/ip_user/a2o_axi_reg/tcl

@@ -0,0 +1 @@
+../../tcl

rel/build/ip_user/a2o_axi_reg/verilog

@@ -0,0 +1 @@
+../../../src/vhdl

rel/build/ip_user/a2o_axi_reg/vhdl

@@ -0,0 +1 @@
+../../../src/vhdl

rel/build/ip_user/a2o_core/readme.md

@@ -0,0 +1,8 @@
+# create IP: a2o_core
+
+```
+$VIVADO -mode tcl -source tcl/create_ip_a2o_core.tcl
+rm -r ../../ip_repo/c_wrapper
+cp -r c_wrapper ../../ip_repo
+```
+

rel/build/ip_user/a2o_core/tcl

@@ -0,0 +1 @@
+../../tcl

rel/build/ip_user/a2o_core/verilog

@@ -0,0 +1 @@
+../../../src/verilog

rel/build/ip_user/a2o_core/vhdl

@@ -0,0 +1 @@
+../../../src/vhdl

rel/build/ip_user/a2o_dbug/readme.md

@@ -0,0 +1,8 @@
+# create IP: a2o_dbug
+
+```
+$VIVADO -mode tcl -source tcl/create_ip_a2o_dbug.tcl
+rm -r ../../ip_repo/a2o_dbug
+cp -r a2o_dbug ../../ip_repo
+```
+

rel/build/ip_user/a2o_dbug/tcl

@@ -0,0 +1 @@
+../../tcl

rel/build/ip_user/a2o_dbug/verilog

@@ -0,0 +1 @@
+../../../src/vhdl

rel/build/ip_user/a2o_dbug/vhdl

@@ -0,0 +1 @@
+../../../src/vhdl

rel/build/ip_user/reverserator_3/create_ip.tcl

@@ -0,0 +1,62 @@
+# ip creator 
+
+set project reverserator_3 ;# also top
+set keep 0              ;# keep project
+set xdc ""              ;# set to xdc file if exists
+set synth_check 1
+
+proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} {
+
+   set vhdl_dir [file normalize ./vhdl] 
+   set output_dir .
+   set project_dir ./prj
+
+   create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e
+
+   add_files -norecurse  $vhdl_dir
+
+   update_compile_order -fileset sources_1
+
+   set_property top $project [current_fileset]
+   set_property target_language VHDL [current_project]
+   set_property default_lib work [current_project]
+   set_property top $project [get_filesets sim_1]
+   set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property simulator_language VHDL [current_project]
+
+   if {$xdc != ""} {
+      set xdc_dir [file normalize ./xdc]   
+      read_xdc $xdc_dir/$xdc
+   }
+   
+   update_compile_order -fileset sources_1
+
+   if {$synth_check} {
+      synth_design -rtl -name elab_for_sanity_check
+   }
+   
+   ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
+   ipx::unload_core $output_dir/$project/component.xml
+   ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
+   update_compile_order -fileset sources_1
+   set_property core_revision 2 [ipx::current_core]
+   ipx::update_source_project_archive -component [ipx::current_core]
+   ipx::create_xgui_files [ipx::current_core]
+   ipx::update_checksums [ipx::current_core]
+   ipx::save_core [ipx::current_core]
+   ipx::move_temp_component_back -component [ipx::current_core]
+
+   if {$keep_project} {
+      close_project
+      puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
+   } else {
+      close_project -delete
+      exec rm -rf $output_dir/$project_dir
+      puts "Project built; only IP files kept."
+   }
+
+}
+
+create_ip $project $keep $synth_check $xdc
+

rel/build/ip_user/reverserator_3/readme.md

@@ -0,0 +1,8 @@
+# create IP: reverserator_3
+
+```
+$VIVADO -mode tcl -source ./create_ip.tcl
+rm -r ../../ip_repo/reverserator_3
+cp -r reverserator_3 ../../ip_repo
+```
+

rel/build/ip_user/reverserator_3/vhdl/reverserator_3.vhdl

@@ -0,0 +1,48 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+-- terminate yet another rare xil bug 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity reverserator_3 is
+	port (
+		outdoor : in  std_logic_vector(0 to 2);
+		inndoor : out std_logic_vector(2 downto 0)
+	);
+end reverserator_3;
+
+architecture reverserator_3 of reverserator_3 is
+begin
+
+   inndoor <= outdoor;
+
+end reverserator_3;
+

rel/build/ip_user/reverserator_4/create_ip.tcl

@@ -0,0 +1,62 @@
+# ip creator 
+
+set project reverserator_4 ;# also top
+set keep 0              ;# keep project
+set xdc ""              ;# set to xdc file if exists
+set synth_check 1
+
+proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} {
+
+   set vhdl_dir [file normalize ./vhdl] 
+   set output_dir .
+   set project_dir ./prj
+
+   create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e
+
+   add_files -norecurse  $vhdl_dir
+
+   update_compile_order -fileset sources_1
+
+   set_property top $project [current_fileset]
+   set_property target_language VHDL [current_project]
+   set_property default_lib work [current_project]
+   set_property top $project [get_filesets sim_1]
+   set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property simulator_language VHDL [current_project]
+
+   if {$xdc != ""} {
+      set xdc_dir [file normalize ./xdc]   
+      read_xdc $xdc_dir/$xdc
+   }
+   
+   update_compile_order -fileset sources_1
+
+   if {$synth_check} {
+      synth_design -rtl -name elab_for_sanity_check
+   }
+   
+   ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
+   ipx::unload_core $output_dir/$project/component.xml
+   ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
+   update_compile_order -fileset sources_1
+   set_property core_revision 2 [ipx::current_core]
+   ipx::update_source_project_archive -component [ipx::current_core]
+   ipx::create_xgui_files [ipx::current_core]
+   ipx::update_checksums [ipx::current_core]
+   ipx::save_core [ipx::current_core]
+   ipx::move_temp_component_back -component [ipx::current_core]
+
+   if {$keep_project} {
+      close_project
+      puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
+   } else {
+      close_project -delete
+      exec rm -rf $output_dir/$project_dir
+      puts "Project built; only IP files kept."
+   }
+
+}
+
+create_ip $project $keep $synth_check $xdc
+

rel/build/ip_user/reverserator_4/readme.md

@@ -0,0 +1,8 @@
+# create IP: reverserator_4
+
+```
+$VIVADO -mode tcl -source ./create_ip.tcl
+rm -r ../../ip_repo/reverserator_4
+cp -r reverserator_4 ../../ip_repo
+```
+

rel/build/ip_user/reverserator_4/vhdl/reverserator_4.vhdl

@@ -0,0 +1,48 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+-- terminate yet another rare xil bug 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity reverserator_4 is
+	port (
+		innnie : in  std_logic_vector(0 to 3);
+		outtie : out std_logic_vector(3 downto 0)
+	);
+end reverserator_4;
+
+architecture reverserator_4 of reverserator_4 is
+begin
+
+   outtie <= innnie;
+
+end reverserator_4;
+

rel/build/ip_user/reverserator_64/create_ip.tcl

@@ -0,0 +1,62 @@
+# ip creator 
+
+set project reverserator_64 ;# also top
+set keep 0              ;# keep project
+set xdc ""              ;# set to xdc file if exists
+set synth_check 1
+
+proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} {
+
+   set vhdl_dir [file normalize ./vhdl] 
+   set output_dir .
+   set project_dir ./prj
+
+   create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e
+
+   add_files -norecurse  $vhdl_dir
+
+   update_compile_order -fileset sources_1
+
+   set_property top $project [current_fileset]
+   set_property target_language VHDL [current_project]
+   set_property default_lib work [current_project]
+   set_property top $project [get_filesets sim_1]
+   set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property simulator_language VHDL [current_project]
+
+   if {$xdc != ""} {
+      set xdc_dir [file normalize ./xdc]   
+      read_xdc $xdc_dir/$xdc
+   }
+   
+   update_compile_order -fileset sources_1
+
+   if {$synth_check} {
+      synth_design -rtl -name elab_for_sanity_check
+   }
+   
+   ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
+   ipx::unload_core $output_dir/$project/component.xml
+   ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
+   update_compile_order -fileset sources_1
+   set_property core_revision 2 [ipx::current_core]
+   ipx::update_source_project_archive -component [ipx::current_core]
+   ipx::create_xgui_files [ipx::current_core]
+   ipx::update_checksums [ipx::current_core]
+   ipx::save_core [ipx::current_core]
+   ipx::move_temp_component_back -component [ipx::current_core]
+
+   if {$keep_project} {
+      close_project
+      puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
+   } else {
+      close_project -delete
+      exec rm -rf $output_dir/$project_dir
+      puts "Project built; only IP files kept."
+   }
+
+}
+
+create_ip $project $keep $synth_check $xdc
+

rel/build/ip_user/reverserator_64/readme.md

@@ -0,0 +1,8 @@
+# create IP: reverserator_64
+
+```
+$VIVADO -mode tcl -source ./create_ip.tcl
+rm -r ../../ip_repo/reverserator_64
+cp -r reverserator_64 ../../ip_repo
+```
+

rel/build/ip_user/reverserator_64/vhdl/reverserator_64.vhdl

@@ -0,0 +1,48 @@
+-- © IBM Corp. 2020
+-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+-- the terms below; you may not use the files in this repository except in
+-- compliance with the License as modified.
+-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Modified Terms:
+--
+--    1) For the purpose of the patent license granted to you in Section 3 of the
+--    License, the "Work" hereby includes implementations of the work of authorship
+--    in physical form.
+--
+--    2) Notwithstanding any terms to the contrary in the License, any licenses
+--    necessary for implementation of the Work that are available from OpenPOWER
+--    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+--    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+--    of the EULA.  
+--
+-- Unless required by applicable law or agreed to in writing, the reference design
+-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+-- for the specific language governing permissions and limitations under the License.
+-- 
+-- Additional rights, including the ability to physically implement a softcore that
+-- is compliant with the required sections of the Power ISA Specification, are
+-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+-- terminate yet another rare xil bug 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity reverserator_64 is
+	port (
+		parkavenue : in  std_logic_vector(0 to 63);
+		skidrowwww : out std_logic_vector(63 downto 0)
+	);
+end reverserator_64;
+
+architecture reverserator_64 of reverserator_64 is
+begin
+
+   skidrowwww <= parkavenue;
+   
+end reverserator_64;
+

rel/build/tcl/create_ip_a2l2_axi.tcl

@@ -0,0 +1,69 @@
+# ip creator 
+
+set project a2l2_axi    ;# also top
+set keep 0              ;# keep project
+set xdc ""              ;# set to xdc file if exists
+set synth_check 1
+set vhdl2008 1
+
+proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} {
+
+   set vhdl_dir [file normalize ./vhdl] 
+   set output_dir .
+   set project_dir ./prj
+
+   create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e
+
+   add_files -norecurse  $vhdl_dir
+
+   set_property library work    [get_files $vhdl_dir/*]
+   
+   if {$vhdl2008} {
+      set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/*]  
+   }
+
+   update_compile_order -fileset sources_1
+
+   set_property top $project [current_fileset]
+   set_property target_language VHDL [current_project]
+   set_property default_lib work [current_project]
+   set_property top $project [get_filesets sim_1]
+   set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property simulator_language VHDL [current_project]  
+
+   if {$xdc != ""} {
+      set xdc_dir [file normalize ./xdc]   
+      read_xdc $xdc_dir/$xdc
+   }
+   
+   update_compile_order -fileset sources_1
+
+   if {$synth_check} {
+      synth_design -rtl -name elab_for_sanity_check
+   }
+   
+   ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
+   ipx::unload_core $output_dir/$project/component.xml
+   ipx::edit_ip_in_project -upgrade true -name ${project}_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
+   update_compile_order -fileset sources_1
+   set_property core_revision 2 [ipx::current_core]
+   ipx::update_source_project_archive -component [ipx::current_core]
+   ipx::create_xgui_files [ipx::current_core]
+   ipx::update_checksums [ipx::current_core]
+   ipx::save_core [ipx::current_core]
+   ipx::move_temp_component_back -component [ipx::current_core]
+
+   if {$keep_project} {
+      close_project
+      puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
+   } else {
+      close_project -delete
+      exec rm -rf $output_dir/$project_dir
+      puts "Project built; only IP files kept."
+   }
+
+}
+
+create_ip $project $keep $synth_check $xdc $vhdl2008
+

rel/build/tcl/create_ip_a2o_axi_reg.tcl

@@ -0,0 +1,69 @@
+# ip creator 
+
+set project a2o_axi_reg ;# also top
+set keep 0              ;# keep project
+set xdc ""              ;# set to xdc file if exists
+set synth_check 1
+set vhdl2008 1
+
+proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} {
+
+   set vhdl_dir [file normalize ./vhdl] 
+   set output_dir .
+   set project_dir ./prj
+
+   create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e
+
+   add_files -norecurse  $vhdl_dir
+
+   set_property library work    [get_files $vhdl_dir/*]
+   
+   if {$vhdl2008} {
+      set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/*]  
+   }   
+
+   update_compile_order -fileset sources_1
+
+   set_property top $project [current_fileset]
+   set_property target_language VHDL [current_project]
+   set_property default_lib work [current_project]
+   set_property top $project [get_filesets sim_1]
+   set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property simulator_language VHDL [current_project]
+
+   if {$xdc != ""} {
+      set xdc_dir [file normalize ./xdc]   
+      read_xdc $xdc_dir/$xdc
+   }
+   
+   update_compile_order -fileset sources_1
+
+   if {$synth_check} {
+      synth_design -rtl -name elab_for_sanity_check
+   }
+   
+   ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
+   ipx::unload_core $output_dir/$project/component.xml
+   ipx::edit_ip_in_project -upgrade true -name ${project}_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
+   update_compile_order -fileset sources_1
+   set_property core_revision 2 [ipx::current_core]
+   ipx::update_source_project_archive -component [ipx::current_core]
+   ipx::create_xgui_files [ipx::current_core]
+   ipx::update_checksums [ipx::current_core]
+   ipx::save_core [ipx::current_core]
+   ipx::move_temp_component_back -component [ipx::current_core]
+
+   if {$keep_project} {
+      close_project
+      puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
+   } else {
+      close_project -delete
+      exec rm -rf $output_dir/$project_dir
+      puts "Project built; only IP files kept."
+   }
+
+}
+
+create_ip $project $keep $synth_check $xdc $vhdl2008
+

rel/build/tcl/create_ip_a2o_core.tcl

@@ -0,0 +1,61 @@
+# ip creator 
+
+set project c_wrapper   ;# also top
+set rev "1"
+set keep 0              ;# keep project
+set xdc ""              ;# set to xdc file if exists
+set synth_check 1
+
+proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {rev 0.1} } {
+
+   set verilog_dir [file normalize ./verilog] 
+   set output_dir .
+   set project_dir ./prj
+
+   create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e
+
+   add_files -norecurse $verilog_dir/trilib
+   add_files -norecurse $verilog_dir/work
+
+   update_compile_order -fileset sources_1
+
+   set_property top $project [current_fileset]
+   set_property target_language VERILOG [current_project]
+   set_property top $project [get_filesets sim_1]
+   set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property simulator_language MIXED [current_project]  
+   
+   if {$xdc != ""} {
+      set xdc_dir [file normalize ./xdc]   
+      read_xdc $xdc_dir/$xdc
+   }
+   
+   update_compile_order -fileset sources_1
+
+   if {$synth_check} {
+      synth_design -rtl -name elab_for_sanity_check
+   }
+   
+   ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
+   ipx::unload_core $output_dir/$project/component.xml
+   ipx::edit_ip_in_project -upgrade true -name a2o_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
+   update_compile_order -fileset sources_1
+   set_property core_revision $rev [ipx::current_core]
+   ipx::update_source_project_archive -component [ipx::current_core]
+   ipx::create_xgui_files [ipx::current_core]
+   ipx::update_checksums [ipx::current_core]
+   ipx::save_core [ipx::current_core]
+   ipx::move_temp_component_back -component [ipx::current_core]
+
+   if {$keep_project} {
+      close_project
+      puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
+   } else {
+      close_project -delete
+      exec rm -rf $output_dir/$project_dir
+      puts "Project built; only IP files kept."
+   }
+
+}
+
+create_ip $project $keep $synth_check $xdc $rev

rel/build/tcl/create_ip_a2o_dbug.tcl

@@ -0,0 +1,69 @@
+# ip creator 
+
+set project a2o_dbug    ;# also top
+set keep 0              ;# keep project
+set xdc ""              ;# set to xdc file if exists
+set synth_check 1
+set vhdl2008 1
+
+proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} {
+
+   set vhdl_dir [file normalize ./vhdl] 
+   set output_dir .
+   set project_dir ./prj
+
+   create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e
+
+   add_files -norecurse $vhdl_dir
+
+   set_property library work [get_files $vhdl_dir/*]
+   
+   if {$vhdl2008} {
+      set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/*]  
+   }
+
+   update_compile_order -fileset sources_1
+
+   set_property top $project [current_fileset]
+   set_property target_language VHDL [current_project]
+   set_property default_lib work [current_project]
+   set_property top $project [get_filesets sim_1]
+   set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
+   set_property simulator_language VHDL [current_project]  
+
+   if {$xdc != ""} {
+      set xdc_dir [file normalize ./xdc]   
+      read_xdc $xdc_dir/$xdc
+   }
+   
+   update_compile_order -fileset sources_1
+
+   if {$synth_check} {
+      synth_design -rtl -name elab_for_sanity_check
+   }
+   
+   ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
+   ipx::unload_core $output_dir/$project/component.xml
+   ipx::edit_ip_in_project -upgrade true -name ${project}_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
+   update_compile_order -fileset sources_1
+   set_property core_revision 2 [ipx::current_core]
+   ipx::update_source_project_archive -component [ipx::current_core]
+   ipx::create_xgui_files [ipx::current_core]
+   ipx::update_checksums [ipx::current_core]
+   ipx::save_core [ipx::current_core]
+   ipx::move_temp_component_back -component [ipx::current_core]
+
+   if {$keep_project} {
+      close_project
+      puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
+   } else {
+      close_project -delete
+      exec rm -rf $output_dir/$project_dir
+      puts "Project built; only IP files kept."
+   }
+
+}
+
+create_ip $project $keep $synth_check $xdc $vhdl2008
+

rel/fpga/init.tcl

@@ -0,0 +1,14 @@
+# init.tcl
+#
+
+set TCL [file dirname [info script]] 
+
+proc include {f} {
+   global TCL
+   source -notrace [file join $TCL $f]
+}
+
+include "utils.tcl"
+include "waimea.tcl"
+
+

rel/fpga/utils.tcl

@@ -0,0 +1,26 @@
+# utils.tcl
+#
+
+proc timestamp {{t ""}} {
+   if {$t == ""} {
+      set t [clock seconds]
+   }
+   return [clock format $t -format %y%m%d%H%M%S]
+}
+
+proc datetime {{t ""}} {
+   if {$t == ""} {
+      set t [clock seconds]
+   }
+   return [clock format $t -format "%m-%d-%y %I:%M:%S %p %Z"]
+}
+
+proc now {} {
+   return [clock seconds]
+}
+
+proc vivado_year {} {
+   regexp -- {Vivado v(\d\d\d\d)\.*} [version] s year
+   return $year
+}
+

rel/fpga/waimea.tcl

@@ -0,0 +1,179 @@
+# waimea board/core command interface
+
+
+####################################################################
+# system commands 
+
+set version 1 ;#coremark_1
+
+proc reset {} {
+global version
+
+   if {$version == 1} {
+     set filter "CELL_NAME=~\"*vio*\""   
+     set probe "vio_0_probe_out1"
+   } else {
+     set filter "CELL_NAME=~\"*marvio*\""
+     set probe "vio_0_probe_out1"
+   }
+
+   set obj_vio [get_hw_vios -of_objects [get_hw_devices xcvu3p_0] -filter $filter]
+   set rst [get_hw_probes a2x_axi_bd_i/vio_0_probe_out1 -of_objects $obj_vio]
+   startgroup
+   set_property OUTPUT_VALUE 0 $rst
+   commit_hw_vio $rst
+   endgroup
+   startgroup
+   set_property OUTPUT_VALUE 1 $rst
+   commit_hw_vio $rst
+   endgroup
+   puts "[datetime] Reset"
+}
+
+proc threadstop {{val F}} {
+global version
+
+   if {$version == 1} {
+     set filter "CELL_NAME=~\"*vio*\""   
+     set probe "vio_0_probe_out0"
+   } else {
+     set filter "CELL_NAME=~\"*marvio*\""
+     set probe "marvio_probe_out0"
+   }
+
+   set obj_vio [get_hw_vios -of_objects [get_hw_devices xcvu3p_0] -filter $filter]
+   set thread_stop [get_hw_probes a2x_axi_bd_i/$probe -of_objects $obj_vio]
+   set_property OUTPUT_VALUE $val $thread_stop
+   commit_hw_vio $thread_stop
+   puts "[datetime] ThreadStop=$val"
+}
+
+####################################################################
+# ila commands
+
+proc ila_arm {{n 0}} {
+  set filter "CELL_NAME=~\"u_ila_$n\""
+  set res [run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]]
+  puts "[datetime] ILA$n armed."
+}
+
+proc ila_wait {{n 0}} {
+  set filter "CELL_NAME=~\"u_ila_$n\""
+  puts "[datetime] ILA$n waiting..."
+  set res [wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]]
+  display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]]
+  puts "[datetime] ILA$n triggered."
+}
+
+####################################################################
+# axi slave commands
+
+proc raxi {addr {len 8} {dev 0} {width 8}} {
+
+  if {$dev == 0} {
+    set dev [get_hw_axis hw_axi_1]
+  }
+
+  create_hw_axi_txn -f raxi_txn $dev -address $addr -len $len -type read
+  run_hw_axi -quiet raxi_txn
+  set res [report_hw_axi_txn -w $width raxi_txn]
+  return $res 
+
+}
+
+proc waxi {addr data {len 8} {dev 0}} {
+
+  if {$dev == 0} {
+    set dev [get_hw_axis hw_axi_1]
+  }
+
+  create_hw_axi_txn -f waxi_txn $dev -address $addr -len $len -type write -data $data
+  run_hw_axi -quiet waxi_txn
+  set res [report_hw_axi_txn waxi_txn]
+  return $res 
+
+}
+
+proc waxiq {addr data {len 8} {dev 0}} {
+
+  set res [waxi $addr $data $len $dev]
+
+}
+
+
+proc testwrites {addr xfers} {
+
+  set start [datetime]
+  for {set i 0} {$i < $xfers} {incr i} {
+    waxi $addr 00000000_11111111_22222222_33333333_44444444_55555555_66666666_77777777
+  }
+  set end [datetime]
+
+  puts "Finished $xfers 32B writes."
+  puts "Start: $start"
+  puts "  End: $end"
+
+}
+
+proc testwrites_128B {addr xfers} {
+
+  set start [datetime]
+  for {set i 0} {$i < $xfers} {incr i} {
+    waxi $addr {
+         00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007
+         00000008 00000009 0000000A 0000000B 0000000C 0000000D 0000000E 0000000F
+         00000010 00000011 00000012 00000013 00000014 00000015 00000006 00000017
+         00000018 00000019 0000001A 0000001B 0000001C 0000001D 0000000E 0000001F
+               } 32
+  }
+  set end [datetime]
+
+  puts "Finished $xfers 122B writes."
+  puts "Start: $start"
+  puts "  End: $end"
+
+}
+
+proc map {lambda list} {
+  set res {}
+  foreach i $list {
+     lappend res [apply $lambda $i]
+  }
+  return $res
+}
+
+proc bytereverse {x} {
+   set res ""
+   for {set i 0} {$i < [string length $x]} {incr i 2} {
+     set res "[string range $x $i [expr $i+1]]$res"
+   }
+   return $res
+}
+
+proc ascii {start {len 32} {dev 0}} {
+  set w 128
+  set res ""
+  set count [expr ($len-1)/$w + 1]
+  set ptr $start
+
+  for {set i 0} {$i < $count} {incr i} {
+
+    set mem [raxi $ptr [expr $w/4] $dev $w]
+    set ptr [format %x [expr [expr 0x$ptr] + $w]]
+
+    # split and remove addr
+    set tokens [regexp -all -inline {\S+} $mem]
+    set tokens [lrange $tokens 1 end]
+
+    # bytereverse and ascii
+    set tokens [map {x {return [bytereverse $x]}} $tokens]
+    set bytes [join $tokens {}]
+    set chars [binary format H* $bytes]
+
+    set res "$res$chars"
+
+  }
+  return $res
+}
+
+

rel/src/verilog/trilib/tri.vh

@@ -0,0 +1,43 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+// *!****************************************************************
+// *! FILENAME    : tri_a2o.param
+// *! DESCRIPTION : Constants for use throughout core
+// *! CONTENTS    :
+// *!
+// *!****************************************************************
+
+`ifndef _tri_vh_
+`define _tri_vh_
+
+`define  NCLK_WIDTH  6   // 0  1xClk, 1  Reset, 2  2xClk, 3  4xClk,  4  Even .5xClk,  5 Odd .5x Clk
+//`define  EXPAND_TYPE  1
+
+// Do NOT add any defines below this line
+`endif  //_tri_vh_

rel/src/verilog/trilib/tri_128x168_1w_0.v

@@ -0,0 +1,258 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_128x168_1w_0.v
+// *! DESCRIPTION : 128 Entry x 168 bit x 1 way array
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_128x168_1w_0(
+   gnd,
+   vdd,
+   vcs,
+   nclk,
+   act,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   abst_scan_in,
+   repr_scan_in,
+   time_scan_in,
+   abst_scan_out,
+   repr_scan_out,
+   time_scan_out,
+   lcb_d_mode_dc,
+   lcb_clkoff_dc_b,
+   lcb_act_dis_dc,
+   lcb_mpw1_dc_b,
+   lcb_mpw2_dc_b,
+   lcb_delay_lclkr_dc,
+   lcb_sg_1,
+   lcb_time_sg_0,
+   lcb_repr_sg_0,
+   lcb_abst_sl_thold_0,
+   lcb_repr_sl_thold_0,
+   lcb_time_sl_thold_0,
+   lcb_ary_nsl_thold_0,
+   lcb_bolt_sl_thold_0,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_en_1,
+   din_abist,
+   abist_cmp_en,
+   abist_raw_b_dc,
+   data_cmp_abist,
+   addr_abist,
+   r_wb_abist,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   write_enable,
+   addr,
+   data_in,
+   data_out
+);
+   parameter                                    addressable_ports = 128;	// number of addressable register in this array
+   parameter                                    addressbus_width = 7;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+   parameter                                    port_bitwidth = 168;		// bitwidth of ports
+   parameter                                    ways = 1;                       // number of ways
+
+   // POWER PINS
+   inout                                        gnd;
+   inout                                        vdd;
+   inout                                        vcs;
+
+   // CLOCK and CLOCKCONTROL ports
+   input [0:`NCLK_WIDTH-1]                      nclk;
+   input                                        act;
+   input                                        ccflush_dc;
+   input                                        scan_dis_dc_b;
+   input                                        scan_diag_dc;
+
+   input                                        abst_scan_in;
+   input                                        repr_scan_in;
+   input                                        time_scan_in;
+   output                                       abst_scan_out;
+   output                                       repr_scan_out;
+   output                                       time_scan_out;
+
+   input                                        lcb_d_mode_dc;
+   input                                        lcb_clkoff_dc_b;
+   input                                        lcb_act_dis_dc;
+   input [0:4]                                  lcb_mpw1_dc_b;
+   input                                        lcb_mpw2_dc_b;
+   input [0:4]                                  lcb_delay_lclkr_dc;
+
+   input                                        lcb_sg_1;
+   input                                        lcb_time_sg_0;
+   input                                        lcb_repr_sg_0;
+
+   input                                        lcb_abst_sl_thold_0;
+   input                                        lcb_repr_sl_thold_0;
+   input                                        lcb_time_sl_thold_0;
+   input                                        lcb_ary_nsl_thold_0;
+   input                                        lcb_bolt_sl_thold_0;		// thold for any regs inside backend
+
+   input                                        tc_lbist_ary_wrt_thru_dc;
+   input                                        abist_en_1;
+   input [0:3]                                  din_abist;
+   input                                        abist_cmp_en;
+   input                                        abist_raw_b_dc;
+   input [0:3]                                  data_cmp_abist;
+   input [0:6]                                  addr_abist;
+   input                                        r_wb_abist;
+
+   // BOLT-ON
+   input                                        pc_bo_enable_2;		// general bolt-on enable, probably DC
+   input                                        pc_bo_reset;		// execute sticky bit decode
+   input                                        pc_bo_unload;
+   input                                        pc_bo_repair;		// load repair reg
+   input                                        pc_bo_shdata;		// shift data for timing write
+   input                                        pc_bo_select;		// select for mask and hier writes
+   output                                       bo_pc_failout;		// fail/no-fix reg
+   output                                       bo_pc_diagloop;
+   input                                        tri_lcb_mpw1_dc_b;
+   input                                        tri_lcb_mpw2_dc_b;
+   input                                        tri_lcb_delay_lclkr_dc;
+   input                                        tri_lcb_clkoff_dc_b;
+   input                                        tri_lcb_act_dis_dc;
+
+   // PORTS
+   input                                        write_enable;
+   input [0:addressbus_width-1]                 addr;
+   input [0:port_bitwidth-1]                    data_in;
+   output [0:port_bitwidth-1]                   data_out;
+
+   // tri_128x168_1w_0
+
+   parameter                                    ramb_base_width = 36;
+   parameter                                    ramb_base_addr = 9;
+   parameter                                    ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1;		// # of RAMB's per way
+
+
+   // Configuration Statement for NCsim
+   //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
+
+   wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in;
+   wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1];
+   wire [0:ramb_base_addr-1]                    ramb_addr;
+
+   wire [0:ways-1]                              write;
+   wire                                         tidn;
+   (* analysis_not_referenced="true" *)
+   wire                                         unused;
+   wire [0:(ramb_base_width*ramb_width_mult-1)] unused_dob;
+
+
+   generate
+   begin
+     assign tidn = 1'b0;
+
+     if (addressbus_width < ramb_base_addr)
+     begin
+       assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
+       assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr;
+     end
+     if (addressbus_width >= ramb_base_addr)
+     begin
+       assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
+     end
+
+     genvar  i;
+     for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1)
+     begin : din
+       if (i < port_bitwidth)
+       begin
+         assign ramb_data_in[i] = data_in[i];
+       end
+       if (i >= port_bitwidth)
+       begin
+         assign ramb_data_in[i] = 1'b0;
+       end
+     end
+
+     genvar  w;
+     for (w = 0; w < ways; w = w + 1)
+     begin : aw
+       assign write[w] = write_enable;
+
+       genvar  x;
+       for (x = 0; x < ramb_width_mult; x = x + 1)
+       begin : ax
+
+         RAMB16_S36_S36
+            #(.SIM_COLLISION_CHECK("NONE"))     // all, none, warning_only, generate_x_only
+         ram(
+               .DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
+               .DOB(unused_dob[x * ramb_base_width:x * ramb_base_width + 31]),
+               .DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .ADDRA(ramb_addr),
+               .ADDRB(ramb_addr),
+               .CLKA(nclk[0]),
+               .CLKB(tidn),
+               .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
+               .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
+               .DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .ENA(act),
+               .ENB(tidn),
+               .SSRA(nclk[1]),
+               .SSRB(tidn),
+               .WEA(write[w]),
+               .WEB(tidn)
+            );
+       end  //ax
+       assign data_out[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
+     end  //aw
+   end
+   endgenerate
+
+   assign abst_scan_out = abst_scan_in;
+   assign repr_scan_out = repr_scan_in;
+   assign time_scan_out = time_scan_in;
+
+   assign bo_pc_failout = 1'b0;
+   assign bo_pc_diagloop = 1'b0;
+
+   assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, nclk, unused_dob});
+endmodule

rel/src/verilog/trilib/tri_128x16_1r1w_1.v

@@ -0,0 +1,335 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+//*****************************************************************************
+//  Description:  Tri Array Wrapper
+//
+//*****************************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_128x16_1r1w_1(
+   vdd,
+   vcs,
+   gnd,
+   nclk,
+   rd_act,
+   wr_act,
+   lcb_d_mode_dc,
+   lcb_clkoff_dc_b,
+   lcb_mpw1_dc_b,
+   lcb_mpw2_dc_b,
+   lcb_delay_lclkr_dc,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   func_scan_in,
+   func_scan_out,
+   lcb_sg_0,
+   lcb_sl_thold_0_b,
+   lcb_time_sl_thold_0,
+   lcb_abst_sl_thold_0,
+   lcb_ary_nsl_thold_0,
+   lcb_repr_sl_thold_0,
+   time_scan_in,
+   time_scan_out,
+   abst_scan_in,
+   abst_scan_out,
+   repr_scan_in,
+   repr_scan_out,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   wr_abst_act,
+   abist_rd0_adr,
+   rd0_abst_act,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   bw,
+   wr_adr,
+   rd_adr,
+   di,
+   do
+);
+   parameter                                      addressable_ports = 128;	// number of addressable register in this array
+   parameter                                      addressbus_width = 7;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+   parameter                                      port_bitwidth = 16;		// bitwidth of ports
+   parameter                                      ways = 1;                     // number of ways
+
+   // POWER PINS
+   inout                                          vdd;
+   inout                                          vcs;
+   inout                                          gnd;
+
+   input [0:`NCLK_WIDTH-1]                        nclk;
+
+   input                                          rd_act;
+   input                                          wr_act;
+
+   // DC TEST PINS
+   input                                          lcb_d_mode_dc;
+   input                                          lcb_clkoff_dc_b;
+   input [0:4]                                    lcb_mpw1_dc_b;
+   input                                          lcb_mpw2_dc_b;
+   input [0:4]                                    lcb_delay_lclkr_dc;
+
+   input                                          ccflush_dc;
+   input                                          scan_dis_dc_b;
+   input                                          scan_diag_dc;
+   input                                          func_scan_in;
+   output                                         func_scan_out;
+
+   input                                          lcb_sg_0;
+   input                                          lcb_sl_thold_0_b;
+   input                                          lcb_time_sl_thold_0;
+   input                                          lcb_abst_sl_thold_0;
+   input                                          lcb_ary_nsl_thold_0;
+   input                                          lcb_repr_sl_thold_0;
+   input                                          time_scan_in;
+   output                                         time_scan_out;
+   input                                          abst_scan_in;
+   output                                         abst_scan_out;
+   input                                          repr_scan_in;
+   output                                         repr_scan_out;
+
+   input [0:3]                                    abist_di;
+   input                                          abist_bw_odd;
+   input                                          abist_bw_even;
+   input [0:6]                                    abist_wr_adr;
+   input                                          wr_abst_act;
+   input [0:6]                                    abist_rd0_adr;
+   input                                          rd0_abst_act;
+   input                                          tc_lbist_ary_wrt_thru_dc;
+   input                                          abist_ena_1;
+   input                                          abist_g8t_rd0_comp_ena;
+   input                                          abist_raw_dc_b;
+   input [0:3]                                    obs0_abist_cmp;
+
+   // BOLT-ON
+   input                                          lcb_bolt_sl_thold_0;
+   input                                          pc_bo_enable_2;	// general bolt-on enable
+   input                                          pc_bo_reset;		// reset
+   input                                          pc_bo_unload;		// unload sticky bits
+   input                                          pc_bo_repair;		// execute sticky bit decode
+   input                                          pc_bo_shdata;		// shift data for timing write and diag loop
+   input                                          pc_bo_select;		// select for mask and hier writes
+   output                                         bo_pc_failout;	// fail/no-fix reg
+   output                                         bo_pc_diagloop;
+   input                                          tri_lcb_mpw1_dc_b;
+   input                                          tri_lcb_mpw2_dc_b;
+   input                                          tri_lcb_delay_lclkr_dc;
+   input                                          tri_lcb_clkoff_dc_b;
+   input                                          tri_lcb_act_dis_dc;
+
+   input [0:15]                                   bw;
+   input [0:6]                                    wr_adr;
+   input [0:6]                                    rd_adr;
+   input [0:15]                                   di;
+
+   output [0:15]                                  do;
+
+   // tri_128x16_1r1w_1
+
+   // Configuration Statement for NCsim
+   //for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36;
+
+   wire                                           clk;
+   wire                                           clk2x;
+   wire [0:8]                                     b0addra;
+   wire [0:8]                                     b0addrb;
+   wire                                           wea;
+   wire                                           web;
+   wire                                           wren_a;
+   // Latches
+   reg                                            reset_q;
+   reg                                            gate_fq;
+   wire                                           gate_d;
+   wire [0:35]                                    r_data_out_1_d;
+   reg [0:35]                                     r_data_out_1_fq;
+   wire [0:35]                                    w_data_in_0;
+
+   wire [0:35]                                    r_data_out_0_bram;
+   wire [0:35]                                    r_data_out_1_bram;
+
+   wire                                           toggle_d;
+   reg                                            toggle_q;
+   wire                                           toggle2x_d;
+   reg                                            toggle2x_q;
+
+   (* analysis_not_referenced="true" *)
+   wire                                           unused;
+
+     assign clk = nclk[0];
+     assign clk2x = nclk[2];
+
+
+     always @(posedge clk)
+     begin: rlatch
+       reset_q <= nclk[1];
+     end
+
+     //
+     //  NEW clk2x gate logic start
+     //
+
+     always @(posedge nclk[0])
+     begin: tlatch
+       if (reset_q == 1'b1)
+         toggle_q <= 1'b1;
+       else
+         toggle_q <= toggle_d;
+     end
+
+
+     always @(posedge nclk[2])
+     begin: flatch
+       toggle2x_q <= toggle2x_d;
+       gate_fq <= gate_d;
+       r_data_out_1_fq <= r_data_out_1_d;
+     end
+
+     assign toggle_d = (~toggle_q);
+     assign toggle2x_d = toggle_q;
+
+     // should force gate_fq to be on during odd 2x clock (second half of 1x clock).
+     //gate_d <= toggle_q xor toggle2x_q;
+     // if you want the first half do the following
+     assign gate_d = (~(toggle_q ^ toggle2x_q));
+
+     assign b0addra[2:8] = wr_adr;
+     assign b0addrb[2:8] = rd_adr;
+
+     // Unused Address Bits
+     assign b0addra[0:1] = 2'b00;
+     assign b0addrb[0:1] = 2'b00;
+
+     // port a is a read-modify-write port
+     assign wren_a = ((bw != 16'b0000000000000000 & wr_act == 1'b1)) ? 1'b1 :
+                     1'b0;
+     assign wea = wren_a & (~(gate_fq));		// write in 2nd half of nclk
+     assign web = 1'b0;
+     assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] :
+                             r_data_out_0_bram[0];
+     assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] :
+                             r_data_out_0_bram[1];
+     assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] :
+                             r_data_out_0_bram[2];
+     assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] :
+                             r_data_out_0_bram[3];
+     assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] :
+                             r_data_out_0_bram[4];
+     assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] :
+                             r_data_out_0_bram[5];
+     assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] :
+                             r_data_out_0_bram[6];
+     assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] :
+                             r_data_out_0_bram[7];
+     assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] :
+                             r_data_out_0_bram[8];
+     assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] :
+                             r_data_out_0_bram[9];
+     assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] :
+                             r_data_out_0_bram[10];
+     assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] :
+                             r_data_out_0_bram[11];
+     assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] :
+                             r_data_out_0_bram[12];
+     assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] :
+                             r_data_out_0_bram[13];
+     assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] :
+                             r_data_out_0_bram[14];
+     assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] :
+                             r_data_out_0_bram[15];
+     assign w_data_in_0[16:35] = {20{1'b0}};
+
+     assign r_data_out_1_d = r_data_out_1_bram;
+
+
+
+     RAMB16_S36_S36
+                #(.SIM_COLLISION_CHECK("NONE"))            // all, none, warning_only, generate_x_only
+     bram0a(
+               .CLKA(clk2x),
+               .CLKB(clk2x),
+               .SSRA(reset_q),
+               .SSRB(reset_q),
+               .ADDRA(b0addra),
+               .ADDRB(b0addrb),
+               .DIA(w_data_in_0[0:31]),
+               .DIB({32{1'b0}}),
+               .DOA(r_data_out_0_bram[0:31]),
+               .DOB(r_data_out_1_bram[0:31]),
+               .DOPA(r_data_out_0_bram[32:35]),
+               .DOPB(r_data_out_1_bram[32:35]),
+               .DIPA(w_data_in_0[32:35]),
+               .DIPB(4'b0000),
+               .ENA(1'b1),
+               .ENB(1'b1),
+               .WEA(wea),
+               .WEB(web)
+            );
+
+     assign do = r_data_out_1_fq[0:15];
+
+     assign func_scan_out = func_scan_in;
+     assign time_scan_out = time_scan_in;
+     assign abst_scan_out = abst_scan_in;
+     assign repr_scan_out = repr_scan_in;
+
+     assign bo_pc_failout = 1'b0;
+     assign bo_pc_diagloop = 1'b0;
+
+     assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
+                       lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
+                       lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
+                       abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
+                       tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
+                       lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
+                       pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
+                       tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_bram[16:35], r_data_out_1_fq[16:35]};
+endmodule

rel/src/verilog/trilib/tri_128x34_4w_1r1w.v

@@ -0,0 +1,324 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_128x34_4w_1r1w.v
+// *! DESCRIPTION : 128 entry x 34 bit x 4 way array,
+// *!               1 read & 1 write port
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_128x34_4w_1r1w(
+   gnd,
+   vdd,
+   vcs,
+   nclk,
+   rd_act,
+   wr_act,
+   sg_0,
+   abst_sl_thold_0,
+   ary_nsl_thold_0,
+   time_sl_thold_0,
+   repr_sl_thold_0,
+   func_sl_thold_0_b,
+   func_force,
+   clkoff_dc_b,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   d_mode_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   delay_lclkr_dc,
+   wr_abst_act,
+   rd0_abst_act,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   abist_rd0_adr,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp,
+   abst_scan_in,
+   time_scan_in,
+   repr_scan_in,
+   func_scan_in,
+   abst_scan_out,
+   time_scan_out,
+   repr_scan_out,
+   func_scan_out,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   wr_way,
+   wr_addr,
+   data_in,
+   rd_addr,
+   data_out
+);
+   parameter                                    addressable_ports = 128;        // number of addressable register in this array
+   parameter                                    addressbus_width = 7;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+   parameter                                    port_bitwidth = 34;		// bitwidth of ports
+   parameter                                    ways = 4;                       // number of ways
+
+   // POWER PINS
+   inout                                        gnd;
+   inout                                        vdd;
+   (* analysis_not_referenced="true" *)
+   inout                                        vcs;
+   // CLOCK and CLOCKCONTROL ports
+   input [0:`NCLK_WIDTH-1]                      nclk;
+   input                                        rd_act;
+   input                                        wr_act;
+   input                                        sg_0;
+   input                                        abst_sl_thold_0;
+   input                                        ary_nsl_thold_0;
+   input                                        time_sl_thold_0;
+   input                                        repr_sl_thold_0;
+   input                                        func_sl_thold_0_b;
+   input                                        func_force;
+   input                                        clkoff_dc_b;
+   input                                        ccflush_dc;
+   input                                        scan_dis_dc_b;
+   input                                        scan_diag_dc;
+   input                                        d_mode_dc;
+   input [0:4]                                  mpw1_dc_b;
+   input                                        mpw2_dc_b;
+   input [0:4]                                  delay_lclkr_dc;
+   // ABIST
+   input                                        wr_abst_act;
+   input                                        rd0_abst_act;
+   input [0:3]                                  abist_di;
+   input                                        abist_bw_odd;
+   input                                        abist_bw_even;
+   input [0:addressbus_width-1]                 abist_wr_adr;
+   input [0:addressbus_width-1]                 abist_rd0_adr;
+   input                                        tc_lbist_ary_wrt_thru_dc;
+   input                                        abist_ena_1;
+   input                                        abist_g8t_rd0_comp_ena;
+   input                                        abist_raw_dc_b;
+   input [0:3]                                  obs0_abist_cmp;
+   // Scan
+   input [0:1]                                  abst_scan_in;
+   input                                        time_scan_in;
+   input                                        repr_scan_in;
+   input                                        func_scan_in;
+   output [0:1]                                 abst_scan_out;
+   output                                       time_scan_out;
+   output                                       repr_scan_out;
+   output                                       func_scan_out;
+   // BOLT-ON
+   input                                        lcb_bolt_sl_thold_0;
+   input                                        pc_bo_enable_2;		// general bolt-on enable
+   input                                        pc_bo_reset;		// reset
+   input                                        pc_bo_unload;		// unload sticky bits
+   input                                        pc_bo_repair;		// execute sticky bit decode
+   input                                        pc_bo_shdata;		// shift data for timing write and diag loop
+   input [0:1]                                  pc_bo_select;		// select for mask and hier writes
+   output [0:1]                                 bo_pc_failout;		// fail/no-fix reg
+   output [0:1]                                 bo_pc_diagloop;
+   input                                        tri_lcb_mpw1_dc_b;
+   input                                        tri_lcb_mpw2_dc_b;
+   input                                        tri_lcb_delay_lclkr_dc;
+   input                                        tri_lcb_clkoff_dc_b;
+   input                                        tri_lcb_act_dis_dc;
+   // Write Ports
+   input [0:ways-1]                             wr_way;
+   input [0:addressbus_width-1]                 wr_addr;
+   input [0:port_bitwidth*ways-1]               data_in;
+   // Read Ports
+   input [0:addressbus_width-1]                 rd_addr;
+   output [0:port_bitwidth*ways-1]              data_out;
+
+   // tri_128x34_4w_1r1w
+
+   parameter                                    ramb_base_width = 36;
+   parameter                                    ramb_base_addr = 9;
+   parameter                                    ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1;		// # of RAMB's per way
+
+
+   // Configuration Statement for NCsim
+   //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
+
+   localparam          rd_act_offset = 0;
+   localparam          data_out_offset = rd_act_offset + 1;
+   localparam          scan_right = data_out_offset + port_bitwidth*ways - 1;
+
+   wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in[0:ways-1];
+   wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1];
+   wire [0:ramb_base_addr-1]                    ramb_rd_addr;
+   wire [0:ramb_base_addr-1]                    ramb_wr_addr;
+
+   wire                                         rd_act_l2;
+   wire [0:port_bitwidth*ways-1]                data_out_d;
+   wire [0:port_bitwidth*ways-1]                data_out_l2;
+
+   wire                                         tidn;
+   (* analysis_not_referenced="true" *)
+   wire                                         unused;
+   wire [31:0]                                  dob;
+   wire [3:0]                                   dopb;
+   wire [0:scan_right]                          func_sov;
+
+   generate
+   begin
+     assign tidn = 1'b0;
+
+     if (addressbus_width < ramb_base_addr)
+     begin
+       assign ramb_rd_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
+       assign ramb_rd_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = rd_addr;
+
+       assign ramb_wr_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
+       assign ramb_wr_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = wr_addr;
+     end
+     if (addressbus_width >= ramb_base_addr)
+     begin
+       assign ramb_rd_addr = rd_addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
+       assign ramb_wr_addr = wr_addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
+     end
+
+     genvar  w;
+     for (w = 0; w < ways; w = w + 1)
+     begin : dw
+       genvar  i;
+       for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1)
+       begin : din
+         if (i < port_bitwidth)
+         begin
+           assign ramb_data_in[w][i] = data_in[w * port_bitwidth + i];
+         end
+         if (i >= port_bitwidth)
+         begin
+           assign ramb_data_in[w][i] = 1'b0;
+         end
+       end
+     end
+
+     //genvar  w;
+     for (w = 0; w < ways; w = w + 1)
+     begin : aw
+       genvar  x;
+       for (x = 0; x < ramb_width_mult; x = x + 1)
+       begin : ax
+
+         RAMB16_S36_S36
+            #(.SIM_COLLISION_CHECK("NONE"))     // all, none, warning_only, generate_x_only
+         arr(
+               .DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
+               .DOB(dob),
+               .DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .DOPB(dopb),
+               .ADDRA(ramb_rd_addr),
+               .ADDRB(ramb_wr_addr),
+               .CLKA(nclk[0]),
+               .CLKB(nclk[0]),
+               .DIA(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]),
+               .DIB(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]),
+               .DIPA(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .DIPB(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .ENA(rd_act),
+               .ENB(wr_act),
+               .SSRA(nclk[1]),
+               .SSRB(nclk[1]),
+               .WEA(tidn),
+               .WEB(wr_way[w])
+            );
+       end  //ax
+       assign data_out_d[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
+     end  //aw
+   end
+   endgenerate
+
+   assign data_out = data_out_l2;
+
+   tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch(
+      .vd(vdd),
+      .gd(gnd),
+      .nclk(nclk),
+      .act(1'b1),
+      .thold_b(func_sl_thold_0_b),
+      .sg(sg_0),
+      .force_t(func_force),
+      .delay_lclkr(delay_lclkr_dc[0]),
+      .mpw1_b(mpw1_dc_b[0]),
+      .mpw2_b(mpw2_dc_b),
+      .d_mode(d_mode_dc),
+      .scin(1'b0),
+      .scout(func_sov[rd_act_offset]),
+      .din(rd_act),
+      .dout(rd_act_l2)
+   );
+
+   tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch(
+      .vd(vdd),
+      .gd(gnd),
+      .nclk(nclk),
+      .act(rd_act_l2),
+      .thold_b(func_sl_thold_0_b),
+      .sg(sg_0),
+      .force_t(func_force),
+      .delay_lclkr(delay_lclkr_dc[0]),
+      .mpw1_b(mpw1_dc_b[0]),
+      .mpw2_b(mpw2_dc_b),
+      .d_mode(d_mode_dc),
+      .scin({port_bitwidth*ways{1'b0}}),
+      .scout(func_sov[data_out_offset:data_out_offset + (port_bitwidth*ways) - 1]),
+      .din(data_out_d),
+      .dout(data_out_l2)
+   );
+
+   assign abst_scan_out = {tidn, tidn};
+   assign time_scan_out = tidn;
+   assign repr_scan_out = tidn;
+   assign func_scan_out = tidn;
+
+   assign bo_pc_failout = {tidn, tidn};
+   assign bo_pc_diagloop = {tidn, tidn};
+
+   assign unused = | ({nclk[2:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, dob, dopb, func_sov, ramb_data_out[0][34:35], ramb_data_out[1][34:35], ramb_data_out[2][34:35], ramb_data_out[3][34:35]});
+
+endmodule

rel/src/verilog/trilib/tri_144x78_2r4w.v

@@ -0,0 +1,604 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 fs / 1 fs
+
+//*****************************************************************************
+//  Description:  Tri-Lam Array Wrapper
+//
+//*****************************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_144x78_2r4w(
+   // Inputs
+   // Power
+   inout                    vdd,
+   inout                    gnd,
+   // Clock & Scan
+   input [0:`NCLK_WIDTH-1]  nclk,
+
+   //-------------------------------------------------------------------
+   // Pervasive
+   //-------------------------------------------------------------------
+   input                    delay_lclkr_dc,
+   input                    mpw1_dc_b,
+   input                    mpw2_dc_b,
+   input                    func_sl_force,
+   input                    func_sl_thold_0_b,
+   input                    func_slp_sl_force,
+   input                    func_slp_sl_thold_0_b,
+   input                    sg_0,
+   input                    scan_in,
+   output                   scan_out,
+
+   //-------------------------------------------------------------------
+   // Read Port
+   //-------------------------------------------------------------------
+   input                     r_late_en_1,
+   input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1,
+   output [64-`GPR_WIDTH:77] r_data_out_1,
+   input                     r_late_en_2,
+   input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2,
+   output [64-`GPR_WIDTH:77] r_data_out_2,
+
+   //-------------------------------------------------------------------
+   // Write Port
+   //-------------------------------------------------------------------
+   input                     w_late_en_1,
+   input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1,
+   input [64-`GPR_WIDTH:77]  w_data_in_1,
+   input                     w_late_en_2,
+   input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2,
+   input [64-`GPR_WIDTH:77]  w_data_in_2,
+   input                     w_late_en_3,
+   input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3,
+   input [64-`GPR_WIDTH:77]  w_data_in_3,
+   input                     w_late_en_4,
+   input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4,
+   input [64-`GPR_WIDTH:77]  w_data_in_4
+);
+
+   // Configuration Statement for NCsim
+   //for all:RAM64X1D use entity unisim.RAM64X1D;
+
+   parameter                tiup = 1'b1;
+   parameter                tidn = 1'b0;
+
+   //-------------------------------------------------------------------
+   // Signals
+   //-------------------------------------------------------------------
+   reg                       write_en;
+   reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]   write_addr;
+   reg [64-`GPR_WIDTH:77]    write_data;
+   wire [0:(`GPR_POOL*`THREADS-1)/64] write_en_arr;
+   wire [0:5]                write_addr_arr;
+   wire [0:1]                wr_mux_ctrl;
+
+   //-------------------------------------------------------------------
+   // Latch Signals
+   //-------------------------------------------------------------------
+   wire                      w1e_q;
+   wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]  w1a_q;
+   wire [64-`GPR_WIDTH:77]   w1d_q;
+   wire                      w2e_q;
+   wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]  w2a_q;
+   wire [64-`GPR_WIDTH:77]   w2d_q;
+   wire                      w3e_q;
+   wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]  w3a_q;
+   wire [64-`GPR_WIDTH:77]   w3d_q;
+   wire                      w4e_q;
+   wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]  w4a_q;
+   wire [64-`GPR_WIDTH:77]   w4d_q;
+   wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]  r1a_q;
+   wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]  r2a_q;
+   wire [0:5]                read1_addr_arr;
+   wire [0:5]                read2_addr_arr;
+   wire [0:(`GPR_POOL*`THREADS-1)/64] read1_en_arr;
+   wire [0:(`GPR_POOL*`THREADS-1)/64] read2_en_arr;
+   reg [64-`GPR_WIDTH:77]    read1_data;
+   reg [64-`GPR_WIDTH:77]    read2_data;
+   wire [64-`GPR_WIDTH:77]   r1d_array[0:(`GPR_POOL*`THREADS-1)/64];
+   wire [64-`GPR_WIDTH:77]   r2d_array[0:(`GPR_POOL*`THREADS-1)/64];
+   wire [64-`GPR_WIDTH:77]   r1d_d;
+   wire [64-`GPR_WIDTH:77]   r2d_d;
+   wire [64-`GPR_WIDTH:77]   r1d_q;
+   wire [64-`GPR_WIDTH:77]   r2d_q;
+
+    (* analysis_not_referenced="true" *)
+   wire                      unused;
+   wire [64-`GPR_WIDTH:77]   unused_port;
+   wire [64-`GPR_WIDTH:77]   unused_port2;
+
+   //-------------------------------------------------------------------
+   // Scanchain
+   //-------------------------------------------------------------------
+   parameter                w1e_offset = 0;
+   parameter                w1a_offset = w1e_offset + 1;
+   parameter                w1d_offset = w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
+   parameter                w2e_offset = w1d_offset + (`GPR_WIDTH+14);
+   parameter                w2a_offset = w2e_offset + 1;
+   parameter                w2d_offset = w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
+   parameter                w3e_offset = w2d_offset + (`GPR_WIDTH+14);
+   parameter                w3a_offset = w3e_offset + 1;
+   parameter                w3d_offset = w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
+   parameter                w4e_offset = w3d_offset + (`GPR_WIDTH+14);
+   parameter                w4a_offset = w4e_offset + 1;
+   parameter                w4d_offset = w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
+   parameter                r1a_offset = w4d_offset + (`GPR_WIDTH+14);
+   parameter                r2a_offset = r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
+   parameter                r1d_offset = r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
+   parameter                r2d_offset = r1d_offset + (`GPR_WIDTH+14);
+   parameter                scan_right = r2d_offset + (`GPR_WIDTH+14);
+   wire [0:scan_right-1]    siv;
+   wire [0:scan_right-1]    sov;
+
+   generate
+   begin
+
+     // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+     // Read Control
+     // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+     // BYPASS
+
+     assign r1d_d = read1_data;
+
+     assign r2d_d = read2_data;
+
+     assign r_data_out_1 = r1d_q;
+     assign r_data_out_2 = r2d_q;
+
+     // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+     // Write Control
+     // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+     assign wr_mux_ctrl = {nclk[0], nclk[2]};
+
+     always @ ( * )
+     begin
+       write_addr <= #10 ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 :
+                        (wr_mux_ctrl == 2'b01) ? w_addr_in_2 :
+                        (wr_mux_ctrl == 2'b10) ? w_addr_in_3 :
+                                                 w_addr_in_4);
+
+       write_en <= #10 ((wr_mux_ctrl == 2'b00) ? w_late_en_1 :
+                      (wr_mux_ctrl == 2'b01) ? w_late_en_2 :
+                      (wr_mux_ctrl == 2'b10) ? w_late_en_3 :
+                                               w_late_en_4);
+
+       // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+       // Depth Control
+       // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+
+       write_data <= #10 ((wr_mux_ctrl == 2'b00) ? w_data_in_1 :
+                        (wr_mux_ctrl == 2'b01) ? w_data_in_2 :
+                        (wr_mux_ctrl == 2'b10) ? w_data_in_3 :
+                                                 w_data_in_4);
+     end
+
+     if (((`GPR_POOL*`THREADS - 1)/64) == 0)
+     begin : depth1
+       if (`GPR_POOL_ENC+`THREADS_POOL_ENC < 6)
+       begin
+         assign write_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
+         assign read1_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
+         assign read2_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
+       end
+
+       assign write_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = write_addr;
+       assign read1_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r1a_q;
+       assign read2_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r2a_q;
+       assign write_en_arr[0] = write_en;
+       assign read1_en_arr[0] = 1'b1;
+       assign read2_en_arr[0] = 1'b1;
+     end
+
+     if (((`GPR_POOL*`THREADS - 1)/64) != 0)
+     begin : depthMulti
+       assign write_addr_arr = write_addr[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
+       assign read1_addr_arr = r1a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
+       assign read2_addr_arr = r2a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
+
+       genvar  wen;
+       for (wen = 0; wen <= ((`GPR_POOL*`THREADS - 1)/64); wen = wen + 1)
+       begin : wrenGen
+         wire wen_match = wen;
+         assign write_en_arr[wen] = write_en & (write_addr[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match);
+         assign read1_en_arr[wen] = r1a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match;
+         assign read2_en_arr[wen] = r2a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match;
+       end
+     end
+
+     always @( * )
+     begin: rdDataMux
+       reg [64-`GPR_WIDTH:77]      rd1_data;
+       reg [64-`GPR_WIDTH:77]      rd2_data;
+       (* analysis_not_referenced="true" *)
+       integer                     rdArr;
+       rd1_data = {`GPR_WIDTH+14{1'b0}};
+       rd2_data = {`GPR_WIDTH+14{1'b0}};
+
+       for (rdArr = 0; rdArr <= ((`GPR_POOL*`THREADS - 1)/64); rdArr = rdArr + 1)
+       begin
+         rd1_data = (r1d_array[rdArr] & {`GPR_WIDTH+14{read1_en_arr[rdArr]}}) | rd1_data;
+         rd2_data = (r2d_array[rdArr] & {`GPR_WIDTH+14{read2_en_arr[rdArr]}}) | rd2_data;
+       end
+       read1_data <= rd1_data;
+       read2_data <= rd2_data;
+     end
+
+     genvar  depth;
+     for (depth = 0; depth <= ((`GPR_POOL*`THREADS - 1)/64); depth = depth + 1)
+     begin : depth_loop
+       genvar  i;
+       for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1)
+       begin : r1
+         RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_1(
+                  .SPO(unused_port[i]),
+                  .DPO(r1d_array[depth][i]),		// Port A 1-bit data output
+                  .A0(write_addr_arr[5]),		// Port A - Write Address (A0-A5)
+                  .A1(write_addr_arr[4]),
+                  .A2(write_addr_arr[3]),
+                  .A3(write_addr_arr[2]),
+                  .A4(write_addr_arr[1]),
+                  .A5(write_addr_arr[0]),
+                  .D(write_data[i]),                    // Port A 1-bit data input
+                  .DPRA0(read1_addr_arr[5]),		// Port B - Read Address (DPRA0-DPRA5)
+                  .DPRA1(read1_addr_arr[4]),
+                  .DPRA2(read1_addr_arr[3]),
+                  .DPRA3(read1_addr_arr[2]),
+                  .DPRA4(read1_addr_arr[1]),
+                  .DPRA5(read1_addr_arr[0]),
+                  .WCLK(nclk[3]),                       // Port A write clock input : clk4x
+                  .WE(write_en_arr[depth])		// Port A write enable input
+               );
+       end
+
+       //genvar  i;
+       for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1)
+       begin : r2
+         RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_2(
+                  .SPO(unused_port2[i]),
+                  .DPO(r2d_array[depth][i]),		// Port A 1-bit data output
+                  .A0(write_addr_arr[5]),		// Port A - Write Address (A0-A5)
+                  .A1(write_addr_arr[4]),
+                  .A2(write_addr_arr[3]),
+                  .A3(write_addr_arr[2]),
+                  .A4(write_addr_arr[1]),
+                  .A5(write_addr_arr[0]),
+                  .D(write_data[i]),		// Port A 1-bit data input
+                  .DPRA0(read2_addr_arr[5]),		// Port B - Read Address (DPRA0-DPRA5)
+                  .DPRA1(read2_addr_arr[4]),
+                  .DPRA2(read2_addr_arr[3]),
+                  .DPRA3(read2_addr_arr[2]),
+                  .DPRA4(read2_addr_arr[1]),
+                  .DPRA5(read2_addr_arr[0]),
+                  .WCLK(nclk[3]),		// Port A write clock input : clk4x
+                  .WE(write_en_arr[depth])		// Port A write enable input
+               );
+       end
+     end
+   end
+   endgenerate
+
+   //----------------------------------------------------------------------------------------------------------------------------------------
+   // Latches
+   //----------------------------------------------------------------------------------------------------------------------------------------
+
+   tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w1e_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w1e_offset]),
+      .scout(sov[w1e_offset]),
+      .din(w_late_en_1),
+      .dout(w1e_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w1a_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .scout(sov[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .din(w_addr_in_1),
+      .dout(w1a_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w1d_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]),
+      .scout(sov[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]),
+      .din(w_data_in_1[64 - `GPR_WIDTH:77]),
+      .dout(w1d_q)
+   );
+
+   tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w2e_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w2e_offset]),
+      .scout(sov[w2e_offset]),
+      .din(w_late_en_2),
+      .dout(w2e_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w2a_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .scout(sov[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .din(w_addr_in_2),
+      .dout(w2a_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w2d_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]),
+      .scout(sov[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]),
+      .din(w_data_in_2[64 - `GPR_WIDTH:77]),
+      .dout(w2d_q)
+   );
+
+   tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w3e_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w3e_offset]),
+      .scout(sov[w3e_offset]),
+      .din(w_late_en_3),
+      .dout(w3e_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w3a_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .scout(sov[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .din(w_addr_in_3),
+      .dout(w3a_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w3d_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]),
+      .scout(sov[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]),
+      .din(w_data_in_3[64 - `GPR_WIDTH:77]),
+      .dout(w3d_q)
+   );
+
+   tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w4e_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w4e_offset]),
+      .scout(sov[w4e_offset]),
+      .din(w_late_en_4),
+      .dout(w4e_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w4a_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .scout(sov[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .din(w_addr_in_4),
+      .dout(w4a_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w4d_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]),
+      .scout(sov[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]),
+      .din(w_data_in_4[64 - `GPR_WIDTH:77]),
+      .dout(w4d_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r1a_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .scout(sov[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .din(r_addr_in_1),
+      .dout(r1a_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r2a_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .scout(sov[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
+      .din(r_addr_in_2),
+      .dout(r2a_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r1d_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]),
+      .scout(sov[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]),
+      .din(r1d_d),
+      .dout(r1d_q)
+   );
+
+   tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r2d_latch(
+      .nclk(nclk),
+      .vd(vdd),
+      .gd(gnd),
+      .act(tiup),
+      .force_t(func_sl_force),
+      .delay_lclkr(delay_lclkr_dc),
+      .mpw1_b(mpw1_dc_b),
+      .mpw2_b(mpw2_dc_b),
+      .thold_b(func_sl_thold_0_b),
+      .d_mode(1'b0),
+      .sg(sg_0),
+      .scin(siv[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]),
+      .scout(sov[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]),
+      .din(r2d_d),
+      .dout(r2d_q)
+   );
+
+   assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
+   assign scan_out = sov[0];
+
+   assign unused = | {unused_port, unused_port2, func_slp_sl_force, func_slp_sl_thold_0_b};
+endmodule

rel/src/verilog/trilib/tri_256x144_8w_1r1w.v

@@ -0,0 +1,513 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_256x144_8w_1r1w.v
+// *! DESCRIPTION : 256 Entry x 144 bit x 8 way array, 9 bit writeable
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_256x144_8w_1r1w(
+   gnd,
+   vdd,
+   vcs,
+   nclk,
+   rd_act,
+   wr_act,
+   sg_0,
+   abst_sl_thold_0,
+   ary_nsl_thold_0,
+   time_sl_thold_0,
+   repr_sl_thold_0,
+   func_sl_force,
+   func_sl_thold_0_b,
+   g8t_clkoff_dc_b,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   g8t_d_mode_dc,
+   g8t_mpw1_dc_b,
+   g8t_mpw2_dc_b,
+   g8t_delay_lclkr_dc,
+   d_mode_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   delay_lclkr_dc,
+   wr_abst_act,
+   rd0_abst_act,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   abist_rd0_adr,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp,
+   abst_scan_in,
+   time_scan_in,
+   repr_scan_in,
+   func_scan_in,
+   abst_scan_out,
+   time_scan_out,
+   repr_scan_out,
+   func_scan_out,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   wr_way,
+   wr_addr,
+   data_in0,
+   data_in1,
+   rd_addr,
+   data_out
+);
+parameter                                  addressable_ports = 256;		// number of addressable register in this array
+parameter                                  addressbus_width = 8;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+parameter                                  port_bitwidth = 144;		    // bitwidth of ports (per way)
+parameter                                  bit_write_type = 9;		    // gives the number of bits that shares one write-enable; must divide evenly into array
+parameter                                  ways = 8;				    // number of ways
+
+// POWER PINS
+inout                                      gnd;
+inout                                      vdd;
+inout                                      vcs;
+
+// CLOCK and CLOCKCONTROL ports
+input [0:`NCLK_WIDTH-1]                    nclk;
+input [0:7]                                rd_act;
+input [0:7]                                wr_act;
+input                                      sg_0;
+input                                      abst_sl_thold_0;
+input                                      ary_nsl_thold_0;
+input                                      time_sl_thold_0;
+input                                      repr_sl_thold_0;
+input                                      func_sl_force;
+input                                      func_sl_thold_0_b;
+input                                      g8t_clkoff_dc_b;
+input                                      ccflush_dc;
+input                                      scan_dis_dc_b;
+input                                      scan_diag_dc;
+input                                      g8t_d_mode_dc;
+input [0:4]                                g8t_mpw1_dc_b;
+input                                      g8t_mpw2_dc_b;
+input [0:4]                                g8t_delay_lclkr_dc;
+input                                      d_mode_dc;
+input                                      mpw1_dc_b;
+input                                      mpw2_dc_b;
+input                                      delay_lclkr_dc;
+
+// ABIST
+input                                      wr_abst_act;
+input                                      rd0_abst_act;
+input [0:3]                                abist_di;
+input                                      abist_bw_odd;
+input                                      abist_bw_even;
+input [0:addressbus_width-1]               abist_wr_adr;
+input [0:addressbus_width-1]               abist_rd0_adr;
+input                                      tc_lbist_ary_wrt_thru_dc;
+input                                      abist_ena_1;
+input                                      abist_g8t_rd0_comp_ena;
+input                                      abist_raw_dc_b;
+input [0:3]                                obs0_abist_cmp;
+
+// SCAN
+input [0:3]                                abst_scan_in;
+input                                      time_scan_in;
+input                                      repr_scan_in;
+input [0:3]                                func_scan_in;
+output [0:3]                               abst_scan_out;
+output                                     time_scan_out;
+output                                     repr_scan_out;
+output [0:3]                               func_scan_out;
+
+// BOLT-ON
+input                                      lcb_bolt_sl_thold_0;
+input                                      pc_bo_enable_2;		        // general bolt-on enable
+input                                      pc_bo_reset;		            // reset
+input                                      pc_bo_unload;		        // unload sticky bits
+input                                      pc_bo_repair;		        // execute sticky bit decode
+input                                      pc_bo_shdata;		        // shift data for timing write and diag loop
+input [0:3]                                pc_bo_select;		        // select for mask and hier writes
+output [0:3]                               bo_pc_failout;		        // fail/no-fix reg
+output [0:3]                               bo_pc_diagloop;
+input                                      tri_lcb_mpw1_dc_b;
+input                                      tri_lcb_mpw2_dc_b;
+input                                      tri_lcb_delay_lclkr_dc;
+input                                      tri_lcb_clkoff_dc_b;
+input                                      tri_lcb_act_dis_dc;
+
+// FUNCTIONAL PORTS
+input [0:ways-1]                           wr_way;
+input [0:(addressbus_width-1)]             wr_addr;
+input [0:(port_bitwidth-1)]                data_in0;
+input [0:(port_bitwidth-1)]                data_in1;
+input [0:(addressbus_width-1)]             rd_addr;
+output [0:(port_bitwidth*ways-1)]          data_out;
+
+parameter                                  ramb_base_addr = 16;
+parameter                                  dataWidth = ((((port_bitwidth - 1)/36) + 1) * 36) - 1;
+parameter                                  numBytes = (dataWidth/9);
+parameter                                  addresswidth = addressbus_width;
+parameter                                  rd_act_offset = 0;
+parameter                                  data_out_offset = rd_act_offset + ways;
+parameter                                  scan_right = data_out_offset + (port_bitwidth*ways) - 1;
+
+wire [0:dataWidth]                         data_in0_pad;
+wire [0:dataWidth]                         data_in1_pad;
+wire [0:dataWidth]                         data_in_swzl[0:ways-1];
+wire [0:dataWidth]                         p0_data_out_pad[0:ways-1];
+wire [0:dataWidth]                         p1_data_out_pad[0:ways-1];
+wire [0:(dataWidth-(dataWidth)/9)-1]       p0_arr_data_in[0:ways-1];
+wire [0:(dataWidth)/9]                     p0_arr_par_in[0:ways-1];
+wire [0:(dataWidth-(dataWidth)/9)-1]       p1_arr_data_in[0:ways-1];
+wire [0:(dataWidth)/9]                     p1_arr_par_in[0:ways-1];
+wire [0:(dataWidth-(dataWidth)/9)-1]       p0_arr_data_out[0:ways-1];
+wire [0:(dataWidth)/9]                     p0_arr_par_out[0:ways-1];
+wire [0:(dataWidth-(dataWidth)/9)-1]       p1_arr_data_out[0:ways-1];
+wire [0:(dataWidth)/9]                     p1_arr_par_out[0:ways-1];
+wire [0:ramb_base_addr-1]                  ramb_rd_addr;
+wire [0:ramb_base_addr-1]                  ramb_wr_addr;
+wire [0:((((port_bitwidth-1)/36)+1)*4)-1]  p0_wayEn[0:ways-1];
+wire [0:((((port_bitwidth-1)/36)+1)*4)-1]  p1_wayEn[0:ways-1];
+wire [0:(port_bitwidth*ways-1)]            p0_data_out_swzl;
+wire [0:(port_bitwidth*ways-1)]            p1_data_out_swzl;
+wire [0:(port_bitwidth*ways-1)]            data_out_fix;
+wire [0:((port_bitwidth-1)/36)]	           cascadeoutlata;
+wire [0:((port_bitwidth-1)/36)]	           cascadeoutlatb;
+wire [0:((port_bitwidth-1)/36)]	           cascadeoutrega;
+wire [0:((port_bitwidth-1)/36)]	           cascadeoutregb;
+wire [0:ways-1]                            rd_act_d;
+wire [0:ways-1]                            rd_act_q;
+wire [0:(port_bitwidth*ways)-1]            data_out_d;
+wire [0:(port_bitwidth*ways)-1]            data_out_b_q;
+
+wire [0:ways-1]                            my_d1clk;
+wire [0:ways-1]                            my_d2clk;
+wire [0:`NCLK_WIDTH-1]                     my_lclk[0:ways-1];
+wire                                       tiup;
+wire [0:scan_right]                        siv;
+wire [0:scan_right]                        sov;
+
+(* analysis_not_referenced="true" *)
+wire                                       unused;
+
+generate begin
+  // Read/Write Port Address Generate
+  assign ramb_rd_addr[11:15] = 5'b0;
+  assign ramb_wr_addr[11:15] = 5'b0;
+  assign rd_act_d = rd_act;
+  assign tiup     = 1'b1;
+
+  genvar  byte;
+  genvar  way;
+  genvar  bit;
+  for (byte = 0; byte <= numBytes; byte = byte + 1) begin : swzl
+    for (way = 0; way < ways; way = way + 1) begin : perWay
+      if (way < (ways/2)) begin : fhalf
+        assign data_in_swzl[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)] = {data_in0_pad[byte + (0 * (numBytes + 1))], data_in0_pad[byte + (1 * (numBytes + 1))],
+                                                                                 data_in0_pad[byte + (2 * (numBytes + 1))], data_in0_pad[byte + (3 * (numBytes + 1))],
+                                                                                 data_in0_pad[byte + (4 * (numBytes + 1))], data_in0_pad[byte + (5 * (numBytes + 1))],
+                                                                                 data_in0_pad[byte + (6 * (numBytes + 1))], data_in0_pad[byte + (7 * (numBytes + 1))]};
+        assign data_in_swzl[way][(((byte * 8) + byte) + 8)] = data_in0_pad[byte + (8 * (numBytes + 1))];
+      end
+      if (way >= (ways/2)) begin : shalf
+        assign data_in_swzl[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)] = {data_in1_pad[byte + (0 * (numBytes + 1))], data_in1_pad[byte + (1 * (numBytes + 1))],
+                                                                                 data_in1_pad[byte + (2 * (numBytes + 1))], data_in1_pad[byte + (3 * (numBytes + 1))],
+                                                                                 data_in1_pad[byte + (4 * (numBytes + 1))], data_in1_pad[byte + (5 * (numBytes + 1))],
+                                                                                 data_in1_pad[byte + (6 * (numBytes + 1))], data_in1_pad[byte + (7 * (numBytes + 1))]};
+        assign data_in_swzl[way][(((byte * 8) + byte) + 8)] = data_in1_pad[byte + (8 * (numBytes + 1))];
+      end
+    end
+  end
+
+  genvar  t;
+  for (t = 0; t < 11; t = t + 1) begin : rambAddrCalc
+    if (t < (11-addresswidth)) begin
+      assign ramb_rd_addr[t] = 1'b0;
+      assign ramb_wr_addr[t] = 1'b0;
+    end
+    if (t >= (11-addresswidth)) begin
+      assign ramb_rd_addr[t] = rd_addr[t - (11 - addresswidth)];
+      assign ramb_wr_addr[t] = wr_addr[t - (11 - addresswidth)];
+    end
+  end
+
+    for (bit = 0; bit <= dataWidth; bit = bit + 1) begin : dFixUp
+      if (bit < port_bitwidth) begin
+        assign data_in0_pad[bit] = data_in0[bit];
+        assign data_in1_pad[bit] = data_in1[bit];
+      end
+      if (bit >= port_bitwidth) begin
+        assign data_in0_pad[bit] = 1'b0;
+        assign data_in1_pad[bit] = 1'b0;
+      end
+    end
+
+  //genvar  way;
+  for (way = 0; way < ways; way = way + 1) begin : NwayDatInFix
+    //genvar  byte;
+    for (byte = 0; byte <= (dataWidth)/9; byte = byte + 1) begin : dFixUp
+      assign p0_arr_data_in[way][byte * 8:(byte * 8) + 7] = 8'h00;
+      assign p0_arr_par_in[way][byte] = 1'b0;
+      assign p1_arr_data_in[way][byte * 8:(byte * 8) + 7] = data_in_swzl[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)];
+      assign p1_arr_par_in[way][byte] = data_in_swzl[way][(((byte * 8) + byte) + 8)];
+    end
+  end
+
+  //genvar  way;
+  for (way = 0; way < ways; way = way + 1) begin : NwayDatOutFix
+    //genvar  byte;
+    for (byte = 0; byte <= (dataWidth)/9; byte = byte + 1) begin : dFixUp
+      assign p0_data_out_pad[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)] = p0_arr_data_out[way][byte * 8:(byte * 8) + 7];
+      assign p0_data_out_pad[way][(((byte * 8) + byte) + 8)] = p0_arr_par_out[way][byte];
+      assign p1_data_out_pad[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)] = p1_arr_data_out[way][byte * 8:(byte * 8) + 7];
+      assign p1_data_out_pad[way][(((byte * 8) + byte) + 8)] = p1_arr_par_out[way][byte];
+    end
+  end
+
+  //genvar  way;
+  for (way = 0; way < ways; way = way + 1) begin : NwayDatOut
+    assign p0_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p0_data_out_pad[way][0:port_bitwidth - 1];
+    assign p1_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p1_data_out_pad[way][0:port_bitwidth - 1];
+
+    //genvar  byte;
+    for (byte = 0; byte <= numBytes; byte = byte + 1) begin : swzl
+      assign data_out_fix[(way * port_bitwidth) + (0 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 0];
+      assign data_out_fix[(way * port_bitwidth) + (1 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 1];
+      assign data_out_fix[(way * port_bitwidth) + (2 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 2];
+      assign data_out_fix[(way * port_bitwidth) + (3 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 3];
+      assign data_out_fix[(way * port_bitwidth) + (4 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 4];
+      assign data_out_fix[(way * port_bitwidth) + (5 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 5];
+      assign data_out_fix[(way * port_bitwidth) + (6 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 6];
+      assign data_out_fix[(way * port_bitwidth) + (7 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 7];
+      assign data_out_fix[(way * port_bitwidth) + (8 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 8];
+    end
+  end
+  assign data_out_d = data_out_fix;
+
+  assign data_out = ~data_out_b_q;
+
+  //genvar  way;
+  for (way = 0; way < ways; way = way + 1) begin : Nways
+    //genvar  byte;
+    for (byte = 0; byte < ((((port_bitwidth - 1)/36) + 1) * 4); byte = byte + 1) begin : BEn
+      if (byte <= (port_bitwidth - 1)/9) begin
+        assign p0_wayEn[way][byte] = 1'b0;
+        assign p1_wayEn[way][byte] = wr_way[way];
+      end
+      if (byte > (port_bitwidth - 1)/9) begin
+        assign p0_wayEn[way][byte] = 1'b0;
+        assign p1_wayEn[way][byte] = 1'b0;
+      end
+    end
+
+    // Port A => Read Port
+    // Port B => Write Port
+    genvar  arr;
+    for (arr = 0; arr <= ((port_bitwidth - 1)/36); arr = arr + 1) begin : Narrs
+      RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) wayArr(
+         .CASCADEOUTLATA(cascadeoutlata[arr]),
+         .CASCADEOUTLATB(cascadeoutlatb[arr]),
+         .CASCADEOUTREGA(cascadeoutrega[arr]),
+         .CASCADEOUTREGB(cascadeoutregb[arr]),
+         .DOA(p0_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]),
+         .DOB(p1_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]),
+         .DOPA(p0_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]),
+         .DOPB(p1_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]),
+         .ADDRA(ramb_rd_addr),
+         .ADDRB(ramb_wr_addr),
+         .CASCADEINLATA(1'b0),
+         .CASCADEINLATB(1'b0),
+         .CASCADEINREGA(1'b0),
+         .CASCADEINREGB(1'b0),
+         .CLKA(nclk[0]),
+         .CLKB(nclk[0]),
+         .DIA(p0_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]),
+         .DIB(p1_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]),
+         .DIPA(p0_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]),
+         .DIPB(p1_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]),
+         .ENA(rd_act[way]),
+         .ENB(wr_act[way]),
+         .REGCEA(1'b0),
+         .REGCEB(1'b0),
+         .SSRA(nclk[1]),   //sreset
+         .SSRB(nclk[1]),   //sreset
+         .WEA(p0_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]),
+         .WEB(p1_wayEn[way][(arr * 4) + 0:(arr * 4) + 3])
+       );
+    end
+  end  //Nways
+
+  assign abst_scan_out = 4'b0;
+  assign time_scan_out = 1'b0;
+  assign repr_scan_out = 1'b0;
+  assign bo_pc_failout = 4'h0;
+  assign bo_pc_diagloop = 4'h0;
+end
+endgenerate
+
+assign unused = |({
+    cascadeoutlata ,
+    cascadeoutlatb ,
+    cascadeoutrega ,
+    cascadeoutregb ,
+    nclk[0:`NCLK_WIDTH-1] ,
+    gnd ,
+    vdd ,
+    vcs ,
+    sg_0 ,
+    ary_nsl_thold_0 ,
+    abst_sl_thold_0 ,
+    time_sl_thold_0 ,
+    repr_sl_thold_0 ,
+    g8t_clkoff_dc_b,
+    ccflush_dc,
+    scan_dis_dc_b,
+    scan_diag_dc,
+    g8t_d_mode_dc,
+    g8t_mpw1_dc_b,
+    g8t_mpw2_dc_b,
+    g8t_delay_lclkr_dc,
+    wr_abst_act,
+    rd0_abst_act,
+    abist_di,
+    abist_bw_odd,
+    abist_bw_even,
+    abist_wr_adr,
+    abist_rd0_adr,
+    tc_lbist_ary_wrt_thru_dc,
+    abist_ena_1,
+    abist_g8t_rd0_comp_ena,
+    abist_raw_dc_b,
+    obs0_abist_cmp,
+    abst_scan_in,
+    time_scan_in,
+    repr_scan_in,
+    func_scan_in,
+    lcb_bolt_sl_thold_0,
+    pc_bo_enable_2,
+    pc_bo_reset,
+    pc_bo_unload,
+    pc_bo_repair,
+    pc_bo_shdata,
+    pc_bo_select,
+    tri_lcb_mpw1_dc_b,
+    tri_lcb_mpw2_dc_b,
+    tri_lcb_delay_lclkr_dc,
+    tri_lcb_clkoff_dc_b,
+    tri_lcb_act_dis_dc,
+    p1_data_out_swzl});
+
+// ###############################################################
+// ## Latches
+// ###############################################################
+tri_rlmreg_p #(.WIDTH(ways), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[rd_act_offset:rd_act_offset + ways - 1]),
+   .scout(sov[rd_act_offset:rd_act_offset + ways - 1]),
+   .din(rd_act_d),
+   .dout(rd_act_q)
+);
+
+generate begin : wayReg
+  genvar way;
+  for (way=0; way<ways; way=way+1) begin : wayReg
+    // ###############################################################
+    // ## LCB
+    // ###############################################################
+    tri_lcbnd  my_lcb(
+       .delay_lclkr(delay_lclkr_dc),
+       .mpw1_b(mpw1_dc_b),
+       .mpw2_b(mpw2_dc_b),
+       .force_t(func_sl_force),
+       .nclk(nclk),
+       .vd(vdd),
+       .gd(gnd),
+       .act(rd_act_q[way]),
+       .sg(sg_0),
+       .thold_b(func_sl_thold_0_b),
+       .d1clk(my_d1clk[way]),
+       .d2clk(my_d2clk[way]),
+       .lclk(my_lclk[way])
+    );
+
+    // ###############################################################
+    // ## Placed Latch
+    // ###############################################################
+    tri_inv_nlats #(.WIDTH(port_bitwidth), .INIT(0), .BTR("NLI0001_X4_A12TH"), .NEEDS_SRESET(0)) data_out_reg(
+       .vd(vdd),
+       .gd(gnd),
+       .lclk(my_lclk[way]),
+       .d1clk(my_d1clk[way]),
+       .d2clk(my_d2clk[way]),
+       .scanin(siv[data_out_offset + (port_bitwidth*way):data_out_offset + (port_bitwidth*(way+1)) - 1]),
+       .scanout(sov[data_out_offset + (port_bitwidth*way):data_out_offset + (port_bitwidth*(way+1)) - 1]),
+       .d(data_out_d[(way*port_bitwidth):((way+1)*port_bitwidth)-1]),
+       .qb(data_out_b_q[(way*port_bitwidth):((way+1)*port_bitwidth)-1])
+    );
+  end
+end
+endgenerate
+
+assign siv[0:(2*port_bitwidth)-1]                 = {sov[1:(2*port_bitwidth)-1], func_scan_in[0]};
+assign func_scan_out[0]                           =  sov[0];
+assign siv[(2*port_bitwidth):(4*port_bitwidth)-1] = {sov[(2*port_bitwidth)+1:(4*port_bitwidth)-1], func_scan_in[1]};
+assign func_scan_out[1]                           =  sov[(2*port_bitwidth)];
+assign siv[(4*port_bitwidth):(6*port_bitwidth)-1] = {sov[(4*port_bitwidth)+1:(6*port_bitwidth)-1], func_scan_in[3]};
+assign func_scan_out[2]                           =  sov[(4*port_bitwidth)];
+assign siv[(6*port_bitwidth):scan_right]          = {sov[(6*port_bitwidth)+1:scan_right], func_scan_in[3]};
+assign func_scan_out[3]                           =  sov[(6*port_bitwidth)];
+
+endmodule

rel/src/verilog/trilib/tri_32x70_2w_1r1w.v

@@ -0,0 +1,564 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_32x70_2w_1r1w.v
+// *! DESCRIPTION : 32 entry x 70 bit x 2 way array,
+// *!               1 read & 1 write port
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_32x70_2w_1r1w(
+   gnd,
+   vdd,
+   vcs,
+   nclk,
+   rd_act,
+   wr_act,
+   sg_0,
+   abst_sl_thold_0,
+   ary_nsl_thold_0,
+   time_sl_thold_0,
+   repr_sl_thold_0,
+   func_sl_force,
+   func_sl_thold_0_b,
+   g8t_clkoff_dc_b,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   g8t_d_mode_dc,
+   g8t_mpw1_dc_b,
+   g8t_mpw2_dc_b,
+   g8t_delay_lclkr_dc,
+   d_mode_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   delay_lclkr_dc,
+   wr_abst_act,
+   rd0_abst_act,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   abist_rd0_adr,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp,
+   abst_scan_in,
+   time_scan_in,
+   repr_scan_in,
+   func_scan_in,
+   abst_scan_out,
+   time_scan_out,
+   repr_scan_out,
+   func_scan_out,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   wr_way,
+   wr_addr,
+   data_in,
+   rd_addr,
+   data_out
+);
+parameter                         addressable_ports = 32;		// number of addressable register in this array
+parameter                         addressbus_width = 5;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+parameter                         port_bitwidth = 70;		// bitwidth of ports
+parameter                         ways = 2;		// number of ways
+
+// POWER PINS
+inout                             gnd;
+inout                             vdd;
+inout                             vcs;
+// CLOCK and CLOCKCONTROL ports
+input [0:`NCLK_WIDTH-1]           nclk;
+input [0:1]                       rd_act;
+input [0:1]                       wr_act;
+input                             sg_0;
+input                             abst_sl_thold_0;
+input                             ary_nsl_thold_0;
+input                             time_sl_thold_0;
+input                             repr_sl_thold_0;
+input                             func_sl_force;
+input                             func_sl_thold_0_b;
+input                             g8t_clkoff_dc_b;
+input                             ccflush_dc;
+input                             scan_dis_dc_b;
+input                             scan_diag_dc;
+input                             g8t_d_mode_dc;
+input [0:4]                       g8t_mpw1_dc_b;
+input                             g8t_mpw2_dc_b;
+input [0:4]                       g8t_delay_lclkr_dc;
+input                             d_mode_dc;
+input                             mpw1_dc_b;
+input                             mpw2_dc_b;
+input                             delay_lclkr_dc;
+
+// ABIST
+input                             wr_abst_act;
+input                             rd0_abst_act;
+input [0:3]                       abist_di;
+input                             abist_bw_odd;
+input                             abist_bw_even;
+input [0:addressbus_width-1]      abist_wr_adr;
+input [0:addressbus_width-1]      abist_rd0_adr;
+input                             tc_lbist_ary_wrt_thru_dc;
+input                             abist_ena_1;
+input                             abist_g8t_rd0_comp_ena;
+input                             abist_raw_dc_b;
+input [0:3]                       obs0_abist_cmp;
+
+// Scan
+input [0:1]                       abst_scan_in;
+input                             time_scan_in;
+input                             repr_scan_in;
+input                             func_scan_in;
+output [0:1]                      abst_scan_out;
+output                            time_scan_out;
+output                            repr_scan_out;
+output                            func_scan_out;
+
+// BOLT-ON
+input                             lcb_bolt_sl_thold_0;
+input                             pc_bo_enable_2;		// general bolt-on enable
+input                             pc_bo_reset;		// reset
+input                             pc_bo_unload;		// unload sticky bits
+input                             pc_bo_repair;		// execute sticky bit decode
+input                             pc_bo_shdata;		// shift data for timing write and diag loop
+input [0:1]                       pc_bo_select;		// select for mask and hier writes
+output [0:1]                      bo_pc_failout;		// fail/no-fix reg
+output [0:1]                      bo_pc_diagloop;
+input                             tri_lcb_mpw1_dc_b;
+input                             tri_lcb_mpw2_dc_b;
+input                             tri_lcb_delay_lclkr_dc;
+input                             tri_lcb_clkoff_dc_b;
+input                             tri_lcb_act_dis_dc;
+
+// Write Ports
+input [0:ways-1]                  wr_way;
+input [0:addressbus_width-1]      wr_addr;
+input [0:port_bitwidth-1]         data_in;
+
+// Read Ports
+input [0:addressbus_width-1]      rd_addr;
+output [0:port_bitwidth*ways-1]   data_out;
+
+// tri_32x70_2w_1r1w
+
+parameter                         ramb_base_width = 36;
+parameter                         ramb_base_addr = 9;
+
+// Configuration Statement for NCsim
+//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
+parameter                          rd_act_offset = 0;
+parameter                          data_out0_offset = rd_act_offset + 2;
+parameter                          data_out1_offset = data_out0_offset + port_bitwidth - 1;
+parameter                          scan_right = data_out1_offset + port_bitwidth - 1;
+
+wire [0:port_bitwidth-1]          array_wr_data;
+wire [0:35]                       ramb_data_in_l;
+wire [0:35]                       ramb_data_in_r;
+wire [0:35]                       ramb_data_p0_outA;
+wire [0:35]                       ramb_data_p0_outB;
+wire [0:35]                       ramb_data_p0_outC;
+wire [0:35]                       ramb_data_p0_outD;
+wire [0:35]                       ramb_data_p1_outA;
+wire [0:35]                       ramb_data_p1_outB;
+wire [0:35]                       ramb_data_p1_outC;
+wire [0:35]                       ramb_data_p1_outD;
+wire [0:ramb_base_addr-1]         ramb_addr_rd1;
+wire [0:ramb_base_addr-1]         ramb_addr_wr_rd0;
+
+wire [0:ramb_base_addr-1]         rd_addr0;
+wire [0:ramb_base_addr-1]         wr_addr1;
+wire                              write_enable_AB;
+wire                              write_enable_CD;
+wire                              tiup;
+wire [0:35]                       tidn;
+wire [0:1]                        act;
+wire                              ary_nsl_thold_0_b;
+wire [0:addressable_ports-1]      arrA_bit0_scanout;
+wire [0:addressable_ports-1]      arrC_bit0_scanout;
+wire [0:addressable_ports-1]      arrA_bit0_d;
+wire [0:addressable_ports-1]      arrA_bit0_q;
+wire [0:addressable_ports-1]      arrC_bit0_d;
+wire [0:addressable_ports-1]      arrC_bit0_q;
+wire [0:addressable_ports-1]      arrA_bit0_wen;
+wire [0:addressable_ports-1]      arrC_bit0_wen;
+reg                               arrA_bit0_out_d;
+reg                               arrC_bit0_out_d;
+wire                              arrA_bit0_out_q;
+wire                              arrC_bit0_out_q;
+wire                              arrA_bit0_out_scanout;
+wire                              arrC_bit0_out_scanout;
+wire [0:port_bitwidth*ways-1]     data_out_d;
+wire [0:port_bitwidth*ways-1]     data_out_q;
+wire [0:1]                        rd_act_d;
+wire [0:1]                        rd_act_q;
+wire [0:scan_right]               siv;
+wire [0:scan_right]               sov;
+
+(* analysis_not_referenced="true" *)
+wire                              unused;
+
+assign unused = | {ramb_data_p1_outA[0], ramb_data_p1_outA[35], ramb_data_p1_outB[35], ramb_data_p1_outC[0], ramb_data_p1_outC[35], ramb_data_p1_outD[35],
+                   ramb_data_p0_outA, ramb_data_p0_outB, ramb_data_p0_outC, ramb_data_p0_outD, gnd, vdd, vcs,
+                   sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b,
+                   scan_diag_dc, g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd,
+                   abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b,
+                   obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload,
+                   pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
+                   tri_lcb_act_dis_dc, arrA_bit0_scanout, arrC_bit0_scanout, arrA_bit0_out_scanout, arrC_bit0_out_scanout};
+
+assign tiup = 1'b1;
+assign tidn = 36'b0;
+assign act = rd_act | wr_act;
+assign rd_act_d = rd_act;
+
+// Data Generate
+assign array_wr_data = data_in;
+
+assign ramb_data_in_l = {array_wr_data[0:34], 1'b0};
+assign ramb_data_in_r = {array_wr_data[35:69], 1'b0};
+
+assign write_enable_AB = wr_act[0] & wr_way[0];
+assign write_enable_CD = wr_act[1] & wr_way[1];
+
+// Read/Write Port Address Generate
+generate
+begin
+  genvar  t;
+  for (t = 0; t < ramb_base_addr; t = t + 1)
+  begin : rambAddrCalc
+    if (t < ramb_base_addr - addressbus_width)
+    begin
+      assign rd_addr0[t] = 1'b0;
+      assign wr_addr1[t] = 1'b0;
+    end
+    if (t >= ramb_base_addr - addressbus_width)
+    begin
+      assign rd_addr0[t] = rd_addr[t - (ramb_base_addr - addressbus_width)];
+      assign wr_addr1[t] = wr_addr[t - (ramb_base_addr - addressbus_width)];
+    end
+  end
+end
+endgenerate
+
+// Writing on PortA
+// Reading on PortB
+assign ramb_addr_rd1 = rd_addr0;
+assign ramb_addr_wr_rd0 = wr_addr1;
+
+assign data_out_d = {arrA_bit0_out_q, ramb_data_p1_outA[1:34], ramb_data_p1_outB[0:34], arrC_bit0_out_q, ramb_data_p1_outC[1:34], ramb_data_p1_outD[0:34]};
+assign data_out   = data_out_q;
+
+generate
+   begin : arr_bit0
+      genvar                                    i;
+      for (i = 0; i <= addressable_ports - 1; i = i + 1)
+        begin : arr_bit0
+           wire [0:addressbus_width-1]         iDummy=i;
+           assign arrA_bit0_wen[i] = write_enable_AB & (wr_addr == iDummy);
+           assign arrC_bit0_wen[i] = write_enable_CD & (wr_addr == iDummy);
+           assign arrA_bit0_d[i] = (arrA_bit0_wen[i] == 1'b1) ? array_wr_data[0] :
+           	                                                   arrA_bit0_q[i];
+           assign arrC_bit0_d[i] = (arrC_bit0_wen[i] == 1'b1) ? array_wr_data[0] :
+           	                                                   arrC_bit0_q[i];
+        end
+   end
+endgenerate
+
+always @(*)
+  begin: bit0_read_proc
+     reg                                      rd_arrA_bit0;
+     reg                                      rd_arrC_bit0;
+     (* analysis_not_referenced="true" *)
+     reg [0:31]                                i;
+     rd_arrA_bit0     = 1'b0;
+     rd_arrC_bit0     = 1'b0;
+     for (i = 0; i <= addressable_ports - 1; i = i + 1)
+       begin
+          rd_arrA_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrA_bit0_q[i])   | rd_arrA_bit0;
+          rd_arrC_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrC_bit0_q[i])   | rd_arrC_bit0;
+       end
+     arrA_bit0_out_d <= rd_arrA_bit0;
+     arrC_bit0_out_d <= rd_arrC_bit0;
+  end
+
+
+assign ary_nsl_thold_0_b = ~ ary_nsl_thold_0;
+
+tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latch(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(write_enable_AB),
+   .force_t(tidn[0]),
+   .d_mode(tidn[0]),
+   .delay_lclkr(tidn[0]),
+   .mpw1_b(tidn[0]),
+   .mpw2_b(tidn[0]),
+   .thold_b(ary_nsl_thold_0_b),
+   .sg(tidn[0]),
+   .scin({addressable_ports{tidn[0]}}),
+   .scout(arrA_bit0_scanout),
+   .din(arrA_bit0_d),
+   .dout(arrA_bit0_q)
+);
+
+tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latch(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(write_enable_CD),
+   .force_t(tidn[0]),
+   .d_mode(tidn[0]),
+   .delay_lclkr(tidn[0]),
+   .mpw1_b(tidn[0]),
+   .mpw2_b(tidn[0]),
+   .thold_b(ary_nsl_thold_0_b),
+   .sg(tidn[0]),
+   .scin({addressable_ports{tidn[0]}}),
+   .scout(arrC_bit0_scanout),
+   .din(arrC_bit0_d),
+   .dout(arrC_bit0_q)
+);
+
+tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(tidn[0]),
+   .d_mode(tidn[0]),
+   .delay_lclkr(tidn[0]),
+   .mpw1_b(tidn[0]),
+   .mpw2_b(tidn[0]),
+   .thold_b(ary_nsl_thold_0_b),
+   .sg(tidn[0]),
+   .scin(tidn[0]),
+   .scout(arrA_bit0_out_scanout),
+   .din(arrA_bit0_out_d),
+   .dout(arrA_bit0_out_q)
+);
+
+tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_out_latch(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(tidn[0]),
+   .d_mode(tidn[0]),
+   .delay_lclkr(tidn[0]),
+   .mpw1_b(tidn[0]),
+   .mpw2_b(tidn[0]),
+   .thold_b(ary_nsl_thold_0_b),
+   .sg(tidn[0]),
+   .scin(tidn[0]),
+   .scout(arrC_bit0_out_scanout),
+   .din(arrC_bit0_out_d),
+   .dout(arrC_bit0_out_q)
+);
+
+
+RAMB16_S36_S36
+    #(.SIM_COLLISION_CHECK("NONE"))   // all, none, warning_only, generate_x_only
+arr0_A(
+   .DOA(ramb_data_p0_outA[0:31]),
+   .DOB(ramb_data_p1_outA[0:31]),
+   .DOPA(ramb_data_p0_outA[32:35]),
+   .DOPB(ramb_data_p1_outA[32:35]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(ramb_data_in_l[0:31]),
+   .DIB(tidn[0:31]),
+   .DIPA(ramb_data_in_l[32:35]),
+   .DIPB(tidn[32:35]),
+   .ENA(act[0]),
+   .ENB(act[0]),
+   .SSRA(nclk[1]),   //sreset
+   .SSRB(nclk[1]),   //sreset
+   .WEA(write_enable_AB),
+   .WEB(tidn[0])
+);
+
+RAMB16_S36_S36
+    #(.SIM_COLLISION_CHECK("NONE"))   // all, none, warning_only, generate_x_only
+arr1_B(
+   .DOA(ramb_data_p0_outB[0:31]),
+   .DOB(ramb_data_p1_outB[0:31]),
+   .DOPA(ramb_data_p0_outB[32:35]),
+   .DOPB(ramb_data_p1_outB[32:35]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(ramb_data_in_r[0:31]),
+   .DIB(tidn[0:31]),
+   .DIPA(ramb_data_in_r[32:35]),
+   .DIPB(tidn[32:35]),
+   .ENA(act[0]),
+   .ENB(act[0]),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_AB),
+   .WEB(tidn[0])
+);
+
+RAMB16_S36_S36
+    #(.SIM_COLLISION_CHECK("NONE"))   // all, none, warning_only, generate_x_only
+arr2_C(
+   .DOA(ramb_data_p0_outC[0:31]),
+   .DOB(ramb_data_p1_outC[0:31]),
+   .DOPA(ramb_data_p0_outC[32:35]),
+   .DOPB(ramb_data_p1_outC[32:35]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(ramb_data_in_l[0:31]),
+   .DIB(tidn[0:31]),
+   .DIPA(ramb_data_in_l[32:35]),
+   .DIPB(tidn[32:35]),
+   .ENA(act[1]),
+   .ENB(act[1]),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_CD),
+   .WEB(tidn[0])
+);
+
+RAMB16_S36_S36
+    #(.SIM_COLLISION_CHECK("NONE"))   // all, none, warning_only, generate_x_only
+arr3_D(
+   .DOA(ramb_data_p0_outD[0:31]),
+   .DOB(ramb_data_p1_outD[0:31]),
+   .DOPA(ramb_data_p0_outD[32:35]),
+   .DOPB(ramb_data_p1_outD[32:35]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(ramb_data_in_r[0:31]),
+   .DIB(tidn[0:31]),
+   .DIPA(ramb_data_in_r[32:35]),
+   .DIPB(tidn[32:35]),
+   .ENA(act[1]),
+   .ENB(act[1]),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_CD),
+   .WEB(tidn[0])
+);
+
+// ####################################################
+// Registers
+// ####################################################
+
+tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[rd_act_offset:rd_act_offset + 2 - 1]),
+   .scout(sov[rd_act_offset:rd_act_offset + 2 - 1]),
+   .din(rd_act_d),
+   .dout(rd_act_q)
+);
+
+tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(rd_act_q[0]),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[data_out0_offset:data_out0_offset + port_bitwidth - 1]),
+   .scout(sov[data_out0_offset:data_out0_offset + port_bitwidth - 1]),
+   .din(data_out_d[0:port_bitwidth - 1]),
+   .dout(data_out_q[0:port_bitwidth - 1])
+);
+
+tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out1_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(rd_act_q[1]),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[data_out1_offset:data_out1_offset + port_bitwidth - 1]),
+   .scout(sov[data_out1_offset:data_out1_offset + port_bitwidth - 1]),
+   .din(data_out_d[port_bitwidth:2 * port_bitwidth - 1]),
+   .dout(data_out_q[port_bitwidth:2 * port_bitwidth - 1])
+);
+
+assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
+assign func_scan_out = sov[0];
+
+assign abst_scan_out = tidn[0:1];
+assign time_scan_out = tidn[0];
+assign repr_scan_out = tidn[0];
+assign bo_pc_failout = tidn[0:1];
+assign bo_pc_diagloop = tidn[0:1];
+endmodule

rel/src/verilog/trilib/tri_512x162_4w_0.v

@@ -0,0 +1,338 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_512x162_4w_0.v
+// *! DESCRIPTION : 512 Entry x 162 bit x 4 way array
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_512x162_4w_0(
+   gnd,
+   vdd,
+   vcs,
+   nclk,
+   ccflush_dc,
+   lcb_clkoff_dc_b,
+   lcb_d_mode_dc,
+   lcb_act_dis_dc,
+   lcb_ary_nsl_thold_0,
+   lcb_sg_1,
+   lcb_abst_sl_thold_0,
+   lcb_func_sl_thold_0_b,
+   func_force,
+   scan_diag_dc,
+   scan_dis_dc_b,
+   func_scan_in,
+   func_scan_out,
+   abst_scan_in,
+   abst_scan_out,
+   lcb_delay_lclkr_np_dc,
+   ctrl_lcb_delay_lclkr_np_dc,
+   dibw_lcb_delay_lclkr_np_dc,
+   ctrl_lcb_mpw1_np_dc_b,
+   dibw_lcb_mpw1_np_dc_b,
+   lcb_mpw1_pp_dc_b,
+   lcb_mpw1_2_pp_dc_b,
+   aodo_lcb_delay_lclkr_dc,
+   aodo_lcb_mpw1_dc_b,
+   aodo_lcb_mpw2_dc_b,
+   lcb_time_sg_0,
+   lcb_time_sl_thold_0,
+   time_scan_in,
+   time_scan_out,
+   bitw_abist,
+   lcb_repr_sl_thold_0,
+   lcb_repr_sg_0,
+   repr_scan_in,
+   repr_scan_out,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_en_1,
+   din_abist,
+   abist_cmp_en,
+   abist_raw_b_dc,
+   data_cmp_abist,
+   addr_abist,
+   r_wb_abist,
+   write_thru_en_dc,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   read_act,
+   write_act,
+   write_enable,
+   write_way,
+   addr,
+   data_in,
+   data_out
+);
+   parameter                                      addressable_ports = 512;	// number of addressable register in this array
+   parameter                                      addressbus_width = 9;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+   parameter                                      port_bitwidth = 162;		// bitwidth of ports
+   parameter                                      ways = 4;		// number of ways
+   // POWER PINS
+   inout                                          gnd;
+   inout                                          vdd;
+   (* analysis_not_referenced="true" *)
+   inout                                          vcs;
+   // CLOCK and CLOCKCONTROL ports
+   input [0:`NCLK_WIDTH-1]                        nclk;
+   input                                          ccflush_dc;
+   input                                          lcb_clkoff_dc_b;
+   input                                          lcb_d_mode_dc;
+   input                                          lcb_act_dis_dc;
+   input                                          lcb_ary_nsl_thold_0;
+   input                                          lcb_sg_1;
+   input                                          lcb_abst_sl_thold_0;
+   input                                          lcb_func_sl_thold_0_b;
+   input                                          func_force;
+   input                                          scan_diag_dc;
+   input                                          scan_dis_dc_b;
+   input                                          func_scan_in;
+   output                                         func_scan_out;
+   input [0:1]                                    abst_scan_in;
+   output [0:1]                                   abst_scan_out;
+   input                                          lcb_delay_lclkr_np_dc;
+   input                                          ctrl_lcb_delay_lclkr_np_dc;
+   input                                          dibw_lcb_delay_lclkr_np_dc;
+   input                                          ctrl_lcb_mpw1_np_dc_b;
+   input                                          dibw_lcb_mpw1_np_dc_b;
+   input                                          lcb_mpw1_pp_dc_b;
+   input                                          lcb_mpw1_2_pp_dc_b;
+   input                                          aodo_lcb_delay_lclkr_dc;
+   input                                          aodo_lcb_mpw1_dc_b;
+   input                                          aodo_lcb_mpw2_dc_b;
+   // Timing Scan Chain Pins
+   input                                          lcb_time_sg_0;
+   input                                          lcb_time_sl_thold_0;
+   input                                          time_scan_in;
+   output                                         time_scan_out;
+   input [0:1]                                    bitw_abist;
+   // REDUNDANCY PINS
+   input                                          lcb_repr_sl_thold_0;
+   input                                          lcb_repr_sg_0;
+   input                                          repr_scan_in;
+   output                                         repr_scan_out;
+   // DATA I/O RELATED PINS:
+   input                                          tc_lbist_ary_wrt_thru_dc;
+   input                                          abist_en_1;
+   input [0:3]                                    din_abist;
+   input                                          abist_cmp_en;
+   input                                          abist_raw_b_dc;
+   input [0:3]                                    data_cmp_abist;
+   input [0:addressbus_width-1]                   addr_abist;
+   input                                          r_wb_abist;
+   input                                          write_thru_en_dc;
+   // BOLT-ON
+   input                                          lcb_bolt_sl_thold_0;	// thold for any regs inside backend
+   input                                          pc_bo_enable_2;	// general bolt-on enable, probably DC
+   input                                          pc_bo_reset;		// execute sticky bit decode
+   input                                          pc_bo_unload;
+   input                                          pc_bo_repair;		// load repair reg
+   input                                          pc_bo_shdata;		// shift data for timing write
+   input [0:1]                                    pc_bo_select;		// select for mask and hier writes
+   output [0:1]                                   bo_pc_failout;	// fail/no-fix reg
+   output [0:1]                                   bo_pc_diagloop;
+   input                                          tri_lcb_mpw1_dc_b;
+   input                                          tri_lcb_mpw2_dc_b;
+   input                                          tri_lcb_delay_lclkr_dc;
+   input                                          tri_lcb_clkoff_dc_b;
+   input                                          tri_lcb_act_dis_dc;
+   // FUNCTIONAL PORTS
+   input [0:1]                                    read_act;
+   input [0:3]                                    write_act;
+   input                                          write_enable;
+   input [0:ways-1]                               write_way;
+   input [0:addressbus_width-1]                   addr;
+   input [0:port_bitwidth-1]                      data_in;
+   output [0:port_bitwidth*ways-1]                data_out;
+
+   // tri_512x162_4w_0
+
+   parameter            ramb_base_width = 36;
+   parameter            ramb_base_addr = 9;
+   parameter            ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1;	// # of RAMB's per way
+
+   // Configuration Statement for NCsim
+   //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
+
+   wire [0:ramb_base_width*ramb_width_mult-1]   ramb_data_in;
+   wire [0:ramb_base_width*ramb_width_mult-1]   ramb_data_out[0:ways-1];
+   wire [0:ramb_base_addr-1]                    ramb_addr;
+
+   wire                                         rd_act_d;
+   wire                                         rd_act_l2;
+   wire [0:port_bitwidth*ways-1]                data_out_d;
+   wire [0:port_bitwidth*ways-1]                data_out_l2;
+
+   wire                                         lcb_sg_0;
+
+   wire [0:ways-1]                                act;
+   wire [0:ways-1]                                write;
+   wire                                           tidn;
+    (* analysis_not_referenced="true" *)
+   wire                                           unused;
+   wire [31:0]                                    dob;
+   wire [3:0]                                     dopb;
+   wire [0:port_bitwidth*ways-1]                  unused_scout;
+
+   generate
+   begin
+     assign tidn = 1'b0;
+
+     if (addressbus_width < ramb_base_addr)
+     begin
+       assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
+       assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr;
+     end
+     if (addressbus_width >= ramb_base_addr)
+     begin
+       assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
+     end
+
+     genvar  i;
+     for (i = 0; i < ramb_base_width*ramb_width_mult; i = i + 1)
+     begin : din
+       if (i < port_bitwidth)
+         assign ramb_data_in[i] = data_in[i];
+       if (i >= port_bitwidth)
+            assign ramb_data_in[i] = 1'b0;
+     end
+
+     genvar  w;
+     for (w = 0; w < ways; w = w + 1)
+     begin : aw
+       assign act[w] = (|(read_act)) | write_way[w];
+       assign write[w] = write_enable & write_way[w];
+
+       genvar  x;
+       for (x = 0; x < ramb_width_mult; x = x + 1)
+       begin : ax
+         RAMB16_S36_S36
+             #(.SIM_COLLISION_CHECK("NONE"))            // all, none, warning_only, generate_x_only
+         arr(
+               .DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
+               .DOB(dob),
+               .DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .DOPB(dopb),
+               .ADDRA(ramb_addr),
+               .ADDRB(ramb_addr),
+               .CLKA(nclk[0]),
+               .CLKB(tidn),
+               .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
+               .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
+               .DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
+               .ENA(act[w]),
+               .ENB(tidn),
+               .SSRA(nclk[1]),
+               .SSRB(tidn),
+               .WEA(write[w]),
+               .WEB(tidn)
+            );
+       end  //ax
+
+       assign data_out_d[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
+
+     end  //aw
+
+   assign data_out = data_out_l2;
+
+   assign rd_act_d = |(read_act);	// Use for data_out latch act
+
+   tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch(
+      .vd(vdd),
+      .gd(gnd),
+      .nclk(nclk),
+      .act(1'b1),
+      .thold_b(lcb_func_sl_thold_0_b),
+      .sg(lcb_sg_0),
+      .force_t(func_force),
+      .delay_lclkr(tri_lcb_delay_lclkr_dc),
+      .mpw1_b(tri_lcb_mpw1_dc_b),
+      .mpw2_b(tri_lcb_mpw2_dc_b),
+      .d_mode(lcb_d_mode_dc),
+      .scin(1'b0),
+      .scout(func_scan_out),
+      .din(rd_act_d),
+      .dout(rd_act_l2)
+   );
+
+   tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch(
+      .vd(vdd),
+      .gd(gnd),
+      .nclk(nclk),
+      .act(rd_act_l2),
+      .thold_b(lcb_func_sl_thold_0_b),
+      .sg(lcb_sg_0),
+      .force_t(func_force),
+      .delay_lclkr(tri_lcb_delay_lclkr_dc),
+      .mpw1_b(tri_lcb_mpw1_dc_b),
+      .mpw2_b(tri_lcb_mpw2_dc_b),
+      .d_mode(lcb_d_mode_dc),
+      .scin({port_bitwidth*ways{1'b0}}),
+      .scout(unused_scout),
+      .din(data_out_d),
+      .dout(data_out_l2)
+   );
+
+   tri_plat #(.WIDTH(1)) perv_1to0_reg(
+      .vd(vdd),
+      .gd(gnd),
+      .nclk(nclk),
+      .flush(ccflush_dc),
+      .din(lcb_sg_1),
+      .q(lcb_sg_0)
+   );
+
+     assign abst_scan_out = 2'b00;
+     assign time_scan_out = 1'b0;
+     assign repr_scan_out = 1'b0;
+
+     assign bo_pc_failout = 2'b00;
+     assign bo_pc_diagloop = 2'b00;
+
+     assign unused = | ({nclk[2:`NCLK_WIDTH-1], ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[1][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[2][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[3][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, lcb_clkoff_dc_b, lcb_d_mode_dc, lcb_act_dis_dc, scan_dis_dc_b, scan_diag_dc, bitw_abist, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, write_thru_en_dc, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_delay_lclkr_np_dc, ctrl_lcb_delay_lclkr_np_dc, dibw_lcb_delay_lclkr_np_dc, ctrl_lcb_mpw1_np_dc_b, dibw_lcb_mpw1_np_dc_b, lcb_mpw1_pp_dc_b, lcb_mpw1_2_pp_dc_b, aodo_lcb_delay_lclkr_dc, aodo_lcb_mpw1_dc_b, aodo_lcb_mpw2_dc_b, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, write_act, dob, dopb, unused_scout});
+   end
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_512x16_1r1w_1.v

@@ -0,0 +1,333 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+//*****************************************************************************
+//  Description:  Tri Array Wrapper
+//
+//*****************************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_512x16_1r1w_1(
+   vdd,
+   vcs,
+   gnd,
+   nclk,
+   rd_act,
+   wr_act,
+   lcb_d_mode_dc,
+   lcb_clkoff_dc_b,
+   lcb_mpw1_dc_b,
+   lcb_mpw2_dc_b,
+   lcb_delay_lclkr_dc,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   func_scan_in,
+   func_scan_out,
+   lcb_sg_0,
+   lcb_sl_thold_0_b,
+   lcb_time_sl_thold_0,
+   lcb_abst_sl_thold_0,
+   lcb_ary_nsl_thold_0,
+   lcb_repr_sl_thold_0,
+   time_scan_in,
+   time_scan_out,
+   abst_scan_in,
+   abst_scan_out,
+   repr_scan_in,
+   repr_scan_out,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   wr_abst_act,
+   abist_rd0_adr,
+   rd0_abst_act,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   bw,
+   wr_adr,
+   rd_adr,
+   di,
+   do
+);
+   parameter                                      addressable_ports = 128;	// number of addressable register in this array
+   parameter                                      addressbus_width = 9;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+   parameter                                      port_bitwidth = 16;		// bitwidth of ports
+   parameter                                      ways = 1;		// number of ways
+
+   // POWER PINS
+   inout                                          vdd;
+   inout                                          vcs;
+   inout                                          gnd;
+
+   input [0:`NCLK_WIDTH-1]                        nclk;
+
+   input                                          rd_act;
+   input                                          wr_act;
+
+   // DC TEST PINS
+   input                                          lcb_d_mode_dc;
+   input                                          lcb_clkoff_dc_b;
+   input [0:4]                                    lcb_mpw1_dc_b;
+   input                                          lcb_mpw2_dc_b;
+   input [0:4]                                    lcb_delay_lclkr_dc;
+
+   input                                          ccflush_dc;
+   input                                          scan_dis_dc_b;
+   input                                          scan_diag_dc;
+   input                                          func_scan_in;
+   output                                         func_scan_out;
+
+   input                                          lcb_sg_0;
+   input                                          lcb_sl_thold_0_b;
+   input                                          lcb_time_sl_thold_0;
+   input                                          lcb_abst_sl_thold_0;
+   input                                          lcb_ary_nsl_thold_0;
+   input                                          lcb_repr_sl_thold_0;
+   input                                          time_scan_in;
+   output                                         time_scan_out;
+   input                                          abst_scan_in;
+   output                                         abst_scan_out;
+   input                                          repr_scan_in;
+   output                                         repr_scan_out;
+
+   input [0:3]                                    abist_di;
+   input                                          abist_bw_odd;
+   input                                          abist_bw_even;
+   input [0:6]                                    abist_wr_adr;
+   input                                          wr_abst_act;
+   input [0:6]                                    abist_rd0_adr;
+   input                                          rd0_abst_act;
+   input                                          tc_lbist_ary_wrt_thru_dc;
+   input                                          abist_ena_1;
+   input                                          abist_g8t_rd0_comp_ena;
+   input                                          abist_raw_dc_b;
+   input [0:3]                                    obs0_abist_cmp;
+
+   // BOLT-ON
+   input                                          lcb_bolt_sl_thold_0;
+   input                                          pc_bo_enable_2;		// general bolt-on enable
+   input                                          pc_bo_reset;		// reset
+   input                                          pc_bo_unload;		// unload sticky bits
+   input                                          pc_bo_repair;		// execute sticky bit decode
+   input                                          pc_bo_shdata;		// shift data for timing write and diag loop
+   input                                          pc_bo_select;		// select for mask and hier writes
+   output                                         bo_pc_failout;		// fail/no-fix reg
+   output                                         bo_pc_diagloop;
+   input                                          tri_lcb_mpw1_dc_b;
+   input                                          tri_lcb_mpw2_dc_b;
+   input                                          tri_lcb_delay_lclkr_dc;
+   input                                          tri_lcb_clkoff_dc_b;
+   input                                          tri_lcb_act_dis_dc;
+
+   input [0:15]                                   bw;
+   input [0:8]                                    wr_adr;
+   input [0:8]                                    rd_adr;
+   input [0:15]                                   di;
+
+   output [0:15]                                  do;
+
+   // Configuration Statement for NCsim
+   //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
+
+   wire                                           clk;
+   wire                                           clk2x;
+   wire [0:8]                                     b0addra;
+   wire [0:8]                                     b0addrb;
+   wire                                           wea;
+   wire                                           web;
+   wire                                           wren_a;
+   // Latches
+   reg                                            reset_q;
+   reg                                            gate_fq;
+   wire                                           gate_d;
+   wire [0:35]                                    r_data_out_1_d;
+   reg [0:35]                                     r_data_out_1_fq;
+   wire [0:35]                                    w_data_in_0;
+
+   wire [0:35]                                    r_data_out_0_bram;
+   wire [0:35]                                    r_data_out_1_bram;
+
+   wire                                           toggle_d;
+   reg                                            toggle_q;
+   wire                                           toggle2x_d;
+   reg                                            toggle2x_q;
+
+   (* analysis_not_referenced="true" *)
+   wire                                           unused;
+
+     assign clk = nclk[0];
+     assign clk2x = nclk[2];
+
+     always @(posedge clk)
+     begin: rlatch
+       reset_q <= nclk[1];
+     end
+
+     //
+     //  NEW clk2x gate logic start
+     //
+
+     always @(posedge clk)
+     begin: tlatch
+       if (reset_q == 1'b1)
+         toggle_q <= 1'b1;
+       else
+         toggle_q <= toggle_d;
+     end
+
+     always @(posedge clk2x)
+     begin: flatch
+       toggle2x_q <= toggle2x_d;
+       gate_fq <= gate_d;
+       r_data_out_1_fq <= r_data_out_1_d;
+     end
+
+     assign toggle_d = (~toggle_q);
+     assign toggle2x_d = toggle_q;
+
+     // should force gate_fq to be on during odd 2x clock (second half of 1x clock).
+     //gate_d <= toggle_q xor toggle2x_q;
+     // if you want the first half do the following
+     assign gate_d = (~(toggle_q ^ toggle2x_q));
+
+     //
+     //  NEW clk2x gate logic end
+     //
+
+     assign b0addra[0:8] = wr_adr;
+     assign b0addrb[0:8] = rd_adr;
+
+     // Unused Address Bits
+     //b0addra(0 to 1) <= "00";
+     //b0addrb(0 to 1) <= "00";
+
+     // port a is a read-modify-write port
+     assign wren_a = ((bw != 16'b0000000000000000) & (wr_act == 1'b1)) ? 1'b1 :
+                     1'b0;
+     assign wea = wren_a & (~(gate_fq));		// write in 2nd half of nclk
+     assign web = 1'b0;
+     assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] :
+                             r_data_out_0_bram[0];
+     assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] :
+                             r_data_out_0_bram[1];
+     assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] :
+                             r_data_out_0_bram[2];
+     assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] :
+                             r_data_out_0_bram[3];
+     assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] :
+                             r_data_out_0_bram[4];
+     assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] :
+                             r_data_out_0_bram[5];
+     assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] :
+                             r_data_out_0_bram[6];
+     assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] :
+                             r_data_out_0_bram[7];
+     assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] :
+                             r_data_out_0_bram[8];
+     assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] :
+                             r_data_out_0_bram[9];
+     assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] :
+                              r_data_out_0_bram[10];
+     assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] :
+                              r_data_out_0_bram[11];
+     assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] :
+                              r_data_out_0_bram[12];
+     assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] :
+                              r_data_out_0_bram[13];
+     assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] :
+                              r_data_out_0_bram[14];
+     assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] :
+                              r_data_out_0_bram[15];
+     assign w_data_in_0[16:35] = 20'b0;
+
+     assign r_data_out_1_d = r_data_out_1_bram;
+
+     RAMB16_S36_S36
+              #(.SIM_COLLISION_CHECK("NONE"))            // all, none, warning_only, generate_x_only
+     bram0a(
+               .CLKA(clk2x),
+               .CLKB(clk2x),
+               .SSRA(reset_q),
+               .SSRB(reset_q),
+               .ADDRA(b0addra),
+               .ADDRB(b0addrb),
+               .DIA(w_data_in_0[0:31]),
+               .DIB(32'b0),
+               .DOA(r_data_out_0_bram[0:31]),
+               .DOB(r_data_out_1_bram[0:31]),
+               .DOPA(r_data_out_0_bram[32:35]),
+               .DOPB(r_data_out_1_bram[32:35]),
+               .DIPA(w_data_in_0[32:35]),
+               .DIPB(4'h0),
+               .ENA(1'b1),
+               .ENB(1'b1),
+               .WEA(wea),
+               .WEB(web)
+            );
+
+     assign do = r_data_out_1_fq[0:15];
+
+     assign func_scan_out = func_scan_in;
+     assign time_scan_out = time_scan_in;
+     assign abst_scan_out = abst_scan_in;
+     assign repr_scan_out = repr_scan_in;
+
+     assign bo_pc_failout = 1'b0;
+     assign bo_pc_diagloop = 1'b0;
+
+     assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
+                       lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
+                       lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
+                       abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
+                       tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
+                       lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
+                       pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
+                       tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_fq[16:35]};
+endmodule

rel/src/verilog/trilib/tri_64x144_1r1w.v

@@ -0,0 +1,427 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_64x144_1r1w.v
+// *! DESCRIPTION : 64 Entry x 144 bit array, 9 bit writeable
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_64x144_1r1w(
+   gnd,
+   vdd,
+   vcs,
+   nclk,
+   rd_act,
+   wr_act,
+   sg_0,
+   abst_sl_thold_0,
+   ary_nsl_thold_0,
+   time_sl_thold_0,
+   repr_sl_thold_0,
+   func_sl_force,
+   func_sl_thold_0_b,
+   g8t_clkoff_dc_b,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   g8t_d_mode_dc,
+   g8t_mpw1_dc_b,
+   g8t_mpw2_dc_b,
+   g8t_delay_lclkr_dc,
+   d_mode_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   delay_lclkr_dc,
+   wr_abst_act,
+   rd0_abst_act,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   abist_rd0_adr,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp,
+   abst_scan_in,
+   time_scan_in,
+   repr_scan_in,
+   func_scan_in,
+   abst_scan_out,
+   time_scan_out,
+   repr_scan_out,
+   func_scan_out,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   write_enable,
+   addr_wr,
+   data_in,
+   addr_rd,
+   data_out
+);
+parameter                                      addressable_ports = 64;	// number of addressable register in this array
+parameter                                      addressbus_width = 6;		// width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+parameter                                      port_bitwidth = 144;		// bitwidth of ports (per way)
+parameter                                      bit_write_type = 9;		// gives the number of bits that shares one write-enable; must divide evenly into array
+parameter                                      ways = 1;                     // number of ways
+
+// POWER PINS
+inout                                          gnd;
+inout                                          vdd;
+inout                                          vcs;
+
+// CLOCK and CLOCKCONTROL ports
+input [0:`NCLK_WIDTH-1]                        nclk;
+input                                          rd_act;
+input                                          wr_act;
+input                                          sg_0;
+input                                          abst_sl_thold_0;
+input                                          ary_nsl_thold_0;
+input                                          time_sl_thold_0;
+input                                          repr_sl_thold_0;
+input                                          func_sl_force;
+input                                          func_sl_thold_0_b;
+input                                          g8t_clkoff_dc_b;
+input                                          ccflush_dc;
+input                                          scan_dis_dc_b;
+input                                          scan_diag_dc;
+input                                          g8t_d_mode_dc;
+input [0:4]                                    g8t_mpw1_dc_b;
+input                                          g8t_mpw2_dc_b;
+input [0:4]                                    g8t_delay_lclkr_dc;
+input                                          d_mode_dc;
+input                                          mpw1_dc_b;
+input                                          mpw2_dc_b;
+input                                          delay_lclkr_dc;
+
+// ABIST
+input                                          wr_abst_act;
+input                                          rd0_abst_act;
+input [0:3]                                    abist_di;
+input                                          abist_bw_odd;
+input                                          abist_bw_even;
+input [0:addressbus_width-1]                   abist_wr_adr;
+input [0:addressbus_width-1]                   abist_rd0_adr;
+input                                          tc_lbist_ary_wrt_thru_dc;
+input                                          abist_ena_1;
+input                                          abist_g8t_rd0_comp_ena;
+input                                          abist_raw_dc_b;
+input [0:3]                                    obs0_abist_cmp;
+
+// Scan
+input                                          abst_scan_in;
+input                                          time_scan_in;
+input                                          repr_scan_in;
+input                                          func_scan_in;
+output                                         abst_scan_out;
+output                                         time_scan_out;
+output                                         repr_scan_out;
+output                                         func_scan_out;
+
+// BOLT-ON
+input                                          lcb_bolt_sl_thold_0;
+input                                          pc_bo_enable_2;	// general bolt-on enable
+input                                          pc_bo_reset;		// reset
+input                                          pc_bo_unload;		// unload sticky bits
+input                                          pc_bo_repair;		// execute sticky bit decode
+input                                          pc_bo_shdata;		// shift data for timing write and diag loop
+input [0:1]                                    pc_bo_select;		// select for mask and hier writes
+output [0:1]                                   bo_pc_failout;	// fail/no-fix reg
+output [0:1]                                   bo_pc_diagloop;
+input                                          tri_lcb_mpw1_dc_b;
+input                                          tri_lcb_mpw2_dc_b;
+input                                          tri_lcb_delay_lclkr_dc;
+input                                          tri_lcb_clkoff_dc_b;
+input                                          tri_lcb_act_dis_dc;
+
+// Write Ports
+input                                          write_enable;
+input [0:addressbus_width-1]                   addr_wr;
+input [0:port_bitwidth-1]                      data_in;
+
+// Read Ports
+input [0:addressbus_width-1]                   addr_rd;
+output [0:port_bitwidth-1]                     data_out;
+
+// tri_64x144_1r1w
+
+// Configuration Statement for NCsim
+//for all:RAMB36 use entity unisim.RAMB36;
+
+parameter                                      data_width = ((((port_bitwidth - 1)/36) + 1) * 36) - 1;
+parameter                                      rd_act_offset = 0;
+parameter                                      data_out_offset = rd_act_offset + 1;
+parameter                                      scan_right = data_out_offset + port_bitwidth - 1;
+
+wire [0:data_width-(data_width/9)-1]           ramb_data_in;
+wire [0:data_width/9]                          ramb_par_in;
+wire [0:data_width-(data_width/9)-1]           ramb_data_out;
+wire [0:data_width/9]                          ramb_par_out;
+wire [0:data_width-(data_width/9)-1]           ramb_data_dummy;
+wire [0:data_width/9]                          ramb_par_dummy;
+wire [0:15]                                    ramb_wr_addr;
+wire [0:15]                                    ramb_rd_addr;
+wire [0:data_width]                            data_in_pad;
+wire [0:data_width]                            data_out_pad;
+wire [0:((port_bitwidth-1)/36)]	               cascadeoutlata;
+wire [0:((port_bitwidth-1)/36)]	               cascadeoutlatb;
+wire [0:((port_bitwidth-1)/36)]	               cascadeoutrega;
+wire [0:((port_bitwidth-1)/36)]	               cascadeoutregb;
+wire                                           rd_act_d;
+wire                                           rd_act_q;
+wire [0:port_bitwidth-1]                       data_out_d;
+wire [0:port_bitwidth-1]                       data_out_q;
+
+wire                                           tiup;
+wire                                           tidn;
+wire [0:(((((port_bitwidth-1)/36)+1)*36)/9)-1] wrt_en;
+wire                                           act;
+wire [0:scan_right]                            siv;
+wire [0:scan_right]                            sov;
+
+(* analysis_not_referenced="true" *)
+wire						 unused;
+
+generate begin
+  assign tiup = 1'b1;
+  assign tidn = 1'b0;
+  assign wrt_en = {(((((port_bitwidth-1)/36)+1)*36)/9){write_enable}};
+  assign act = rd_act | wr_act;
+  assign rd_act_d = rd_act;
+
+  assign ramb_wr_addr[0] = 1'b0;
+  assign ramb_wr_addr[11:15] = 5'b0;
+  assign ramb_rd_addr[0] = 1'b0;
+  assign ramb_rd_addr[11:15] = 5'b0;
+
+  genvar  addr;
+  for (addr = 0; addr < 10; addr = addr + 1) begin : padA0
+    if (addr < 10 - addressbus_width)
+    begin
+      assign ramb_wr_addr[addr + 1] = 1'b0;
+      assign ramb_rd_addr[addr + 1] = 1'b0;
+    end
+    if (addr >= 10 - addressbus_width)
+    begin
+      assign ramb_wr_addr[addr + 1] = addr_wr[addr - (10 - addressbus_width)];
+      assign ramb_rd_addr[addr + 1] = addr_rd[addr - (10 - addressbus_width)];
+    end
+  end
+
+  // PORTA => Used for Writing
+  // PORTB => Used for Reading
+  genvar  arr;
+  for (arr = 0; arr <= (port_bitwidth - 1)/36; arr = arr + 1)
+  begin : padD0
+    genvar  bit;
+    for (bit = 0; bit < 36; bit = bit + 1)
+    begin : numBit
+      if ((arr * 36) + bit < port_bitwidth)
+      begin
+        assign data_in_pad[(arr * 36) + bit] = data_in[(arr * 36) + bit];
+      end
+      if ((arr * 36) + bit >= port_bitwidth)
+      begin
+        assign data_in_pad[(arr * 36) + bit] = 1'b0;
+      end
+    end
+  end
+
+  genvar  byte;
+  for (byte = 0; byte <= (data_width)/9; byte = byte + 1)
+  begin : dInFixUp
+    assign ramb_data_in[byte * 8:(byte * 8) + 7] = data_in_pad[(byte * 8) + byte:(byte * 8) + 7 + byte];
+    assign ramb_par_in[byte] = data_in_pad[(byte * 8) + byte + 8];
+  end
+
+  //genvar  byte;
+  for (byte = 0; byte <= (data_width)/9; byte = byte + 1)
+  begin : dOutFixUp
+    assign data_out_pad[(byte * 8) + byte:(byte * 8) + 7 + byte] = ramb_data_out[byte * 8:(byte * 8) + 7];
+    assign data_out_pad[(byte * 8) + byte + 8] = ramb_par_out[byte];
+  end
+
+  genvar  anum;
+  for (anum = 0; anum <= (port_bitwidth - 1)/36; anum = anum + 1)
+  begin : arrNum
+
+   RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) ARR(
+      .CASCADEOUTLATA(cascadeoutlata[anum]),
+      .CASCADEOUTLATB(cascadeoutlatb[anum]),
+      .CASCADEOUTREGA(cascadeoutrega[anum]),
+      .CASCADEOUTREGB(cascadeoutregb[anum]),
+      .DOA(ramb_data_dummy[(32 * anum):31 + (32 * anum)]),
+      .DOB(ramb_data_out[(32 * anum):31 + (32 * anum)]),
+      .DOPA(ramb_par_dummy[(4 * anum):3 + (4 * anum)]),
+      .DOPB(ramb_par_out[(4 * anum):3 + (4 * anum)]),
+      .ADDRA(ramb_wr_addr),
+      .ADDRB(ramb_rd_addr),
+      .CASCADEINLATA(1'b0),
+      .CASCADEINLATB(1'b0),
+      .CASCADEINREGA(1'b0),
+      .CASCADEINREGB(1'b0),
+      .CLKA(nclk[0]),
+      .CLKB(nclk[0]),
+      .DIA(ramb_data_in[(32 * anum):31 + (32 * anum)]),
+      .DIB(32'b0),
+      .DIPA(ramb_par_in[(4 * anum):3 + (4 * anum)]),
+      .DIPB(4'b0),
+      .ENA(act),
+      .ENB(act),
+      .REGCEA(1'b0),
+      .REGCEB(1'b0),
+      .SSRA(nclk[1]),        //sreset
+      .SSRB(nclk[1]),
+      .WEA(wrt_en[anum * 4:anum * 4 + 3]),
+      .WEB(4'b0)	//'
+   );
+  end
+  assign data_out_d = data_out_pad[0:port_bitwidth - 1];
+  assign data_out   = data_out_q;
+
+  assign abst_scan_out = tidn;
+  assign time_scan_out = tidn;
+  assign repr_scan_out = tidn;
+  assign bo_pc_failout = 2'b00;
+  assign bo_pc_diagloop = 2'b00;
+end
+endgenerate
+
+assign unused = | {
+  cascadeoutlata ,
+  cascadeoutlatb ,
+  cascadeoutrega ,
+  cascadeoutregb ,
+  ramb_data_dummy ,
+  ramb_par_dummy ,
+  nclk[2:`NCLK_WIDTH-1] ,
+  gnd ,
+  vdd ,
+  vcs ,
+  sg_0 ,
+  abst_sl_thold_0 ,
+  ary_nsl_thold_0 ,
+  time_sl_thold_0 ,
+  repr_sl_thold_0 ,
+  g8t_clkoff_dc_b ,
+  ccflush_dc ,
+  scan_dis_dc_b ,
+  scan_diag_dc ,
+  g8t_d_mode_dc ,
+  g8t_mpw1_dc_b ,
+  g8t_mpw2_dc_b ,
+  g8t_delay_lclkr_dc ,
+  wr_abst_act ,
+  rd0_abst_act ,
+  abist_di ,
+  abist_bw_odd ,
+  abist_bw_even ,
+  abist_wr_adr ,
+  abist_rd0_adr ,
+  tc_lbist_ary_wrt_thru_dc ,
+  abist_ena_1 ,
+  abist_g8t_rd0_comp_ena ,
+  abist_raw_dc_b ,
+  obs0_abist_cmp ,
+  abst_scan_in ,
+  time_scan_in ,
+  repr_scan_in ,
+  lcb_bolt_sl_thold_0 ,
+  pc_bo_enable_2 ,
+  pc_bo_reset ,
+  pc_bo_unload ,
+  pc_bo_repair ,
+  pc_bo_shdata ,
+  pc_bo_select ,
+  tri_lcb_mpw1_dc_b ,
+  tri_lcb_mpw2_dc_b ,
+  tri_lcb_delay_lclkr_dc ,
+  tri_lcb_clkoff_dc_b ,
+  tri_lcb_act_dis_dc };
+
+// ####################################################
+// Registers
+// ####################################################
+tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[rd_act_offset]),
+   .scout(sov[rd_act_offset]),
+   .din(rd_act_d),
+   .dout(rd_act_q)
+);
+
+tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(rd_act_q),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[data_out_offset:data_out_offset + port_bitwidth - 1]),
+   .scout(sov[data_out_offset:data_out_offset + port_bitwidth - 1]),
+   .din(data_out_d),
+   .dout(data_out_q)
+);
+
+assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
+assign func_scan_out = sov[0];
+
+endmodule

rel/src/verilog/trilib/tri_64x34_8w_1r1w.v

@@ -0,0 +1,621 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_64x34_8w_1r1w.vhdl
+// *! DESCRIPTION : 32 entry x 35 bit x 8 way array
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_64x34_8w_1r1w(
+   gnd,
+   vdd,
+   vcs,
+   nclk,
+   rd_act,
+   wr_act,
+   sg_0,
+   abst_sl_thold_0,
+   ary_nsl_thold_0,
+   time_sl_thold_0,
+   repr_sl_thold_0,
+   func_sl_force,
+   func_sl_thold_0_b,
+   g8t_clkoff_dc_b,
+   ccflush_dc,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   g8t_d_mode_dc,
+   g8t_mpw1_dc_b,
+   g8t_mpw2_dc_b,
+   g8t_delay_lclkr_dc,
+   d_mode_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   delay_lclkr_dc,
+   wr_abst_act,
+   rd0_abst_act,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   abist_rd0_adr,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp,
+   abst_scan_in,
+   time_scan_in,
+   repr_scan_in,
+   func_scan_in,
+   abst_scan_out,
+   time_scan_out,
+   repr_scan_out,
+   func_scan_out,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   write_enable,
+   way,
+   addr_wr,
+   data_in,
+   addr_rd_01,
+   addr_rd_23,
+   addr_rd_45,
+   addr_rd_67,
+   data_out
+);
+parameter                         addressable_ports = 64;		// number of addressable register in this array
+parameter                         addressbus_width = 6;		    // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
+parameter                         port_bitwidth = 34;		    // bitwidth of ports
+parameter                         ways = 8;				        // number of ways
+// POWER PINS
+inout                             gnd;
+inout                             vdd;
+inout                             vcs;
+
+// CLOCK and CLOCKCONTROL ports
+input [0:`NCLK_WIDTH-1]           nclk;
+input                             rd_act;
+input                             wr_act;
+input                             sg_0;
+input                             abst_sl_thold_0;
+input                             ary_nsl_thold_0;
+input                             time_sl_thold_0;
+input                             repr_sl_thold_0;
+input                             func_sl_force;
+input                             func_sl_thold_0_b;
+input                             g8t_clkoff_dc_b;
+input                             ccflush_dc;
+input                             scan_dis_dc_b;
+input                             scan_diag_dc;
+input                             g8t_d_mode_dc;
+input [0:4]                       g8t_mpw1_dc_b;
+input                             g8t_mpw2_dc_b;
+input [0:4]                       g8t_delay_lclkr_dc;
+input                             d_mode_dc;
+input                             mpw1_dc_b;
+input                             mpw2_dc_b;
+input                             delay_lclkr_dc;
+
+// ABIST
+input                             wr_abst_act;
+input                             rd0_abst_act;
+input [0:3]                       abist_di;
+input                             abist_bw_odd;
+input                             abist_bw_even;
+input [0:addressbus_width-1]      abist_wr_adr;
+input [0:addressbus_width-1]      abist_rd0_adr;
+input                             tc_lbist_ary_wrt_thru_dc;
+input                             abist_ena_1;
+input                             abist_g8t_rd0_comp_ena;
+input                             abist_raw_dc_b;
+input [0:3]                       obs0_abist_cmp;
+
+// SCAN
+input                             abst_scan_in;
+input                             time_scan_in;
+input                             repr_scan_in;
+input                             func_scan_in;
+output                            abst_scan_out;
+output                            time_scan_out;
+output                            repr_scan_out;
+output                            func_scan_out;
+
+// BOLT-ON
+input                             lcb_bolt_sl_thold_0;
+input                             pc_bo_enable_2;		        // general bolt-on enable
+input                             pc_bo_reset;		            // reset
+input                             pc_bo_unload;		            // unload sticky bits
+input                             pc_bo_repair;		            // execute sticky bit decode
+input                             pc_bo_shdata;		            // shift data for timing write and diag loop
+input [0:3]                       pc_bo_select;		            // select for mask and hier writes
+output [0:3]                      bo_pc_failout;		        // fail/no-fix reg
+output [0:3]                      bo_pc_diagloop;
+input                             tri_lcb_mpw1_dc_b;
+input                             tri_lcb_mpw2_dc_b;
+input                             tri_lcb_delay_lclkr_dc;
+input                             tri_lcb_clkoff_dc_b;
+input                             tri_lcb_act_dis_dc;
+
+// Write Ports
+input [0:3]                       write_enable;
+input [0:ways-1]                  way;
+input [0:addressbus_width-1]      addr_wr;
+input [0:port_bitwidth-1]         data_in;
+
+// Read Ports
+input [0:addressbus_width-1]      addr_rd_01;
+input [0:addressbus_width-1]      addr_rd_23;
+input [0:addressbus_width-1]      addr_rd_45;
+input [0:addressbus_width-1]      addr_rd_67;
+output [0:port_bitwidth*ways-1]   data_out;
+
+// tri_64x34_8w_1r1w
+parameter                           ramb_base_addr = 16;
+parameter                           dataWidth = ((((port_bitwidth - 1)/36) + 1) * 36) - 1;
+parameter                           numBytes = (dataWidth/9);
+
+// Configuration Statement for NCsim
+//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
+parameter                           rd_act_offset = 0;
+parameter                           data_out_offset = rd_act_offset + 1;
+parameter                           scan_right = data_out_offset + (ways*port_bitwidth) - 1;
+
+wire [0:35]                         ramb_data_in;
+wire [0:35]                         ramb_data_p0_out[0:ways-1];
+wire [0:(dataWidth+1)*ways-1]       ramb_data_p0_concat;
+wire [0:ramb_base_addr-1]           ramb_addr_rd1;
+wire [0:ramb_base_addr-1]           ramb_addr_wr_rd0;
+
+wire [0:ramb_base_addr-1]           rd_addr0;
+wire [0:ramb_base_addr-1]           wr_addr;
+wire                                write_en;
+wire [0:3]                          write_enable_way[0:ways-1];
+wire [0:(dataWidth-numBytes)-1]     arr_data_in;
+wire [0:numBytes]                   arr_par_in;
+wire [0:(dataWidth-numBytes)-1]     arr_data_out[0:ways-1];
+wire [0:numBytes]                   arr_par_out[0:ways-1];
+wire [0:dataWidth]                  arr_data_out_pad[0:ways-1];
+wire [0:(dataWidth+1)*ways-1]       arr_data_concat;
+wire [0:port_bitwidth*ways-1]       data_out_d;
+wire [0:port_bitwidth*ways-1]       data_out_q;
+wire [0:ways-1]			            cascadeoutlata;
+wire [0:ways-1]			            cascadeoutlatb;
+wire [0:ways-1]			            cascadeoutrega;
+wire [0:ways-1]			            cascadeoutregb;
+wire                                rd_act_d;
+wire                                rd_act_q;
+
+(* analysis_not_referenced="true" *)
+wire				                unused;
+wire                                tiup;
+wire [0:35]                         tidn;
+wire [0:scan_right]                 siv;
+wire [0:scan_right]                 sov;
+
+generate begin
+
+  assign tiup = 1'b1;
+  assign tidn = 36'b0;
+
+  // Data Generate
+  genvar  t;
+  for (t = 0; t < 36; t = t + 1)
+  begin : addr_calc
+    if (t < 35 - (port_bitwidth - 1))
+    begin
+      assign ramb_data_in[t] = 1'b0;
+    end
+    if (t >= 35 - (port_bitwidth - 1))
+    begin
+      assign ramb_data_in[t] = data_in[t - (35 - (port_bitwidth - 1))];
+    end
+  end
+
+  genvar  byte;
+  for (byte = 0; byte <= numBytes; byte = byte + 1)  begin : dFixUp
+    assign arr_data_in[byte*8:(byte*8)+7] = ramb_data_in[(byte * 8)+byte:(((byte*8)+7)+byte)];
+    assign arr_par_in[byte]		          = ramb_data_in[(((byte*8)+byte)+8)];
+    genvar numWays;
+    for (numWays=0; numWays<ways; numWays=numWays+1) begin : wayRd
+      assign arr_data_out_pad[numWays][(byte * 8) + byte:(((byte * 8) + 7) + byte)] = arr_data_out[numWays][byte * 8:(byte * 8) + 7];
+      assign arr_data_out_pad[numWays][(((byte * 8) + byte) + 8)]		            = arr_par_out[numWays][byte];
+    end
+  end
+
+  // Read/Write Port Address Generate
+  assign rd_addr0[1] = 1'b0;
+  assign rd_addr0[0] = 1'b0;
+  assign rd_addr0[11:15] = 5'b0;
+  assign wr_addr[1] = 1'b0;
+  assign wr_addr[0] = 1'b0;
+  assign wr_addr[11:15] = 5'b0;
+
+  for (t = 0; t < 9; t = t + 1) begin : rambAddrCalc
+    if (t < 9 - addressbus_width) begin
+      assign rd_addr0[t+2] = 1'b0;
+      assign wr_addr[t+2] = 1'b0;
+    end
+    if (t >= 9 - addressbus_width) begin
+      assign rd_addr0[t+2] = addr_rd_01[t - (9 - addressbus_width)];
+      assign wr_addr[t+2] = addr_wr[t - (9 - addressbus_width)];
+    end
+  end
+
+  genvar numWays;
+  for (numWays=0; numWays<ways; numWays=numWays+1) begin : dOut
+    assign data_out_d[(numWays*port_bitwidth):(numWays*port_bitwidth)+port_bitwidth-1] = arr_data_out_pad[numWays][(35 - (port_bitwidth - 1)):35];
+    assign arr_data_concat[(numWays*(dataWidth+1)):(numWays*(dataWidth+1))+(dataWidth+1)-1]     = arr_data_out_pad[numWays];
+    assign ramb_data_p0_concat[(numWays*(dataWidth+1)):(numWays*(dataWidth+1))+(dataWidth+1)-1] = ramb_data_p0_out[numWays];
+    assign write_enable_way[numWays] = {4{write_enable[numWays/2] & way[numWays]}};
+  end
+
+end
+endgenerate
+
+// Writing on PortA
+// Reading on PortB
+assign ramb_addr_rd1 = rd_addr0;
+assign write_en = |(write_enable);
+assign ramb_addr_wr_rd0 = wr_addr;
+assign rd_act_d = rd_act;
+assign data_out = data_out_q;
+
+// all, none, warning_only, generate_x_only
+RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr0_A(
+   .CASCADEOUTLATA(cascadeoutlata[0]),
+   .CASCADEOUTLATB(cascadeoutlatb[0]),
+   .CASCADEOUTREGA(cascadeoutrega[0]),
+   .CASCADEOUTREGB(cascadeoutregb[0]),
+   .DOA(ramb_data_p0_out[0][0:31]),
+   .DOB(arr_data_out[0]),
+   .DOPA(ramb_data_p0_out[0][32:35]),
+   .DOPB(arr_par_out[0]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CASCADEINLATA(1'b0),
+   .CASCADEINLATB(1'b0),
+   .CASCADEINREGA(1'b0),
+   .CASCADEINREGB(1'b0),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(arr_data_in),
+   .DIB(tidn[0:31]),
+   .DIPA(arr_par_in),
+   .DIPB(tidn[32:35]),
+   .ENA(write_en),
+   .ENB(rd_act),
+   .REGCEA(1'b0),
+   .REGCEB(1'b0),
+   .SSRA(nclk[1]),   //sreset
+   .SSRB(nclk[1]),   //sreset
+   .WEA(write_enable_way[0]),
+   .WEB(tidn[0:3])
+);
+
+// all, none, warning_only, generate_x_only
+RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr1_B(
+   .CASCADEOUTLATA(cascadeoutlata[1]),
+   .CASCADEOUTLATB(cascadeoutlatb[1]),
+   .CASCADEOUTREGA(cascadeoutrega[1]),
+   .CASCADEOUTREGB(cascadeoutregb[1]),
+   .DOA(ramb_data_p0_out[1][0:31]),
+   .DOB(arr_data_out[1]),
+   .DOPA(ramb_data_p0_out[1][32:35]),
+   .DOPB(arr_par_out[1]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CASCADEINLATA(1'b0),
+   .CASCADEINLATB(1'b0),
+   .CASCADEINREGA(1'b0),
+   .CASCADEINREGB(1'b0),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(arr_data_in),
+   .DIB(tidn[0:31]),
+   .DIPA(arr_par_in),
+   .DIPB(tidn[32:35]),
+   .ENA(write_en),
+   .ENB(rd_act),
+   .REGCEA(1'b0),
+   .REGCEB(1'b0),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_way[1]),
+   .WEB(tidn[0:3])
+);
+
+// all, none, warning_only, generate_x_only
+RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr2_C(
+   .CASCADEOUTLATA(cascadeoutlata[2]),
+   .CASCADEOUTLATB(cascadeoutlatb[2]),
+   .CASCADEOUTREGA(cascadeoutrega[2]),
+   .CASCADEOUTREGB(cascadeoutregb[2]),
+   .DOA(ramb_data_p0_out[2][0:31]),
+   .DOB(arr_data_out[2]),
+   .DOPA(ramb_data_p0_out[2][32:35]),
+   .DOPB(arr_par_out[2]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CASCADEINLATA(1'b0),
+   .CASCADEINLATB(1'b0),
+   .CASCADEINREGA(1'b0),
+   .CASCADEINREGB(1'b0),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(arr_data_in),
+   .DIB(tidn[0:31]),
+   .DIPA(arr_par_in),
+   .DIPB(tidn[32:35]),
+   .ENA(write_en),
+   .ENB(rd_act),
+   .REGCEA(1'b0),
+   .REGCEB(1'b0),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_way[2]),
+   .WEB(tidn[0:3])
+);
+
+// all, none, warning_only, generate_x_only
+RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr3_D(
+   .CASCADEOUTLATA(cascadeoutlata[3]),
+   .CASCADEOUTLATB(cascadeoutlatb[3]),
+   .CASCADEOUTREGA(cascadeoutrega[3]),
+   .CASCADEOUTREGB(cascadeoutregb[3]),
+   .DOA(ramb_data_p0_out[3][0:31]),
+   .DOB(arr_data_out[3]),
+   .DOPA(ramb_data_p0_out[3][32:35]),
+   .DOPB(arr_par_out[3]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CASCADEINLATA(1'b0),
+   .CASCADEINLATB(1'b0),
+   .CASCADEINREGA(1'b0),
+   .CASCADEINREGB(1'b0),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(arr_data_in),
+   .DIB(tidn[0:31]),
+   .DIPA(arr_par_in),
+   .DIPB(tidn[32:35]),
+   .ENA(write_en),
+   .ENB(rd_act),
+   .REGCEA(1'b0),
+   .REGCEB(1'b0),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_way[3]),
+   .WEB(tidn[0:3])
+);
+
+// all, none, warning_only, generate_x_only
+RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr4_E(
+   .CASCADEOUTLATA(cascadeoutlata[4]),
+   .CASCADEOUTLATB(cascadeoutlatb[4]),
+   .CASCADEOUTREGA(cascadeoutrega[4]),
+   .CASCADEOUTREGB(cascadeoutregb[4]),
+   .DOA(ramb_data_p0_out[4][0:31]),
+   .DOB(arr_data_out[4]),
+   .DOPA(ramb_data_p0_out[4][32:35]),
+   .DOPB(arr_par_out[4]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CASCADEINLATA(1'b0),
+   .CASCADEINLATB(1'b0),
+   .CASCADEINREGA(1'b0),
+   .CASCADEINREGB(1'b0),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(arr_data_in),
+   .DIB(tidn[0:31]),
+   .DIPA(arr_par_in),
+   .DIPB(tidn[32:35]),
+   .ENA(write_en),
+   .ENB(rd_act),
+   .REGCEA(1'b0),
+   .REGCEB(1'b0),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_way[4]),
+   .WEB(tidn[0:3])
+);
+
+// all, none, warning_only, generate_x_only
+RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr5_F(
+   .CASCADEOUTLATA(cascadeoutlata[5]),
+   .CASCADEOUTLATB(cascadeoutlatb[5]),
+   .CASCADEOUTREGA(cascadeoutrega[5]),
+   .CASCADEOUTREGB(cascadeoutregb[5]),
+   .DOA(ramb_data_p0_out[5][0:31]),
+   .DOB(arr_data_out[5]),
+   .DOPA(ramb_data_p0_out[5][32:35]),
+   .DOPB(arr_par_out[5]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CASCADEINLATA(1'b0),
+   .CASCADEINLATB(1'b0),
+   .CASCADEINREGA(1'b0),
+   .CASCADEINREGB(1'b0),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(arr_data_in),
+   .DIB(tidn[0:31]),
+   .DIPA(arr_par_in),
+   .DIPB(tidn[32:35]),
+   .ENA(write_en),
+   .ENB(rd_act),
+   .REGCEA(1'b0),
+   .REGCEB(1'b0),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_way[5]),
+   .WEB(tidn[0:3])
+);
+
+// all, none, warning_only, generate_x_only
+RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr6_G(
+   .CASCADEOUTLATA(cascadeoutlata[6]),
+   .CASCADEOUTLATB(cascadeoutlatb[6]),
+   .CASCADEOUTREGA(cascadeoutrega[6]),
+   .CASCADEOUTREGB(cascadeoutregb[6]),
+   .DOA(ramb_data_p0_out[6][0:31]),
+   .DOB(arr_data_out[6]),
+   .DOPA(ramb_data_p0_out[6][32:35]),
+   .DOPB(arr_par_out[6]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CASCADEINLATA(1'b0),
+   .CASCADEINLATB(1'b0),
+   .CASCADEINREGA(1'b0),
+   .CASCADEINREGB(1'b0),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(arr_data_in),
+   .DIB(tidn[0:31]),
+   .DIPA(arr_par_in),
+   .DIPB(tidn[32:35]),
+   .ENA(write_en),
+   .ENB(rd_act),
+   .REGCEA(1'b0),
+   .REGCEB(1'b0),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_way[6]),
+   .WEB(tidn[0:3])
+);
+
+// all, none, warning_only, generate_x_only
+RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) arr7_H(
+   .CASCADEOUTLATA(cascadeoutlata[7]),
+   .CASCADEOUTLATB(cascadeoutlatb[7]),
+   .CASCADEOUTREGA(cascadeoutrega[7]),
+   .CASCADEOUTREGB(cascadeoutregb[7]),
+   .DOA(ramb_data_p0_out[7][0:31]),
+   .DOB(arr_data_out[7]),
+   .DOPA(ramb_data_p0_out[7][32:35]),
+   .DOPB(arr_par_out[7]),
+   .ADDRA(ramb_addr_wr_rd0),
+   .ADDRB(ramb_addr_rd1),
+   .CASCADEINLATA(1'b0),
+   .CASCADEINLATB(1'b0),
+   .CASCADEINREGA(1'b0),
+   .CASCADEINREGB(1'b0),
+   .CLKA(nclk[0]),
+   .CLKB(nclk[0]),
+   .DIA(arr_data_in),
+   .DIB(tidn[0:31]),
+   .DIPA(arr_par_in),
+   .DIPB(tidn[32:35]),
+   .ENA(write_en),
+   .ENB(rd_act),
+   .REGCEA(1'b0),
+   .REGCEB(1'b0),
+   .SSRA(nclk[1]),
+   .SSRB(nclk[1]),
+   .WEA(write_enable_way[7]),
+   .WEB(tidn[0:3])
+);
+
+assign abst_scan_out = tidn[0];
+assign time_scan_out = tidn[0];
+assign repr_scan_out = tidn[0];
+assign bo_pc_failout = tidn[0:3];
+assign bo_pc_diagloop = tidn[0:3];
+
+assign unused = |({cascadeoutlata, cascadeoutlatb, cascadeoutrega, cascadeoutregb, tiup, wr_act,
+                   ramb_data_p0_concat, nclk[2:`NCLK_WIDTH-1], gnd, vdd, vcs, sg_0, abst_sl_thold_0, ary_nsl_thold_0,
+                   time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc,
+                   g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di,
+                   abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1,
+                   abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in,
+                   lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
+                   pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
+                   tri_lcb_act_dis_dc, addr_rd_23, addr_rd_45, addr_rd_67, arr_data_concat});
+
+// ####################################################
+// Registers
+// ####################################################
+
+tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[rd_act_offset]),
+   .scout(sov[rd_act_offset]),
+   .din(rd_act_d),
+   .dout(rd_act_q)
+);
+
+tri_rlmreg_p #(.WIDTH((ways*port_bitwidth)), .INIT(0), .NEEDS_SRESET(1)) data_out_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(rd_act_q),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[data_out_offset:data_out_offset + (ways*port_bitwidth) - 1]),
+   .scout(sov[data_out_offset:data_out_offset + (ways*port_bitwidth) - 1]),
+   .din(data_out_d),
+   .dout(data_out_q)
+);
+
+assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
+assign func_scan_out = sov[0];
+
+endmodule

rel/src/verilog/trilib/tri_64x72_1r1w.v

@@ -0,0 +1,298 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 fs / 1 fs
+
+//*****************************************************************************
+//  Description:  Tri-Lam Array Wrapper
+//
+//*****************************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_64x72_1r1w(
+   vdd,
+   vcs,
+   gnd,
+   nclk,
+   sg_0,
+   abst_sl_thold_0,
+   ary_nsl_thold_0,
+   time_sl_thold_0,
+   repr_sl_thold_0,
+   rd0_act,
+   rd0_adr,
+   do0,
+   wr_act,
+   wr_adr,
+   di,
+   abst_scan_in,
+   abst_scan_out,
+   time_scan_in,
+   time_scan_out,
+   repr_scan_in,
+   repr_scan_out,
+   scan_dis_dc_b,
+   scan_diag_dc,
+   ccflush_dc,
+   clkoff_dc_b,
+   d_mode_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   delay_lclkr_dc,
+   lcb_bolt_sl_thold_0,
+   pc_bo_enable_2,
+   pc_bo_reset,
+   pc_bo_unload,
+   pc_bo_repair,
+   pc_bo_shdata,
+   pc_bo_select,
+   bo_pc_failout,
+   bo_pc_diagloop,
+   tri_lcb_mpw1_dc_b,
+   tri_lcb_mpw2_dc_b,
+   tri_lcb_delay_lclkr_dc,
+   tri_lcb_clkoff_dc_b,
+   tri_lcb_act_dis_dc,
+   abist_di,
+   abist_bw_odd,
+   abist_bw_even,
+   abist_wr_adr,
+   wr_abst_act,
+   abist_rd0_adr,
+   rd0_abst_act,
+   tc_lbist_ary_wrt_thru_dc,
+   abist_ena_1,
+   abist_g8t_rd0_comp_ena,
+   abist_raw_dc_b,
+   obs0_abist_cmp
+);
+
+   // Power
+   (* analysis_not_referenced="true" *)
+   inout                               vdd;
+   (* analysis_not_referenced="true" *)
+   inout                               vcs;
+   (* analysis_not_referenced="true" *)
+   inout                               gnd;
+
+   // Clock Pervasive
+   input [0:`NCLK_WIDTH-1]             nclk;
+   input                               sg_0;
+   input                               abst_sl_thold_0;
+   input                               ary_nsl_thold_0;
+   input                               time_sl_thold_0;
+   input                               repr_sl_thold_0;
+
+   // Reads
+   input                               rd0_act;
+   input [0:5]                         rd0_adr;
+   output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0;
+
+   // Writes
+   input                               wr_act;
+   input [0:5]                         wr_adr;
+   input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)]  di;
+
+   // Scan
+   input                               abst_scan_in;
+   output                              abst_scan_out;
+   input                               time_scan_in;
+   output                              time_scan_out;
+   input                               repr_scan_in;
+   output                              repr_scan_out;
+
+   // Misc Pervasive
+   input                               scan_dis_dc_b;
+   input                               scan_diag_dc;
+   input                               ccflush_dc;
+   input                               clkoff_dc_b;
+   input                               d_mode_dc;
+   input [0:4]                         mpw1_dc_b;
+   input                               mpw2_dc_b;
+   input [0:4]                         delay_lclkr_dc;
+
+   // BOLT-ON
+   input                               lcb_bolt_sl_thold_0;
+   input                               pc_bo_enable_2;		// general bolt-on enable
+   input                               pc_bo_reset;		// reset
+   input                               pc_bo_unload;		// unload sticky bits
+   input                               pc_bo_repair;		// execute sticky bit decode
+   input                               pc_bo_shdata;		// shift data for timing write and diag loop
+   input                               pc_bo_select;		// select for mask and hier writes
+   output                              bo_pc_failout;		// fail/no-fix reg
+   output                              bo_pc_diagloop;
+   input                               tri_lcb_mpw1_dc_b;
+   input                               tri_lcb_mpw2_dc_b;
+   input                               tri_lcb_delay_lclkr_dc;
+   input                               tri_lcb_clkoff_dc_b;
+   input                               tri_lcb_act_dis_dc;
+
+   // ABIST
+   input [0:3]                         abist_di;
+   input                               abist_bw_odd;
+   input                               abist_bw_even;
+   input [0:5]                         abist_wr_adr;
+   input                               wr_abst_act;
+   input [0:5]                         abist_rd0_adr;
+   input                               rd0_abst_act;
+   input                               tc_lbist_ary_wrt_thru_dc;
+   input                               abist_ena_1;
+   input                               abist_g8t_rd0_comp_ena;
+   input                               abist_raw_dc_b;
+   input [0:3]                         obs0_abist_cmp;
+
+   // Configuration Statement for NCsim
+   //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
+
+   wire                                clk;
+   wire                                clk2x;
+   reg [0:8]                           addra;
+   reg [0:8]                           addrb;
+   reg                                 wea;
+   reg                                 web;
+   wire [0:71]                         bdo;
+   wire [0:71]                         bdi;
+   wire                                sreset;
+   wire [0:71]                         tidn;
+   // Latches
+   reg                                 reset_q;
+   reg                                 gate_fq;
+   wire                                gate_d;
+   wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)]   bdo_d;
+   reg [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)]    bdo_fq;
+
+   wire                                toggle_d;
+   reg                                 toggle_q;
+   wire                                toggle2x_d;
+   reg                                 toggle2x_q;
+
+   (* analysis_not_referenced="true" *)
+   wire                                unused;
+
+   generate
+   begin
+     assign tidn = 72'b0;
+     assign clk = nclk[0];
+     assign clk2x = nclk[2];
+     assign sreset = nclk[1];
+
+     always @(posedge clk)
+     begin: rlatch
+       reset_q <= #10 sreset;
+     end
+
+     //
+     //  NEW clk2x gate logic start
+     //
+
+     always @(posedge clk)
+     begin: tlatch
+       if (reset_q == 1'b1)
+         toggle_q <= 1'b1;
+       else
+         toggle_q <= toggle_d;
+     end
+
+     always @(posedge clk2x)
+     begin: flatch
+       toggle2x_q <= toggle2x_d;
+       gate_fq <= gate_d;
+       bdo_fq <= bdo_d;
+     end
+
+     assign toggle_d = (~toggle_q);
+     assign toggle2x_d = toggle_q;
+
+     // should force gate_fq to be on during odd 2x clock (second half of 1x clock).
+     //gate_d <= toggle_q xor toggle2x_q;
+     // if you want the first half do the following
+     assign gate_d = (~(toggle_q ^ toggle2x_q));
+
+     //
+     //  NEW clk2x gate logic end
+     //
+
+     if (`GPR_WIDTH == 32)
+     begin
+       assign bdi = {tidn[0:31], di[32:63], di[64:70], tidn[71]};
+     end
+     if (`GPR_WIDTH == 64)
+     begin
+       assign bdi = di[0:71];
+     end
+
+     assign bdo_d = bdo[64 - `GPR_WIDTH:72 - (64/`GPR_WIDTH)];
+     assign do0 = bdo_fq;
+
+     always @ ( * )
+     begin
+       wea <= #10 (wr_act & gate_fq);
+       web <= #10 (wr_act & gate_fq);
+
+       addra <= #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} :
+                                         {2'b00, rd0_adr, 1'b0});
+
+       addrb <= #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} :
+                                         {2'b00, rd0_adr, 1'b1});
+     end
+
+     RAMB16_S36_S36
+       #(.SIM_COLLISION_CHECK("NONE"))      // all, none, warning_only, generate_x_only
+     bram0a(
+         .CLKA(clk2x),
+         .CLKB(clk2x),
+         .SSRA(sreset),
+         .SSRB(sreset),
+         .ADDRA(addra),
+         .ADDRB(addrb),
+         .DIA(bdi[00:31]),
+         .DIB(bdi[32:63]),
+         .DIPA(bdi[64:67]),
+         .DIPB(bdi[68:71]),
+         .DOA(bdo[00:31]),
+         .DOB(bdo[32:63]),
+         .DOPA(bdo[64:67]),
+         .DOPB(bdo[68:71]),
+         .ENA(1'b1),
+         .ENB(1'b1),
+         .WEA(wea),
+         .WEB(web)
+      );
+
+     assign abst_scan_out = abst_scan_in;
+     assign time_scan_out = time_scan_in;
+     assign repr_scan_out = repr_scan_in;
+
+     assign bo_pc_failout = 1'b0;
+     assign bo_pc_diagloop = 1'b0;
+
+     assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});
+  end
+  endgenerate
+endmodule

rel/src/verilog/trilib/tri_a2o.vh

@@ -0,0 +1,167 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`ifndef _tri_a2o_vh_
+`define _tri_a2o_vh_
+
+`include "tri.vh"
+
+// Use this line for 1 thread.  Comment out for 2 thread design.
+`define THREADS1
+
+`define  gpr_t  3'b000
+`define  cr_t  3'b001
+`define  lr_t  3'b010
+`define  ctr_t  3'b011
+`define  xer_t  3'b100
+`define  spr_t  3'b101
+`define  axu0_t  3'b110
+`define  axu1_t  3'b111
+
+`ifdef THREADS1
+    `define  THREADS  1
+    `define  THREAD_POOL_ENC  0
+    `define  THREADS_POOL_ENC  0
+`else
+    `define  THREADS  2
+    `define  THREAD_POOL_ENC  1
+    `define  THREADS_POOL_ENC  1
+`endif
+`define  EFF_IFAR_ARCH  62
+`define  EFF_IFAR_WIDTH  20
+`define  EFF_IFAR   20
+`define  FPR_POOL_ENC 6
+`define  REGMODE 6
+`define  FPR_POOL 64
+`define  REAL_IFAR_WIDTH  42
+`define  EMQ_ENTRIES  4
+`define  GPR_WIDTH  64
+`define  ITAG_SIZE_ENC  7
+`define  CPL_Q_DEPTH  32
+`define  CPL_Q_DEPTH_ENC  6
+`define  GPR_WIDTH_ENC 6
+`define  GPR_POOL_ENC  6
+`define  GPR_POOL  64
+`define  GPR_UCODE_POOL  4
+`define  CR_POOL_ENC  5
+`define  CR_POOL  24
+`define  CR_UCODE_POOL  1
+`define  BR_POOL_ENC  3
+`define  BR_POOL      8
+`define  LR_POOL_ENC  3
+`define  LR_POOL  8
+`define  LR_UCODE_POOL  0
+`define  CTR_POOL_ENC  3
+`define  CTR_POOL  8
+`define  CTR_UCODE_POOL  0
+`define  XER_POOL_ENC  4
+`define  XER_POOL  12
+`define  XER_UCODE_POOL  0
+`define  LDSTQ_ENTRIES  16
+`define  LDSTQ_ENTRIES_ENC  4
+`define  STQ_ENTRIES  12
+`define  STQ_ENTRIES_ENC  4
+`define  STQ_FWD_ENTRIES  4		// number of stq entries that can be forwarded from
+`define  STQ_DATA_SIZE  64		// 64 or 128 Bit store data sizes supported
+`define  DC_SIZE  15			// 14 => 16K L1D$, 15 => 32K L1D$
+`define  CL_SIZE  6			// 6 => 64B CLINE, 7 => 128B CLINE
+`define  LMQ_ENTRIES  8
+`define  LMQ_ENTRIES_ENC  3
+`define  LGQ_ENTRIES  8
+`define  AXU_SPARE_ENC  3
+`define  RV_FX0_ENTRIES  12
+`define  RV_FX1_ENTRIES  12
+`define  RV_LQ_ENTRIES  16
+`define  RV_AXU0_ENTRIES  12
+`define  RV_AXU1_ENTRIES  0
+`define  RV_FX0_ENTRIES_ENC  4
+`define  RV_FX1_ENTRIES_ENC  4
+`define  RV_LQ_ENTRIES_ENC  4
+`define  RV_AXU0_ENTRIES_ENC  4
+`define  RV_AXU1_ENTRIES_ENC  1
+`define  UCODE_ENTRIES  8
+`define  UCODE_ENTRIES_ENC  3
+`define  FXU1_ENABLE  1
+`define  TYPE_WIDTH 3
+`define  IBUFF_INSTR_WIDTH  70
+`define  IBUFF_IFAR_WIDTH  20
+`define  IBUFF_DEPTH  16
+`define  PF_IAR_BITS  12		// number of IAR bits used by prefetch
+`define  FXU0_PIPE_START 1
+`define  FXU0_PIPE_END 8
+`define  FXU1_PIPE_START 1
+`define  FXU1_PIPE_END 5
+`define  LQ_LOAD_PIPE_START 4
+`define  LQ_LOAD_PIPE_END 8
+`define  LQ_REL_PIPE_START 2
+`define  LQ_REL_PIPE_END 4
+`define  LOAD_CREDITS   8
+`define  STORE_CREDITS 4
+`define  IUQ_ENTRIES   4 		   // Instruction Fetch Queue Size
+`define  MMQ_ENTRIES   2 		   // MMU Queue Size
+`define  CR_WIDTH 4
+`define  BUILD_PFETCH  1		   // 1=> include pfetch in the build, 0=> build without pfetch
+`define  PF_IFAR_WIDTH  12
+`define  PFETCH_INITIAL_DEPTH  0	// the initial value for the SPR that determines how many lines to prefetch
+`define  PFETCH_Q_SIZE_ENC  3		// number of bits to address queue size (3 => 8 entries, 4 => 16 entries)
+`define  PFETCH_Q_SIZE  8		   // number of entries
+`define  INCLUDE_IERAT_BYPASS  1	// 0 => Removes IERAT Bypass logic, 1=> includes (power savings)
+`define  XER_WIDTH  10
+`define  INIT_BHT  1			      // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
+`define  INIT_IUCR0  16'h00FA	   // BP enabled 
+`define  INIT_MASK  2'b10
+`define  RELQ_INCLUDE  0		   // Reload Queue Included
+
+`define  G_BRANCH_LEN  `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1
+
+// IERAT boot config entry values
+`define  IERAT_BCFG_EPN_0TO15      0
+`define  IERAT_BCFG_EPN_16TO31     0
+`define  IERAT_BCFG_EPN_32TO47     (2 ** 16) - 1   // 1 for 64K, 65535 for 4G
+`define  IERAT_BCFG_EPN_48TO51     (2 ** 4) - 1    // 15 for 64K or 4G
+`define  IERAT_BCFG_RPN_22TO31     0               // (2 ** 10) - 1  for x3ff
+`define  IERAT_BCFG_RPN_32TO47     (2 ** 16) - 1   // 1 for 64K, 8181 for 512M, 65535 for 4G
+`define  IERAT_BCFG_RPN_48TO51     (2 ** 4) - 1    // 15 for 64K or 4G
+`define  IERAT_BCFG_RPN2_32TO47    0               // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
+`define  IERAT_BCFG_RPN2_48TO51    0               // 0 to match dd1 hardwired value;  (2**4)-2 for adjacent 4K page
+`define  IERAT_BCFG_ATTR    0                      // u0-u3, endian
+
+// DERAT boot config entry values
+`define  DERAT_BCFG_EPN_0TO15      0
+`define  DERAT_BCFG_EPN_16TO31     0
+`define  DERAT_BCFG_EPN_32TO47     (2 ** 16) - 1   // 1 for 64K, 65535 for 4G
+`define  DERAT_BCFG_EPN_48TO51     (2 ** 4) - 1    // 15 for 64K or 4G
+`define  DERAT_BCFG_RPN_22TO31     0               // (2 ** 10) - 1  for x3ff
+`define  DERAT_BCFG_RPN_32TO47     (2 ** 16) - 1   // 1 for 64K, 8191 for 512M, 65535 for 4G
+`define  DERAT_BCFG_RPN_48TO51     (2 ** 4) - 1    // 15 for 64K or 4G
+`define  DERAT_BCFG_RPN2_32TO47    0               // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
+`define  DERAT_BCFG_RPN2_48TO51    0               // 0 to match dd1 hardwired value;  (2**4)-2 for adjacent 4K page
+`define  DERAT_BCFG_ATTR    0                      // u0-u3, endian
+
+// Do NOT add any defines below this line
+`endif  //_tri_a2o_vh_

rel/src/verilog/trilib/tri_addrcmp.v

@@ -0,0 +1,101 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+//  Description:  Address Decoder
+//
+//*****************************************************************************
+
+module tri_addrcmp(
+   enable_lsb,
+   d0,
+   d1,
+   eq
+);
+
+   input        enable_lsb;		// when "0" the LSB is disabled
+   input [0:35] d0;
+   input [0:35] d1;
+   output       eq;
+
+   // tri_addrcmp
+
+      parameter    tiup = 1'b1;
+      parameter    tidn = 1'b0;
+
+      wire [0:35]  eq01_b;
+      wire [0:18]  eq02;
+      wire [0:9]   eq04_b;
+      wire [0:4]   eq08;
+      wire [0:1]   eq24_b;
+
+      assign eq01_b[0:35] = (d0[0:35] ^ d1[0:35]);
+
+      assign eq02[0] = (~(eq01_b[0] | eq01_b[1]));
+      assign eq02[1] = (~(eq01_b[2] | eq01_b[3]));
+      assign eq02[2] = (~(eq01_b[4] | eq01_b[5]));
+      assign eq02[3] = (~(eq01_b[6] | eq01_b[7]));
+      assign eq02[4] = (~(eq01_b[8] | eq01_b[9]));
+      assign eq02[5] = (~(eq01_b[10] | eq01_b[11]));
+      assign eq02[6] = (~(eq01_b[12] | eq01_b[13]));
+      assign eq02[7] = (~(eq01_b[14] | eq01_b[15]));
+      assign eq02[8] = (~(eq01_b[16] | eq01_b[17]));
+      assign eq02[9] = (~(eq01_b[18] | eq01_b[19]));
+      assign eq02[10] = (~(eq01_b[20] | eq01_b[21]));
+      assign eq02[11] = (~(eq01_b[22] | eq01_b[23]));
+      assign eq02[12] = (~(eq01_b[24] | eq01_b[25]));
+      assign eq02[13] = (~(eq01_b[26] | eq01_b[27]));
+      assign eq02[14] = (~(eq01_b[28] | eq01_b[29]));
+      assign eq02[15] = (~(eq01_b[30] | eq01_b[31]));
+      assign eq02[16] = (~(eq01_b[32] | eq01_b[33]));
+      assign eq02[17] = (~(eq01_b[34]));
+      assign eq02[18] = (~(eq01_b[35] & enable_lsb));
+
+      assign eq04_b[0] = (~(eq02[0] & eq02[1]));
+      assign eq04_b[1] = (~(eq02[2] & eq02[3]));
+      assign eq04_b[2] = (~(eq02[4] & eq02[5]));
+      assign eq04_b[3] = (~(eq02[6] & eq02[7]));
+      assign eq04_b[4] = (~(eq02[8] & eq02[9]));
+      assign eq04_b[5] = (~(eq02[10] & eq02[11]));
+      assign eq04_b[6] = (~(eq02[12] & eq02[13]));
+      assign eq04_b[7] = (~(eq02[14] & eq02[15]));
+      assign eq04_b[8] = (~(eq02[16] & eq02[17]));
+      assign eq04_b[9] = (~(eq02[18]));
+
+      assign eq08[0] = (~(eq04_b[0] | eq04_b[1]));
+      assign eq08[1] = (~(eq04_b[2] | eq04_b[3]));
+      assign eq08[2] = (~(eq04_b[4] | eq04_b[5]));
+      assign eq08[3] = (~(eq04_b[6] | eq04_b[7]));
+      assign eq08[4] = (~(eq04_b[8] | eq04_b[9]));
+
+      assign eq24_b[0] = (~(eq08[0] & eq08[1] & eq08[2]));
+      assign eq24_b[1] = (~(eq08[3] & eq08[4]));
+
+      assign eq = (~(eq24_b[0] | eq24_b[1]));		// output
+endmodule

rel/src/verilog/trilib/tri_agecmp.v

@@ -0,0 +1,60 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+//  Description:  Prioritizer
+//
+//*****************************************************************************
+
+module tri_agecmp(
+   a,
+   b,
+   a_newer_b
+);
+   parameter        SIZE = 8;
+
+   input [0:SIZE-1] a;
+   input [0:SIZE-1] b;
+   output           a_newer_b;
+
+   // tri_agecmp
+
+   wire             a_lt_b;
+   wire             a_gte_b;
+   wire             cmp_sel;
+
+   assign a_lt_b = (a[1:SIZE - 1] < b[1:SIZE - 1]) ? 1'b1 :
+   1'b0;
+
+   assign a_gte_b = (~a_lt_b);
+
+   assign cmp_sel = a[0] ~^ b[0];
+
+   assign a_newer_b = (a_lt_b & (~cmp_sel)) | (a_gte_b & cmp_sel);
+endmodule

rel/src/verilog/trilib/tri_aoi21.v

@@ -0,0 +1,68 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_nand2.v
+// *! DESCRIPTION : Three input, AOI21 gate
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_aoi21(
+   y,
+   a0,
+   a1,
+   b0
+);
+   parameter                      WIDTH = 1;
+   parameter                      BTR = "AOI21_X2M_NONE";  //Specify full BTR name, else let tool select
+   output [0:WIDTH-1]  y;
+   input [0:WIDTH-1]   a0;
+   input [0:WIDTH-1]   a1;
+   input [0:WIDTH-1]   b0;
+
+   // tri_aoi21
+   genvar 	       i;
+   wire [0:WIDTH-1]    outA;
+
+   generate
+      begin : t
+	 for (i = 0; i < WIDTH; i = i + 1)
+	   begin : w
+
+	      and I0(outA[i], a0[i], a1[i]);
+	      nor I2(y[i], outA[i], b0[i]);
+
+	   end // block: w
+      end
+
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_aoi22.v

@@ -0,0 +1,73 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_aoi22.v
+// *! DESCRIPTION : AOI22 gate
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_aoi22(
+   y,
+   a0,
+   a1,
+   b0,
+   b1
+);
+   parameter                      WIDTH = 1;
+   parameter                      BTR = "AOI22_X2M_NONE";  //Specify full BTR name, else let tool select
+   output [0:WIDTH-1]  y;
+   input [0:WIDTH-1]   a0;
+   input [0:WIDTH-1]   a1;
+   input [0:WIDTH-1]   b0;
+   input [0:WIDTH-1]   b1;
+
+   // tri_aoi22
+   genvar 	       i;
+   wire [0:WIDTH-1]    outA;
+   wire [0:WIDTH-1]    outB;
+
+   generate
+      begin : t
+	 for (i = 0; i < WIDTH; i = i + 1)
+	   begin : w
+
+	      and I0(outA[i], a0[i], a1[i]);
+	      and I1(outB[i], b0[i], b1[i]);
+	      nor I2(y[i], outA[i], outB[i]);
+
+
+	   end // block: w
+      end
+
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_aoi22_nlats_wlcb.v

@@ -0,0 +1,145 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_aoi22_nlats_wlcb.v
+// *! DESCRIPTION : Multi-bit aoi22-latch, LCB included
+// *!
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_aoi22_nlats_wlcb(
+   vd,
+   gd,
+   nclk,
+   act,
+   force_t,
+   thold_b,
+   d_mode,
+   sg,
+   delay_lclkr,
+   mpw1_b,
+   mpw2_b,
+   scin,
+   scout,
+   a1,
+   a2,
+   b1,
+   b2,
+   qb
+);
+
+   parameter                      WIDTH = 4;
+   parameter                      OFFSET = 0;		//starting bit
+   parameter                      INIT = 0;		// will be converted to the least signficant
+                                                        // 31 bits of init_v
+   parameter                      IBUF = 1'b0;		//inverted latch IOs, if set to true.
+   parameter                      DUALSCAN = "";		// if "S", marks data ports as scan for Moebius
+   parameter                      NEEDS_SRESET = 1;		// for inferred latches
+   parameter                      L2_LATCH_TYPE = 2;            //L2_LATCH_TYPE = slave_latch;
+                                                                //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
+   parameter                      SYNTHCLONEDLATCH = "";
+   parameter                      BTR = "NLL0001_X2_A12TH";
+
+   inout                          vd;
+   inout                          gd;
+   input [0:`NCLK_WIDTH-1]        nclk;
+   input                          act;		// 1: functional, 0: no clock
+   input                          force_t;		// 1: force LCB active
+   input                          thold_b;		// 1: functional, 0: no clock
+   input                          d_mode;		// 1: disable pulse mode, 0: pulse mode
+   input                          sg;		// 0: functional, 1: scan
+   input                          delay_lclkr;		// 0: functional
+   input                          mpw1_b;		// pulse width control bit
+   input                          mpw2_b;		// pulse width control bit
+   input [OFFSET:OFFSET+WIDTH-1]  scin;		// scan in
+   output [OFFSET:OFFSET+WIDTH-1] scout;
+   input [OFFSET:OFFSET+WIDTH-1]  a1;
+   input [OFFSET:OFFSET+WIDTH-1]  a2;
+   input [OFFSET:OFFSET+WIDTH-1]  b1;
+   input [OFFSET:OFFSET+WIDTH-1]  b2;
+   output [OFFSET:OFFSET+WIDTH-1] qb;
+
+   // tri_aoi22_nlats_wlcb
+
+   parameter [0:WIDTH-1]          init_v = INIT;
+   parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};
+
+   generate
+   begin
+      wire                        sreset;
+      wire [0:WIDTH-1]            int_din;
+      wire [0:WIDTH-1]            din;
+      reg [0:WIDTH-1]             int_dout;
+      wire [0:WIDTH-1]            vact;
+      wire [0:WIDTH-1]            vact_b;
+      wire [0:WIDTH-1]            vsreset;
+      wire [0:WIDTH-1]            vsreset_b;
+      wire [0:WIDTH-1]            vthold;
+      wire [0:WIDTH-1]            vthold_b;
+       (* analysis_not_referenced="true" *)
+      wire                        unused;
+
+      if (NEEDS_SRESET == 1)
+      begin : rst
+         assign sreset = nclk[1];
+      end
+      if (NEEDS_SRESET != 1)
+      begin : no_rst
+         assign sreset = 1'b0;
+      end
+
+      assign vsreset = {WIDTH{sreset}};
+      assign vsreset_b = {WIDTH{~sreset}};
+
+      assign din = (a1 & a2) | (b1 & b2);		// Output is inverted, so just AND-OR here
+      assign int_din = (vsreset_b & din) | (vsreset & init_v);
+
+      assign vact = {WIDTH{act | force_t}};
+      assign vact_b = {WIDTH{~(act | force_t)}};
+
+      assign vthold_b = {WIDTH{thold_b}};
+      assign vthold = {WIDTH{~thold_b}};
+
+
+      always @(posedge nclk[0])
+      begin: l
+        int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
+      end
+
+      assign qb = (~int_dout);
+
+      assign scout = ZEROS;
+
+      assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk) | (|scin);
+   end
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_bht_1024x8_1r1w.v

@@ -0,0 +1,577 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *********************************************************************
+//
+// This is the ENTITY for tri_bht_1024x8_1r1w
+//
+// *********************************************************************
+
+(* block_type="soft" *)
+(* recursive_synthesis="2" *)
+(* pin_default_power_domain="vdd" *)
+(* pin_default_ground_domain ="gnd" *)
+
+`include "tri_a2o.vh"
+
+module tri_bht_1024x8_1r1w(
+   gnd,
+   vdd,
+   vcs,
+   nclk,
+   pc_iu_func_sl_thold_2,
+   pc_iu_sg_2,
+   pc_iu_time_sl_thold_2,
+   pc_iu_abst_sl_thold_2,
+   pc_iu_ary_nsl_thold_2,
+   pc_iu_repr_sl_thold_2,
+   pc_iu_bolt_sl_thold_2,
+   tc_ac_ccflush_dc,
+   tc_ac_scan_dis_dc_b,
+   clkoff_b,
+   scan_diag_dc,
+   act_dis,
+   d_mode,
+   delay_lclkr,
+   mpw1_b,
+   mpw2_b,
+   g8t_clkoff_b,
+   g8t_d_mode,
+   g8t_delay_lclkr,
+   g8t_mpw1_b,
+   g8t_mpw2_b,
+   func_scan_in,
+   time_scan_in,
+   abst_scan_in,
+   repr_scan_in,
+   func_scan_out,
+   time_scan_out,
+   abst_scan_out,
+   repr_scan_out,
+   pc_iu_abist_di_0,
+   pc_iu_abist_g8t_bw_1,
+   pc_iu_abist_g8t_bw_0,
+   pc_iu_abist_waddr_0,
+   pc_iu_abist_g8t_wenb,
+   pc_iu_abist_raddr_0,
+   pc_iu_abist_g8t1p_renb_0,
+   an_ac_lbist_ary_wrt_thru_dc,
+   pc_iu_abist_ena_dc,
+   pc_iu_abist_wl128_comp_ena,
+   pc_iu_abist_raw_dc_b,
+   pc_iu_abist_g8t_dcomp,
+   pc_iu_bo_enable_2,
+   pc_iu_bo_reset,
+   pc_iu_bo_unload,
+   pc_iu_bo_repair,
+   pc_iu_bo_shdata,
+   pc_iu_bo_select,
+   iu_pc_bo_fail,
+   iu_pc_bo_diagout,
+   r_act,
+   w_act,
+   r_addr,
+   w_addr,
+   data_in,
+   data_out0,
+   data_out1,
+   data_out2,
+   data_out3,
+   pc_iu_init_reset
+);
+   // power pins
+   inout               gnd;
+   inout               vdd;
+   inout               vcs;
+
+   // clock and clockcontrol ports
+   input [0:`NCLK_WIDTH-1]              nclk;
+   input               pc_iu_func_sl_thold_2;
+   input               pc_iu_sg_2;
+   input               pc_iu_time_sl_thold_2;
+   input               pc_iu_abst_sl_thold_2;
+   input               pc_iu_ary_nsl_thold_2;
+   input               pc_iu_repr_sl_thold_2;
+   input               pc_iu_bolt_sl_thold_2;
+   input               tc_ac_ccflush_dc;
+   input               tc_ac_scan_dis_dc_b;
+   input               clkoff_b;
+   input               scan_diag_dc;
+   input               act_dis;
+   input               d_mode;
+   input               delay_lclkr;
+   input               mpw1_b;
+   input               mpw2_b;
+   input               g8t_clkoff_b;
+   input               g8t_d_mode;
+   input [0:4]         g8t_delay_lclkr;
+   input [0:4]         g8t_mpw1_b;
+   input               g8t_mpw2_b;
+   input               func_scan_in;
+   input               time_scan_in;
+   input               abst_scan_in;
+   input               repr_scan_in;
+   output              func_scan_out;
+   output              time_scan_out;
+   output              abst_scan_out;
+   output              repr_scan_out;
+
+   input [0:3]         pc_iu_abist_di_0;
+   input               pc_iu_abist_g8t_bw_1;
+   input               pc_iu_abist_g8t_bw_0;
+   input [3:9]         pc_iu_abist_waddr_0;
+   input               pc_iu_abist_g8t_wenb;
+   input [3:9]         pc_iu_abist_raddr_0;
+   input               pc_iu_abist_g8t1p_renb_0;
+   input               an_ac_lbist_ary_wrt_thru_dc;
+   input               pc_iu_abist_ena_dc;
+   input               pc_iu_abist_wl128_comp_ena;
+   input               pc_iu_abist_raw_dc_b;
+   input [0:3]         pc_iu_abist_g8t_dcomp;
+
+   // BOLT-ON
+   input               pc_iu_bo_enable_2;		// general bolt-on enable
+   input               pc_iu_bo_reset;		// reset
+   input               pc_iu_bo_unload;		// unload sticky bits
+   input               pc_iu_bo_repair;		// execute sticky bit decode
+   input               pc_iu_bo_shdata;		// shift data for timing write and diag loop
+   input               pc_iu_bo_select;		// select for mask and hier writes
+   output              iu_pc_bo_fail;		// fail/no-fix reg
+   output              iu_pc_bo_diagout;
+
+   // ports
+   input               r_act;
+   input [0:3]         w_act;
+   input [0:9]         r_addr;
+   input [0:9]         w_addr;
+   input [0:1]         data_in;
+   output [0:1]        data_out0;
+   output [0:1]        data_out1;
+   output [0:1]        data_out2;
+
+   output [0:1]        data_out3;
+
+   input               pc_iu_init_reset;
+
+   //--------------------------
+   // constants
+   //--------------------------
+
+
+      parameter           data_in_offset = 0;
+      parameter           w_act_offset = data_in_offset + 2;
+      parameter           r_act_offset = w_act_offset + 4;
+      parameter           w_addr_offset = r_act_offset + 1;
+      parameter           r_addr_offset = w_addr_offset + 10;
+      parameter           data_out_offset = r_addr_offset + 10;
+      parameter           reset_w_addr_offset = data_out_offset + 8;
+      parameter           array_offset = reset_w_addr_offset + 9;
+      parameter           scan_right = array_offset + 1 - 1;
+
+      //--------------------------
+      // signals
+      //--------------------------
+
+      wire                pc_iu_func_sl_thold_1;
+      wire                pc_iu_func_sl_thold_0;
+      wire                pc_iu_func_sl_thold_0_b;
+      wire                pc_iu_time_sl_thold_1;
+      wire                pc_iu_time_sl_thold_0;
+      wire                pc_iu_ary_nsl_thold_1;
+      wire                pc_iu_ary_nsl_thold_0;
+      wire                pc_iu_abst_sl_thold_1;
+      wire                pc_iu_abst_sl_thold_0;
+      wire                pc_iu_repr_sl_thold_1;
+      wire                pc_iu_repr_sl_thold_0;
+      wire                pc_iu_bolt_sl_thold_1;
+      wire                pc_iu_bolt_sl_thold_0;
+      wire                pc_iu_sg_1;
+      wire                pc_iu_sg_0;
+      wire                force_t;
+
+      wire [0:scan_right] siv;
+      wire [0:scan_right] sov;
+
+      wire                tiup;
+
+      wire [0:7]          data_out_d;
+      wire [0:7]          data_out_q;
+
+      wire                ary_w_en;
+      wire [0:8]          ary_w_addr;
+      wire [0:15]         ary_w_sel;
+      wire [0:15]         ary_w_data;
+
+      wire                ary_r_en;
+      wire [0:8]          ary_r_addr;
+      wire [0:15]         ary_r_data;
+
+      wire [0:7]          data_out;
+      wire [0:3]          write_thru;
+
+      wire [0:1]          data_in_d;
+      wire [0:1]          data_in_q;
+      wire [0:3]          w_act_d;
+      wire [0:3]          w_act_q;
+      wire                r_act_d;
+      wire                r_act_q;
+      wire [0:9]          w_addr_d;
+      wire [0:9]          w_addr_q;
+      wire [0:9]          r_addr_d;
+      wire [0:9]          r_addr_q;
+
+      wire                lat_wi_act;
+      wire                lat_ri_act;
+      wire                lat_ro_act;
+
+      wire		  reset_act;
+      wire [0:8]	  reset_w_addr_d;
+      wire [0:8]	  reset_w_addr_q;
+
+
+      assign tiup = 1'b1;
+
+      assign reset_act			= pc_iu_init_reset;
+      assign reset_w_addr_d[0:8]	= reset_w_addr_q[0:8] + 9'b000000001;
+
+      assign data_out0[0:1] = data_out_q[0:1];
+      assign data_out1[0:1] = data_out_q[2:3];
+      assign data_out2[0:1] = data_out_q[4:5];
+      assign data_out3[0:1] = data_out_q[6:7];
+
+      assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[1:9] == r_addr[1:9]) & r_act == 1'b1)));
+
+      assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[1:9];
+
+      assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b0;
+      assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b0;
+      assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b0;
+      assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b0;
+      assign ary_w_sel[4] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b0;
+      assign ary_w_sel[5] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b0;
+      assign ary_w_sel[6] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b0;
+      assign ary_w_sel[7] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b0;
+      assign ary_w_sel[8] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b1;
+      assign ary_w_sel[9] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b1;
+      assign ary_w_sel[10] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b1;
+      assign ary_w_sel[11] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b1;
+      assign ary_w_sel[12] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b1;
+      assign ary_w_sel[13] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b1;
+      assign ary_w_sel[14] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b1;
+      assign ary_w_sel[15] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b1;
+
+      assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000:
+                                            {(data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK)};
+
+      assign ary_r_en = r_act;
+
+      assign ary_r_addr[0:8] = r_addr[1:9];
+
+      assign data_out[0:7] = (r_addr_q[0] == 1'b0 ? ary_r_data[0:7] ^ ({`INIT_MASK, `INIT_MASK, `INIT_MASK, `INIT_MASK}) : 8'b00000000 ) | (r_addr_q[0] == 1'b1 ? ary_r_data[8:15] ^ ({`INIT_MASK, `INIT_MASK, `INIT_MASK, `INIT_MASK}) : 8'b00000000 );
+
+      //write through support
+
+      assign data_in_d[0:1] = data_in[0:1];
+      assign w_act_d[0:3] = w_act[0:3];
+      assign r_act_d = r_act;
+      assign w_addr_d[0:9] = w_addr[0:9];
+      assign r_addr_d[0:9] = r_addr[0:9];
+
+      assign write_thru[0:3] = ((w_addr_q[0:9] == r_addr_q[0:9]) & r_act_q == 1'b1) ? w_act_q[0:3] :
+                               4'b0000;
+
+      assign data_out_d[0:1] = (write_thru[0] == 1'b1) ? data_in_q[0:1] :
+                               data_out[0:1];
+      assign data_out_d[2:3] = (write_thru[1] == 1'b1) ? data_in_q[0:1] :
+                               data_out[2:3];
+      assign data_out_d[4:5] = (write_thru[2] == 1'b1) ? data_in_q[0:1] :
+                               data_out[4:5];
+      assign data_out_d[6:7] = (write_thru[3] == 1'b1) ? data_in_q[0:1] :
+                               data_out[6:7];
+
+      //latch acts
+      assign lat_wi_act = |(w_act[0:3]);
+      assign lat_ri_act = r_act;
+      assign lat_ro_act = r_act_q;
+
+      //-----------------------------------------------
+      // array
+      //-----------------------------------------------
+
+
+
+            tri_512x16_1r1w_1  bht0(
+               .gnd(gnd),
+               .vdd(vdd),
+               .vcs(vcs),
+               .nclk(nclk),
+
+               .rd_act(ary_r_en),
+               .wr_act(ary_w_en),
+
+               .lcb_d_mode_dc(g8t_d_mode),
+               .lcb_clkoff_dc_b(g8t_clkoff_b),
+               .lcb_mpw1_dc_b(g8t_mpw1_b),
+               .lcb_mpw2_dc_b(g8t_mpw2_b),
+               .lcb_delay_lclkr_dc(g8t_delay_lclkr),
+               .ccflush_dc(tc_ac_ccflush_dc),
+               .scan_dis_dc_b(tc_ac_scan_dis_dc_b),
+               .scan_diag_dc(scan_diag_dc),
+               .func_scan_in(siv[array_offset]),
+               .func_scan_out(sov[array_offset]),
+
+               .lcb_sg_0(pc_iu_sg_0),
+               .lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
+               .lcb_time_sl_thold_0(pc_iu_time_sl_thold_0),
+               .lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0),
+               .lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0),
+               .lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0),
+               .time_scan_in(time_scan_in),
+               .time_scan_out(time_scan_out),
+               .abst_scan_in(abst_scan_in),
+               .abst_scan_out(abst_scan_out),
+               .repr_scan_in(repr_scan_in),
+               .repr_scan_out(repr_scan_out),
+
+               .abist_di(pc_iu_abist_di_0),
+               .abist_bw_odd(pc_iu_abist_g8t_bw_1),
+               .abist_bw_even(pc_iu_abist_g8t_bw_0),
+               .abist_wr_adr(pc_iu_abist_waddr_0),
+               .wr_abst_act(pc_iu_abist_g8t_wenb),
+               .abist_rd0_adr(pc_iu_abist_raddr_0),
+               .rd0_abst_act(pc_iu_abist_g8t1p_renb_0),
+               .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
+               .abist_ena_1(pc_iu_abist_ena_dc),
+               .abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena),
+               .abist_raw_dc_b(pc_iu_abist_raw_dc_b),
+               .obs0_abist_cmp(pc_iu_abist_g8t_dcomp),
+
+               .lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0),
+               .pc_bo_enable_2(pc_iu_bo_enable_2),
+               .pc_bo_reset(pc_iu_bo_reset),
+               .pc_bo_unload(pc_iu_bo_unload),
+               .pc_bo_repair(pc_iu_bo_repair),
+               .pc_bo_shdata(pc_iu_bo_shdata),
+               .pc_bo_select(pc_iu_bo_select),
+               .bo_pc_failout(iu_pc_bo_fail),
+               .bo_pc_diagloop(iu_pc_bo_diagout),
+
+               .tri_lcb_mpw1_dc_b(mpw1_b),
+               .tri_lcb_mpw2_dc_b(mpw2_b),
+               .tri_lcb_delay_lclkr_dc(delay_lclkr),
+               .tri_lcb_clkoff_dc_b(clkoff_b),
+               .tri_lcb_act_dis_dc(act_dis),
+
+               .bw(ary_w_sel),
+               .wr_adr(ary_w_addr),
+               .rd_adr(ary_r_addr),
+               .di(ary_w_data),
+               .do(ary_r_data)
+            );
+
+      //-----------------------------------------------
+      // latches
+      //-----------------------------------------------
+
+
+      tri_rlmreg_p #(.WIDTH(2), .INIT(0)) data_in_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(lat_wi_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[data_in_offset:data_in_offset + 2 - 1]),
+         .scout(sov[data_in_offset:data_in_offset + 2 - 1]),
+         .din(data_in_d),
+         .dout(data_in_q)
+      );
+
+
+      tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(tiup),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[w_act_offset:w_act_offset + 4 - 1]),
+         .scout(sov[w_act_offset:w_act_offset + 4 - 1]),
+         .din(w_act_d),
+         .dout(w_act_q)
+      );
+
+
+      tri_rlmlatch_p #(.INIT(0)) r_act_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(tiup),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[r_act_offset]),
+         .scout(sov[r_act_offset]),
+         .din(r_act_d),
+         .dout(r_act_q)
+      );
+
+
+      tri_rlmreg_p #(.WIDTH(10), .INIT(0)) w_addr_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(lat_wi_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[w_addr_offset:w_addr_offset + 10 - 1]),
+         .scout(sov[w_addr_offset:w_addr_offset + 10 - 1]),
+         .din(w_addr_d),
+         .dout(w_addr_q)
+      );
+
+
+      tri_rlmreg_p #(.WIDTH(10), .INIT(0)) r_addr_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(lat_ri_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[r_addr_offset:r_addr_offset + 10 - 1]),
+         .scout(sov[r_addr_offset:r_addr_offset + 10 - 1]),
+         .din(r_addr_d),
+         .dout(r_addr_q)
+      );
+
+
+      tri_rlmreg_p #(.WIDTH(8), .INIT(0)) data_out_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(lat_ro_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[data_out_offset:data_out_offset + 8 - 1]),
+         .scout(sov[data_out_offset:data_out_offset + 8 - 1]),
+         .din(data_out_d),
+         .dout(data_out_q)
+      );
+
+      tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(reset_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
+         .scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
+         .din(reset_w_addr_d),
+         .dout(reset_w_addr_q)
+      );
+
+      //-----------------------------------------------
+      // pervasive
+      //-----------------------------------------------
+
+
+      tri_plat #(.WIDTH(7)) perv_2to1_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .flush(tc_ac_ccflush_dc),
+         .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}),
+         .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1})
+      );
+
+
+      tri_plat #(.WIDTH(7)) perv_1to0_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .flush(tc_ac_ccflush_dc),
+         .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}),
+         .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0})
+      );
+
+
+      tri_lcbor  perv_lcbor(
+         .clkoff_b(clkoff_b),
+         .thold(pc_iu_func_sl_thold_0),
+         .sg(pc_iu_sg_0),
+         .act_dis(act_dis),
+         .force_t(force_t),
+         .thold_b(pc_iu_func_sl_thold_0_b)
+      );
+
+      //-----------------------------------------------
+      // scan
+      //-----------------------------------------------
+
+      assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]};
+      assign func_scan_out = sov[scan_right];
+
+
+endmodule

rel/src/verilog/trilib/tri_bht_512x4_1r1w.v

@@ -0,0 +1,577 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *********************************************************************
+//
+// This is the ENTITY for tri_bht_512x4_1r1w
+//
+// *********************************************************************
+
+(* block_type="soft" *)
+(* recursive_synthesis="2" *)
+(* pin_default_power_domain="vdd" *)
+(* pin_default_ground_domain ="gnd" *)
+
+`include "tri_a2o.vh"
+
+module tri_bht_512x4_1r1w(
+   gnd,
+   vdd,
+   vcs,
+   nclk,
+   pc_iu_func_sl_thold_2,
+   pc_iu_sg_2,
+   pc_iu_time_sl_thold_2,
+   pc_iu_abst_sl_thold_2,
+   pc_iu_ary_nsl_thold_2,
+   pc_iu_repr_sl_thold_2,
+   pc_iu_bolt_sl_thold_2,
+   tc_ac_ccflush_dc,
+   tc_ac_scan_dis_dc_b,
+   clkoff_b,
+   scan_diag_dc,
+   act_dis,
+   d_mode,
+   delay_lclkr,
+   mpw1_b,
+   mpw2_b,
+   g8t_clkoff_b,
+   g8t_d_mode,
+   g8t_delay_lclkr,
+   g8t_mpw1_b,
+   g8t_mpw2_b,
+   func_scan_in,
+   time_scan_in,
+   abst_scan_in,
+   repr_scan_in,
+   func_scan_out,
+   time_scan_out,
+   abst_scan_out,
+   repr_scan_out,
+   pc_iu_abist_di_0,
+   pc_iu_abist_g8t_bw_1,
+   pc_iu_abist_g8t_bw_0,
+   pc_iu_abist_waddr_0,
+   pc_iu_abist_g8t_wenb,
+   pc_iu_abist_raddr_0,
+   pc_iu_abist_g8t1p_renb_0,
+   an_ac_lbist_ary_wrt_thru_dc,
+   pc_iu_abist_ena_dc,
+   pc_iu_abist_wl128_comp_ena,
+   pc_iu_abist_raw_dc_b,
+   pc_iu_abist_g8t_dcomp,
+   pc_iu_bo_enable_2,
+   pc_iu_bo_reset,
+   pc_iu_bo_unload,
+   pc_iu_bo_repair,
+   pc_iu_bo_shdata,
+   pc_iu_bo_select,
+   iu_pc_bo_fail,
+   iu_pc_bo_diagout,
+   r_act,
+   w_act,
+   r_addr,
+   w_addr,
+   data_in,
+   data_out0,
+   data_out1,
+   data_out2,
+   data_out3,
+   pc_iu_init_reset
+);
+   // power pins
+   inout               gnd;
+   inout               vdd;
+   inout               vcs;
+
+   // clock and clockcontrol ports
+   input [0:`NCLK_WIDTH-1]              nclk;
+   input               pc_iu_func_sl_thold_2;
+   input               pc_iu_sg_2;
+   input               pc_iu_time_sl_thold_2;
+   input               pc_iu_abst_sl_thold_2;
+   input               pc_iu_ary_nsl_thold_2;
+   input               pc_iu_repr_sl_thold_2;
+   input               pc_iu_bolt_sl_thold_2;
+   input               tc_ac_ccflush_dc;
+   input               tc_ac_scan_dis_dc_b;
+   input               clkoff_b;
+   input               scan_diag_dc;
+   input               act_dis;
+   input               d_mode;
+   input               delay_lclkr;
+   input               mpw1_b;
+   input               mpw2_b;
+   input               g8t_clkoff_b;
+   input               g8t_d_mode;
+   input [0:4]         g8t_delay_lclkr;
+   input [0:4]         g8t_mpw1_b;
+   input               g8t_mpw2_b;
+   input               func_scan_in;
+   input               time_scan_in;
+   input               abst_scan_in;
+   input               repr_scan_in;
+   output              func_scan_out;
+   output              time_scan_out;
+   output              abst_scan_out;
+   output              repr_scan_out;
+
+   input [0:3]         pc_iu_abist_di_0;
+   input               pc_iu_abist_g8t_bw_1;
+   input               pc_iu_abist_g8t_bw_0;
+   input [3:9]         pc_iu_abist_waddr_0;
+   input               pc_iu_abist_g8t_wenb;
+   input [3:9]         pc_iu_abist_raddr_0;
+   input               pc_iu_abist_g8t1p_renb_0;
+   input               an_ac_lbist_ary_wrt_thru_dc;
+   input               pc_iu_abist_ena_dc;
+   input               pc_iu_abist_wl128_comp_ena;
+   input               pc_iu_abist_raw_dc_b;
+   input [0:3]         pc_iu_abist_g8t_dcomp;
+
+   // BOLT-ON
+   input               pc_iu_bo_enable_2;		// general bolt-on enable
+   input               pc_iu_bo_reset;		// reset
+   input               pc_iu_bo_unload;		// unload sticky bits
+   input               pc_iu_bo_repair;		// execute sticky bit decode
+   input               pc_iu_bo_shdata;		// shift data for timing write and diag loop
+   input               pc_iu_bo_select;		// select for mask and hier writes
+   output              iu_pc_bo_fail;		// fail/no-fix reg
+   output              iu_pc_bo_diagout;
+
+   // ports
+   input               r_act;
+   input [0:3]         w_act;
+   input [0:8]         r_addr;
+   input [0:8]         w_addr;
+   input	       data_in;
+   output              data_out0;
+   output              data_out1;
+   output              data_out2;
+   output              data_out3;
+
+   input               pc_iu_init_reset;
+
+   //--------------------------
+   // constants
+   //--------------------------
+
+
+      parameter           data_in_offset = 0;
+      parameter           w_act_offset = data_in_offset + 1;
+      parameter           r_act_offset = w_act_offset + 4;
+      parameter           w_addr_offset = r_act_offset + 1;
+      parameter           r_addr_offset = w_addr_offset + 9;
+      parameter           data_out_offset = r_addr_offset + 9;
+      parameter           reset_w_addr_offset = data_out_offset + 4;
+      parameter           array_offset = reset_w_addr_offset + 9;
+      parameter           scan_right = array_offset + 1 - 1;
+
+      //--------------------------
+      // signals
+      //--------------------------
+
+      wire                pc_iu_func_sl_thold_1;
+      wire                pc_iu_func_sl_thold_0;
+      wire                pc_iu_func_sl_thold_0_b;
+      wire                pc_iu_time_sl_thold_1;
+      wire                pc_iu_time_sl_thold_0;
+      wire                pc_iu_ary_nsl_thold_1;
+      wire                pc_iu_ary_nsl_thold_0;
+      wire                pc_iu_abst_sl_thold_1;
+      wire                pc_iu_abst_sl_thold_0;
+      wire                pc_iu_repr_sl_thold_1;
+      wire                pc_iu_repr_sl_thold_0;
+      wire                pc_iu_bolt_sl_thold_1;
+      wire                pc_iu_bolt_sl_thold_0;
+      wire                pc_iu_sg_1;
+      wire                pc_iu_sg_0;
+      wire                force_t;
+
+      wire [0:scan_right] siv;
+      wire [0:scan_right] sov;
+
+      wire                tiup;
+
+      wire [0:3]          data_out_d;
+      wire [0:3]          data_out_q;
+
+      wire                ary_w_en;
+      wire [0:8]          ary_w_addr;
+      wire [0:15]         ary_w_sel;
+      wire [0:15]         ary_w_data;
+
+      wire                ary_r_en;
+      wire [0:8]          ary_r_addr;
+      wire [0:15]         ary_r_data;
+
+      wire [0:3]          data_out;
+      wire [0:3]          write_thru;
+
+      wire                data_in_d;
+      wire                data_in_q;
+      wire [0:3]          w_act_d;
+      wire [0:3]          w_act_q;
+      wire                r_act_d;
+      wire                r_act_q;
+      wire [0:8]          w_addr_d;
+      wire [0:8]          w_addr_q;
+      wire [0:8]          r_addr_d;
+      wire [0:8]          r_addr_q;
+
+      wire                lat_wi_act;
+      wire                lat_ri_act;
+      wire                lat_ro_act;
+
+      wire		  reset_act;
+      wire [0:8]	  reset_w_addr_d;
+      wire [0:8]	  reset_w_addr_q;
+
+
+
+      assign tiup = 1'b1;
+
+      assign reset_act			= pc_iu_init_reset;
+      assign reset_w_addr_d[0:8]	= reset_w_addr_q[0:8] + 9'b000000001;
+
+      assign data_out0 = data_out_q[0];
+      assign data_out1 = data_out_q[1];
+      assign data_out2 = data_out_q[2];
+      assign data_out3 = data_out_q[3];
+
+      assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[0:8] == r_addr[0:8]) & r_act == 1'b1)));
+
+      assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[0:8];
+
+      assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0];
+      assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[1];
+      assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[2];
+      assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[3];
+      assign ary_w_sel[4] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[5] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[6] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[7] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[8] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[9] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[10] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[11] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[12] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[13] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[14] = reset_act ? 1'b1 : 1'b0;
+      assign ary_w_sel[15] = reset_act ? 1'b1 : 1'b0;
+
+      assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000:
+                                            {data_in, data_in, data_in, data_in, 12'b000000000000};
+
+      assign ary_r_en = r_act;
+
+      assign ary_r_addr[0:8] = r_addr[0:8];
+
+      assign data_out[0:3] = ary_r_data[0:3];
+
+      //write through support
+
+      assign data_in_d = data_in;
+      assign w_act_d[0:3] = w_act[0:3];
+      assign r_act_d = r_act;
+      assign w_addr_d[0:8] = w_addr[0:8];
+      assign r_addr_d[0:8] = r_addr[0:8];
+
+      assign write_thru[0:3] = ((w_addr_q[0:8] == r_addr_q[0:8]) & r_act_q == 1'b1) ? w_act_q[0:3] :
+                               4'b0000;
+
+      assign data_out_d[0] = (write_thru[0] == 1'b1) ? data_in_q :
+                              data_out[0];
+      assign data_out_d[1] = (write_thru[1] == 1'b1) ? data_in_q :
+                              data_out[1];
+      assign data_out_d[2] = (write_thru[2] == 1'b1) ? data_in_q :
+                              data_out[2];
+      assign data_out_d[3] = (write_thru[3] == 1'b1) ? data_in_q :
+                              data_out[3];
+
+      //latch acts
+      assign lat_wi_act = |(w_act[0:3]);
+      assign lat_ri_act = r_act;
+      assign lat_ro_act = r_act_q;
+
+      //-----------------------------------------------
+      // array
+      //-----------------------------------------------
+
+
+
+            tri_512x16_1r1w_1  bht0(
+               .gnd(gnd),
+               .vdd(vdd),
+               .vcs(vcs),
+               .nclk(nclk),
+
+               .rd_act(ary_r_en),
+               .wr_act(ary_w_en),
+
+               .lcb_d_mode_dc(g8t_d_mode),
+               .lcb_clkoff_dc_b(g8t_clkoff_b),
+               .lcb_mpw1_dc_b(g8t_mpw1_b),
+               .lcb_mpw2_dc_b(g8t_mpw2_b),
+               .lcb_delay_lclkr_dc(g8t_delay_lclkr),
+               .ccflush_dc(tc_ac_ccflush_dc),
+               .scan_dis_dc_b(tc_ac_scan_dis_dc_b),
+               .scan_diag_dc(scan_diag_dc),
+               .func_scan_in(siv[array_offset]),
+               .func_scan_out(sov[array_offset]),
+
+               .lcb_sg_0(pc_iu_sg_0),
+               .lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
+               .lcb_time_sl_thold_0(pc_iu_time_sl_thold_0),
+               .lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0),
+               .lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0),
+               .lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0),
+               .time_scan_in(time_scan_in),
+               .time_scan_out(time_scan_out),
+               .abst_scan_in(abst_scan_in),
+               .abst_scan_out(abst_scan_out),
+               .repr_scan_in(repr_scan_in),
+               .repr_scan_out(repr_scan_out),
+
+               .abist_di(pc_iu_abist_di_0),
+               .abist_bw_odd(pc_iu_abist_g8t_bw_1),
+               .abist_bw_even(pc_iu_abist_g8t_bw_0),
+               .abist_wr_adr(pc_iu_abist_waddr_0),
+               .wr_abst_act(pc_iu_abist_g8t_wenb),
+               .abist_rd0_adr(pc_iu_abist_raddr_0),
+               .rd0_abst_act(pc_iu_abist_g8t1p_renb_0),
+               .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
+               .abist_ena_1(pc_iu_abist_ena_dc),
+               .abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena),
+               .abist_raw_dc_b(pc_iu_abist_raw_dc_b),
+               .obs0_abist_cmp(pc_iu_abist_g8t_dcomp),
+
+               .lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0),
+               .pc_bo_enable_2(pc_iu_bo_enable_2),
+               .pc_bo_reset(pc_iu_bo_reset),
+               .pc_bo_unload(pc_iu_bo_unload),
+               .pc_bo_repair(pc_iu_bo_repair),
+               .pc_bo_shdata(pc_iu_bo_shdata),
+               .pc_bo_select(pc_iu_bo_select),
+               .bo_pc_failout(iu_pc_bo_fail),
+               .bo_pc_diagloop(iu_pc_bo_diagout),
+
+               .tri_lcb_mpw1_dc_b(mpw1_b),
+               .tri_lcb_mpw2_dc_b(mpw2_b),
+               .tri_lcb_delay_lclkr_dc(delay_lclkr),
+               .tri_lcb_clkoff_dc_b(clkoff_b),
+               .tri_lcb_act_dis_dc(act_dis),
+
+               .bw(ary_w_sel),
+               .wr_adr(ary_w_addr),
+               .rd_adr(ary_r_addr),
+               .di(ary_w_data),
+               .do(ary_r_data)
+            );
+
+      //-----------------------------------------------
+      // latches
+      //-----------------------------------------------
+
+
+      tri_rlmlatch_p #(.INIT(0)) data_in_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(lat_wi_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[data_in_offset:data_in_offset]),
+         .scout(sov[data_in_offset:data_in_offset]),
+         .din(data_in_d),
+         .dout(data_in_q)
+      );
+
+
+      tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(tiup),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[w_act_offset:w_act_offset + 4 - 1]),
+         .scout(sov[w_act_offset:w_act_offset + 4 - 1]),
+         .din(w_act_d),
+         .dout(w_act_q)
+      );
+
+
+      tri_rlmlatch_p #(.INIT(0)) r_act_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(tiup),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[r_act_offset]),
+         .scout(sov[r_act_offset]),
+         .din(r_act_d),
+         .dout(r_act_q)
+      );
+
+
+      tri_rlmreg_p #(.WIDTH(9), .INIT(0)) w_addr_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(lat_wi_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[w_addr_offset:w_addr_offset + 9 - 1]),
+         .scout(sov[w_addr_offset:w_addr_offset + 9 - 1]),
+         .din(w_addr_d),
+         .dout(w_addr_q)
+      );
+
+
+      tri_rlmreg_p #(.WIDTH(9), .INIT(0)) r_addr_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(lat_ri_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[r_addr_offset:r_addr_offset + 9 - 1]),
+         .scout(sov[r_addr_offset:r_addr_offset + 9 - 1]),
+         .din(r_addr_d),
+         .dout(r_addr_q)
+      );
+
+
+      tri_rlmreg_p #(.WIDTH(4), .INIT(0)) data_out_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(lat_ro_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[data_out_offset:data_out_offset + 4 - 1]),
+         .scout(sov[data_out_offset:data_out_offset + 4 - 1]),
+         .din(data_out_d),
+         .dout(data_out_q)
+      );
+
+      tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .act(reset_act),
+         .thold_b(pc_iu_func_sl_thold_0_b),
+         .sg(pc_iu_sg_0),
+         .force_t(force_t),
+         .delay_lclkr(delay_lclkr),
+         .mpw1_b(mpw1_b),
+         .mpw2_b(mpw2_b),
+         .d_mode(d_mode),
+         .scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
+         .scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
+         .din(reset_w_addr_d),
+         .dout(reset_w_addr_q)
+      );
+
+      //-----------------------------------------------
+      // pervasive
+      //-----------------------------------------------
+
+
+      tri_plat #(.WIDTH(7)) perv_2to1_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .flush(tc_ac_ccflush_dc),
+         .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}),
+         .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1})
+      );
+
+
+      tri_plat #(.WIDTH(7)) perv_1to0_reg(
+         .vd(vdd),
+         .gd(gnd),
+         .nclk(nclk),
+         .flush(tc_ac_ccflush_dc),
+         .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}),
+         .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0})
+      );
+
+
+      tri_lcbor  perv_lcbor(
+         .clkoff_b(clkoff_b),
+         .thold(pc_iu_func_sl_thold_0),
+         .sg(pc_iu_sg_0),
+         .act_dis(act_dis),
+         .force_t(force_t),
+         .thold_b(pc_iu_func_sl_thold_0_b)
+      );
+
+      //-----------------------------------------------
+      // scan
+      //-----------------------------------------------
+
+      assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]};
+      assign func_scan_out = sov[scan_right];
+
+
+endmodule

rel/src/verilog/trilib/tri_bthmx.v

@@ -0,0 +1,64 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+//  Description:  XU Multiplier Top
+//
+//*****************************************************************************
+module tri_bthmx(x, sneg, sx, sx2, right, left, q, vd, gd);
+
+input          x;
+input          sneg;
+input          sx;
+input          sx2;
+input          right;
+output         left;
+output         q;
+(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
+(* ANALYSIS_NOT_REFERENCED="TRUE" *)
+inout          vd;
+(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
+(* ANALYSIS_NOT_REFERENCED="TRUE" *)
+inout          gd;
+
+
+
+wire center, xn, spos;
+
+assign xn      = ~x;
+assign spos    = ~sneg;
+
+assign center  = ~(( xn & spos ) |
+                   ( x  & sneg ));
+
+assign left    = center; // output
+
+
+assign q       = ( center &  sx  ) |
+                 ( right  &  sx2 ) ;
+
+endmodule

rel/src/verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v

@@ -0,0 +1,471 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+//********************************************************************
+//*
+//* TITLE: I-ERAT CAM Match Line Logic for Functional Model
+//*
+//* NAME: tri_cam_16x143_1r1w1c_matchline
+//*
+//*********************************************************************
+
+module tri_cam_16x143_1r1w1c_matchline(
+   addr_in,
+   addr_enable,
+   comp_pgsize,
+   pgsize_enable,
+   entry_size,
+   entry_cmpmask,
+   entry_xbit,
+   entry_xbitmask,
+   entry_epn,
+   comp_class,
+   entry_class,
+   class_enable,
+   comp_extclass,
+   entry_extclass,
+   extclass_enable,
+   comp_state,
+   entry_hv,
+   entry_ds,
+   state_enable,
+   entry_thdid,
+   comp_thdid,
+   thdid_enable,
+   entry_pid,
+   comp_pid,
+   pid_enable,
+   entry_v,
+   comp_invalidate,
+   match
+);
+   parameter                 HAVE_XBIT = 1;
+   parameter                 NUM_PGSIZES = 5;
+   parameter                 HAVE_CMPMASK = 1;
+   parameter                 CMPMASK_WIDTH = 4;
+
+   // @{default:nclk}@
+   input [0:51]              addr_in;
+   input [0:1]               addr_enable;
+   input [0:2]               comp_pgsize;
+   input                     pgsize_enable;
+   input [0:2]               entry_size;
+   input [0:CMPMASK_WIDTH-1] entry_cmpmask;
+   input                     entry_xbit;
+   input [0:CMPMASK_WIDTH-1] entry_xbitmask;
+   input [0:51]              entry_epn;
+   input [0:1]               comp_class;
+   input [0:1]               entry_class;
+   input [0:2]               class_enable;
+   input [0:1]               comp_extclass;
+   input [0:1]               entry_extclass;
+   input [0:1]               extclass_enable;
+   input [0:1]               comp_state;
+   input                     entry_hv;
+   input                     entry_ds;
+   input [0:1]               state_enable;
+   input [0:3]               entry_thdid;
+   input [0:3]               comp_thdid;
+   input [0:1]               thdid_enable;
+   input [0:7]               entry_pid;
+   input [0:7]               comp_pid;
+   input                     pid_enable;
+   input                     entry_v;
+   input                     comp_invalidate;
+
+   output                    match;
+
+   // tri_cam_16x143_1r1w1c_matchline
+
+   //----------------------------------------------------------------------
+   // Signals
+   //----------------------------------------------------------------------
+
+   wire [34:51]              entry_epn_b;
+   wire                      function_50_51;
+   wire                      function_48_51;
+   wire                      function_46_51;
+   wire                      function_44_51;
+   wire                      function_40_51;
+   wire                      function_36_51;
+   wire                      function_34_51;
+   wire                      pgsize_eq_16K;
+   wire                      pgsize_eq_64K;
+   wire                      pgsize_eq_256K;
+   wire                      pgsize_eq_1M;
+   wire                      pgsize_eq_16M;
+   wire                      pgsize_eq_256M;
+   wire                      pgsize_eq_1G;
+   wire                      pgsize_gte_16K;
+   wire                      pgsize_gte_64K;
+   wire                      pgsize_gte_256K;
+   wire                      pgsize_gte_1M;
+   wire                      pgsize_gte_16M;
+   wire                      pgsize_gte_256M;
+   wire                      pgsize_gte_1G;
+   wire                      comp_or_34_35;
+   wire                      comp_or_34_39;
+   wire                      comp_or_36_39;
+   wire                      comp_or_40_43;
+   wire                      comp_or_44_45;
+   wire                      comp_or_44_47;
+   wire                      comp_or_46_47;
+   wire                      comp_or_48_49;
+   wire                      comp_or_48_51;
+   wire                      comp_or_50_51;
+   wire [0:72]               match_line;
+   wire                      pgsize_match;
+   wire                      addr_match;
+   wire                      class_match;
+   wire                      extclass_match;
+   wire                      state_match;
+   wire                      thdid_match;
+   wire                      pid_match;
+    (* analysis_not_referenced="true" *)
+   wire [0:2]                unused;
+
+   assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^
+                                {addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]}));
+
+   generate
+   begin
+     if (NUM_PGSIZES == 8)
+     begin : numpgsz8
+       // tie off unused signals
+       assign comp_or_34_39 = 1'b0;
+       assign comp_or_44_47 = 1'b0;
+       assign comp_or_48_51 = 1'b0;
+       assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51};
+
+       assign entry_epn_b[34:51] = (~(entry_epn[34:51]));
+
+       if (HAVE_CMPMASK == 0)
+       begin
+         assign pgsize_eq_1G   = (   entry_size[0]   &    entry_size[1]   &    entry_size[2]);
+         assign pgsize_eq_256M = (   entry_size[0]   &    entry_size[1]   & (~(entry_size[2])));
+         assign pgsize_eq_16M  = (   entry_size[0]   & (~(entry_size[1])) &    entry_size[2]);
+         assign pgsize_eq_1M   = (   entry_size[0]   & (~(entry_size[1])) & (~(entry_size[2])));
+         assign pgsize_eq_256K = ((~(entry_size[0])) &    entry_size[1]   &    entry_size[2]);
+         assign pgsize_eq_64K  = ((~(entry_size[0])) &    entry_size[1]   & (~(entry_size[2])));
+         assign pgsize_eq_16K  = ((~(entry_size[0])) & (~(entry_size[1])) &    entry_size[2]);
+
+         assign pgsize_gte_1G   = (   entry_size[0]   &    entry_size[1]   &    entry_size[2]);
+         assign pgsize_gte_256M = (   entry_size[0]   &    entry_size[1]   & (~(entry_size[2]))) | pgsize_gte_1G;
+         assign pgsize_gte_16M  = (   entry_size[0]   & (~(entry_size[1])) &    entry_size[2])   | pgsize_gte_256M;
+         assign pgsize_gte_1M   = (   entry_size[0]   & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M;
+         assign pgsize_gte_256K = ((~(entry_size[0])) &    entry_size[1]   &    entry_size[2])   | pgsize_gte_1M;
+         assign pgsize_gte_64K  = ((~(entry_size[0])) &    entry_size[1]   & (~(entry_size[2]))) | pgsize_gte_256K;
+         assign pgsize_gte_16K  = ((~(entry_size[0])) & (~(entry_size[1])) &    entry_size[2])   | pgsize_gte_64K;
+
+         assign unused[1] = |{entry_cmpmask, entry_xbitmask};
+       end
+
+       if (HAVE_CMPMASK == 1)
+       begin
+         //  size           entry_cmpmask: 0123456
+         //    1GB                         0000000
+         //  256MB                         1000000
+         //   16MB                         1100000
+         //    1MB                         1110000
+         //  256KB                         1111000
+         //   64KB                         1111100
+         //   16KB                         1111110
+         //    4KB                         1111111
+         assign pgsize_gte_1G   = (~entry_cmpmask[0]);
+         assign pgsize_gte_256M = (~entry_cmpmask[1]);
+         assign pgsize_gte_16M  = (~entry_cmpmask[2]);
+         assign pgsize_gte_1M   = (~entry_cmpmask[3]);
+         assign pgsize_gte_256K = (~entry_cmpmask[4]);
+         assign pgsize_gte_64K  = (~entry_cmpmask[5]);
+         assign pgsize_gte_16K  = (~entry_cmpmask[6]);
+
+         //  size          entry_xbitmask: 0123456
+         //    1GB                         1000000
+         //  256MB                         0100000
+         //   16MB                         0010000
+         //    1MB                         0001000
+         //  256KB                         0000100
+         //   64KB                         0000010
+         //   16KB                         0000001
+         //    4KB                         0000000
+         assign pgsize_eq_1G   = entry_xbitmask[0];
+         assign pgsize_eq_256M = entry_xbitmask[1];
+         assign pgsize_eq_16M  = entry_xbitmask[2];
+         assign pgsize_eq_1M   = entry_xbitmask[3];
+         assign pgsize_eq_256K = entry_xbitmask[4];
+         assign pgsize_eq_64K  = entry_xbitmask[5];
+         assign pgsize_eq_16K  = entry_xbitmask[6];
+
+         assign unused[1] = 1'b0;
+       end
+
+       if (HAVE_XBIT == 0)
+       begin
+         assign function_34_51 = 1'b0;
+         assign function_36_51 = 1'b0;
+         assign function_40_51 = 1'b0;
+         assign function_44_51 = 1'b0;
+         assign function_46_51 = 1'b0;
+         assign function_48_51 = 1'b0;
+         assign function_50_51 = 1'b0;
+	 assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51,
+                              function_46_51, function_48_51, function_50_51, entry_xbit,
+                              entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M,
+                              pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K};
+       end
+
+       if (HAVE_XBIT != 0)
+       begin
+         assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G))   | (|(entry_epn_b[34:51] & addr_in[34:51]));
+         assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51]));
+         assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M))  | (|(entry_epn_b[40:51] & addr_in[40:51]));
+         assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M))   | (|(entry_epn_b[44:51] & addr_in[44:51]));
+         assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51]));
+         assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K))  | (|(entry_epn_b[48:51] & addr_in[48:51]));
+         assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K))  | (|(entry_epn_b[50:51] & addr_in[50:51]));
+         assign unused[2] = 1'b0;
+       end
+
+       assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K;
+       assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K;
+       assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K;
+       assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M;
+       assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
+       assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M;
+       assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G;
+
+       if (HAVE_XBIT == 0)
+       begin
+         assign addr_match = (comp_or_34_35 &		//  Ignore functions based on page size
+                              comp_or_36_39 &
+                              comp_or_40_43 &
+                              comp_or_44_45 &
+                              comp_or_46_47 &
+                              comp_or_48_49 &
+                              comp_or_50_51 &
+                              (&(match_line[31:33])) &		//  Regular compare largest page size
+                              ((&(match_line[0:30])) | (~(addr_enable[1])))) |         // ignored part of epn
+                            (~(addr_enable[0]));       //  Include address as part of compare,
+                                                       //  should never ignore for regular compare/read.
+                                                       //  Could ignore for compare/invalidate
+       end
+
+       if (HAVE_XBIT != 0)
+       begin
+         assign addr_match = (function_50_51 &		//  Exclusion functions
+                              function_48_51 &
+                              function_46_51 &
+                              function_44_51 &
+                              function_40_51 &
+                              function_36_51 &
+                              function_34_51 &
+                              comp_or_34_35 &		//  Ignore functions based on page size
+                              comp_or_36_39 &
+                              comp_or_40_43 &
+                              comp_or_44_45 &
+                              comp_or_46_47 &
+                              comp_or_48_49 &
+                              comp_or_50_51 &
+                              (&(match_line[31:33])) &         //  Regular compare largest page size
+                              (&(match_line[0:30]) | (~(addr_enable[1])))) |         // ignored part of epn
+                            (~(addr_enable[0]));           //  Include address as part of compare,
+                                                           //  should never ignore for regular compare/read.
+                                                           //  Could ignore for compare/invalidate
+       end
+     end  // numpgsz8: NUM_PGSIZES = 8
+
+
+     if (NUM_PGSIZES == 5)
+     begin : numpgsz5
+       // tie off unused signals
+       assign function_50_51 = 1'b0;
+       assign function_46_51 = 1'b0;
+       assign function_36_51 = 1'b0;
+       assign pgsize_eq_16K = 1'b0;
+       assign pgsize_eq_256K = 1'b0;
+       assign pgsize_eq_256M = 1'b0;
+       assign pgsize_gte_16K = 1'b0;
+       assign pgsize_gte_256K = 1'b0;
+       assign pgsize_gte_256M = 1'b0;
+       assign comp_or_34_35 = 1'b0;
+       assign comp_or_36_39 = 1'b0;
+       assign comp_or_44_45 = 1'b0;
+       assign comp_or_46_47 = 1'b0;
+       assign comp_or_48_49 = 1'b0;
+       assign comp_or_50_51 = 1'b0;
+       assign unused[0] = |{function_50_51, function_46_51, function_36_51,
+                            pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M,
+                            pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M,
+                            comp_or_34_35, comp_or_36_39, comp_or_44_45,
+                            comp_or_46_47, comp_or_48_49, comp_or_50_51};
+
+       assign entry_epn_b[34:51] = (~(entry_epn[34:51]));
+
+       if (HAVE_CMPMASK == 0)
+       begin
+         // 110
+         assign pgsize_eq_1G  = (   entry_size[0]   &    entry_size[1]   & (~(entry_size[2])));
+         // 111
+         assign pgsize_eq_16M = (   entry_size[0]   &    entry_size[1]   &    entry_size[2]);
+         // 101
+         assign pgsize_eq_1M  = (   entry_size[0]   & (~(entry_size[1])) &    entry_size[2]);
+         // 011
+         assign pgsize_eq_64K = ((~(entry_size[0])) &    entry_size[1]   &    entry_size[2]);
+
+         assign pgsize_gte_1G  = (   entry_size[0]   &    entry_size[1]   & (~(entry_size[2])));
+         assign pgsize_gte_16M = (   entry_size[0]   &    entry_size[1]   & entry_size[2]) | pgsize_gte_1G;
+         assign pgsize_gte_1M  = (   entry_size[0]   & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M;
+         assign pgsize_gte_64K = ((~(entry_size[0])) &    entry_size[1]   & entry_size[2]) | pgsize_gte_1M;
+
+         assign unused[1] = |{entry_cmpmask, entry_xbitmask};
+       end
+
+       if (HAVE_CMPMASK == 1)
+       begin
+         //  size           entry_cmpmask: 0123
+         //    1GB                         0000
+         //   16MB                         1000
+         //    1MB                         1100
+         //   64KB                         1110
+         //    4KB                         1111
+         assign pgsize_gte_1G  = (~entry_cmpmask[0]);
+         assign pgsize_gte_16M = (~entry_cmpmask[1]);
+         assign pgsize_gte_1M  = (~entry_cmpmask[2]);
+         assign pgsize_gte_64K = (~entry_cmpmask[3]);
+
+         //  size          entry_xbitmask: 0123
+         //    1GB                         1000
+         //   16MB                         0100
+         //    1MB                         0010
+         //   64KB                         0001
+         //    4KB                         0000
+         assign pgsize_eq_1G  = entry_xbitmask[0];
+         assign pgsize_eq_16M = entry_xbitmask[1];
+         assign pgsize_eq_1M  = entry_xbitmask[2];
+         assign pgsize_eq_64K = entry_xbitmask[3];
+
+         assign unused[1] = 1'b0;
+       end
+
+       if (HAVE_XBIT == 0)
+       begin
+         assign function_34_51 = 1'b0;
+         assign function_40_51 = 1'b0;
+         assign function_44_51 = 1'b0;
+         assign function_48_51 = 1'b0;
+	 assign unused[2] = |{function_34_51, function_40_51, function_44_51,
+                              function_48_51, entry_xbit, entry_epn_b,
+                              pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K};
+       end
+
+       if (HAVE_XBIT != 0)
+       begin
+         // 1G
+         assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G))  | (|(entry_epn_b[34:51] & addr_in[34:51]));
+         // 16M
+         assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
+         // 1M
+         assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M))  | (|(entry_epn_b[44:51] & addr_in[44:51]));
+         // 64K
+         assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
+         assign unused[2] = 1'b0;
+       end
+
+       assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K;
+       assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M;
+       assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
+       assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G;
+
+       if (HAVE_XBIT == 0)
+       begin
+         assign addr_match = (comp_or_34_39 &		//  Ignore functions based on page size
+                              comp_or_40_43 &
+                              comp_or_44_47 &
+                              comp_or_48_51 &
+                              (&(match_line[31:33])) &		//  Regular compare largest page size
+                              ((&(match_line[0:30])) | (~(addr_enable[1])))) |         // ignored part of epn
+                            (~(addr_enable[0]));       //  Include address as part of compare,
+                                                       //  should never ignore for regular compare/read.
+                                                       //  Could ignore for compare/invalidate
+       end
+
+       if (HAVE_XBIT != 0)
+       begin
+         assign addr_match = (function_48_51 &
+                              function_44_51 &
+                              function_40_51 &
+                              function_34_51 &
+                              comp_or_34_39 &		//  Ignore functions based on page size
+                              comp_or_40_43 &
+                              comp_or_44_47 &
+                              comp_or_48_51 &
+                              (&(match_line[31:33])) &         //  Regular compare largest page size
+                              ((&(match_line[0:30])) | (~(addr_enable[1])))) |         // ignored part of epn
+                            (~(addr_enable[0]));             //  Include address as part of compare,
+                                                             //  should never ignore for regular compare/read.
+                                                             //  Could ignore for compare/invalidate
+       end
+     end // numpgsz5: NUM_PGSIZES = 5
+
+
+     assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable));
+
+     assign class_match = (match_line[55] | (~(class_enable[0]))) &
+                          (match_line[56] | (~(class_enable[1]))) &
+                          ((&(match_line[55:56])) | (~(class_enable[2])) |
+                           ((~(entry_extclass[1])) & (~comp_invalidate)));		// pid_nz bit
+
+     assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) &               // iprot bit
+                             (match_line[58] | (~(extclass_enable[1])));		// pid_nz bit
+
+     assign state_match = (match_line[59] | (~(state_enable[0]))) &
+                          (match_line[60] | (~(state_enable[1])));
+
+     assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) &
+                          (&(match_line[69:72]) | (~(thdid_enable[1])) |
+                           ((~(entry_extclass[1])) & (~comp_invalidate)));		// pid_nz bit
+
+     assign pid_match = (&(match_line[61:68])) |
+                        // entry_pid=0 ignores pid match for compares,
+                        //  but not for invalidates.
+                        ((~(entry_extclass[1])) & (~comp_invalidate)) |		// pid_nz bit
+                        (~(pid_enable));
+
+     assign match = addr_match &        //  Address compare
+                    pgsize_match &      //  Size compare
+                    class_match &       //  Class compare
+                    extclass_match &    //  ExtClass compare
+                    state_match &       //  State compare
+                    thdid_match &       //  ThdID compare
+                    pid_match &         //  PID compare
+                    entry_v;            //  Valid
+   end
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v

@@ -0,0 +1,471 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+//********************************************************************
+//*
+//* TITLE: D-ERAT CAM Match Line Logic for Functional Model
+//*
+//* NAME: tri_cam_32x143_1r1w1c_matchline
+//*
+//*********************************************************************
+
+module tri_cam_32x143_1r1w1c_matchline(
+   addr_in,
+   addr_enable,
+   comp_pgsize,
+   pgsize_enable,
+   entry_size,
+   entry_cmpmask,
+   entry_xbit,
+   entry_xbitmask,
+   entry_epn,
+   comp_class,
+   entry_class,
+   class_enable,
+   comp_extclass,
+   entry_extclass,
+   extclass_enable,
+   comp_state,
+   entry_hv,
+   entry_ds,
+   state_enable,
+   entry_thdid,
+   comp_thdid,
+   thdid_enable,
+   entry_pid,
+   comp_pid,
+   pid_enable,
+   entry_v,
+   comp_invalidate,
+   match
+);
+   parameter                 HAVE_XBIT = 1;
+   parameter                 NUM_PGSIZES = 5;
+   parameter                 HAVE_CMPMASK = 1;
+   parameter                 CMPMASK_WIDTH = 4;
+
+   // @{default:nclk}@
+   input [0:51]              addr_in;
+   input [0:1]               addr_enable;
+   input [0:2]               comp_pgsize;
+   input                     pgsize_enable;
+   input [0:2]               entry_size;
+   input [0:CMPMASK_WIDTH-1] entry_cmpmask;
+   input                     entry_xbit;
+   input [0:CMPMASK_WIDTH-1] entry_xbitmask;
+   input [0:51]              entry_epn;
+   input [0:1]               comp_class;
+   input [0:1]               entry_class;
+   input [0:2]               class_enable;
+   input [0:1]               comp_extclass;
+   input [0:1]               entry_extclass;
+   input [0:1]               extclass_enable;
+   input [0:1]               comp_state;
+   input                     entry_hv;
+   input                     entry_ds;
+   input [0:1]               state_enable;
+   input [0:3]               entry_thdid;
+   input [0:3]               comp_thdid;
+   input [0:1]               thdid_enable;
+   input [0:7]               entry_pid;
+   input [0:7]               comp_pid;
+   input                     pid_enable;
+   input                     entry_v;
+   input                     comp_invalidate;
+
+   output                    match;
+
+   // tri_cam_32x143_1r1w1c_matchline
+
+   //----------------------------------------------------------------------
+   // Signals
+   //----------------------------------------------------------------------
+
+   wire [34:51]              entry_epn_b;
+   wire                      function_50_51;
+   wire                      function_48_51;
+   wire                      function_46_51;
+   wire                      function_44_51;
+   wire                      function_40_51;
+   wire                      function_36_51;
+   wire                      function_34_51;
+   wire                      pgsize_eq_16K;
+   wire                      pgsize_eq_64K;
+   wire                      pgsize_eq_256K;
+   wire                      pgsize_eq_1M;
+   wire                      pgsize_eq_16M;
+   wire                      pgsize_eq_256M;
+   wire                      pgsize_eq_1G;
+   wire                      pgsize_gte_16K;
+   wire                      pgsize_gte_64K;
+   wire                      pgsize_gte_256K;
+   wire                      pgsize_gte_1M;
+   wire                      pgsize_gte_16M;
+   wire                      pgsize_gte_256M;
+   wire                      pgsize_gte_1G;
+   wire                      comp_or_34_35;
+   wire                      comp_or_34_39;
+   wire                      comp_or_36_39;
+   wire                      comp_or_40_43;
+   wire                      comp_or_44_45;
+   wire                      comp_or_44_47;
+   wire                      comp_or_46_47;
+   wire                      comp_or_48_49;
+   wire                      comp_or_48_51;
+   wire                      comp_or_50_51;
+   wire [0:72]               match_line;
+   wire                      pgsize_match;
+   wire                      addr_match;
+   wire                      class_match;
+   wire                      extclass_match;
+   wire                      state_match;
+   wire                      thdid_match;
+   wire                      pid_match;
+    (* analysis_not_referenced="true" *)
+   wire [0:2]                unused;
+
+   assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^
+                                {addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]}));
+
+   generate
+   begin
+     if (NUM_PGSIZES == 8)
+     begin : numpgsz8
+       // tie off unused signals
+       assign comp_or_34_39 = 1'b0;
+       assign comp_or_44_47 = 1'b0;
+       assign comp_or_48_51 = 1'b0;
+       assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51};
+
+       assign entry_epn_b[34:51] = (~(entry_epn[34:51]));
+
+       if (HAVE_CMPMASK == 0)
+       begin
+         assign pgsize_eq_1G   = (   entry_size[0]   &    entry_size[1]   &    entry_size[2]);
+         assign pgsize_eq_256M = (   entry_size[0]   &    entry_size[1]   & (~(entry_size[2])));
+         assign pgsize_eq_16M  = (   entry_size[0]   & (~(entry_size[1])) &    entry_size[2]);
+         assign pgsize_eq_1M   = (   entry_size[0]   & (~(entry_size[1])) & (~(entry_size[2])));
+         assign pgsize_eq_256K = ((~(entry_size[0])) &    entry_size[1]   &    entry_size[2]);
+         assign pgsize_eq_64K  = ((~(entry_size[0])) &    entry_size[1]   & (~(entry_size[2])));
+         assign pgsize_eq_16K  = ((~(entry_size[0])) & (~(entry_size[1])) &    entry_size[2]);
+
+         assign pgsize_gte_1G   = (   entry_size[0]   &    entry_size[1]   &    entry_size[2]);
+         assign pgsize_gte_256M = (   entry_size[0]   &    entry_size[1]   & (~(entry_size[2]))) | pgsize_gte_1G;
+         assign pgsize_gte_16M  = (   entry_size[0]   & (~(entry_size[1])) &    entry_size[2])   | pgsize_gte_256M;
+         assign pgsize_gte_1M   = (   entry_size[0]   & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M;
+         assign pgsize_gte_256K = ((~(entry_size[0])) &    entry_size[1]   &    entry_size[2])   | pgsize_gte_1M;
+         assign pgsize_gte_64K  = ((~(entry_size[0])) &    entry_size[1]   & (~(entry_size[2]))) | pgsize_gte_256K;
+         assign pgsize_gte_16K  = ((~(entry_size[0])) & (~(entry_size[1])) &    entry_size[2])   | pgsize_gte_64K;
+
+         assign unused[1] = |{entry_cmpmask, entry_xbitmask};
+       end
+
+       if (HAVE_CMPMASK == 1)
+       begin
+         //  size           entry_cmpmask: 0123456
+         //    1GB                         0000000
+         //  256MB                         1000000
+         //   16MB                         1100000
+         //    1MB                         1110000
+         //  256KB                         1111000
+         //   64KB                         1111100
+         //   16KB                         1111110
+         //    4KB                         1111111
+         assign pgsize_gte_1G   = (~entry_cmpmask[0]);
+         assign pgsize_gte_256M = (~entry_cmpmask[1]);
+         assign pgsize_gte_16M  = (~entry_cmpmask[2]);
+         assign pgsize_gte_1M   = (~entry_cmpmask[3]);
+         assign pgsize_gte_256K = (~entry_cmpmask[4]);
+         assign pgsize_gte_64K  = (~entry_cmpmask[5]);
+         assign pgsize_gte_16K  = (~entry_cmpmask[6]);
+
+         //  size          entry_xbitmask: 0123456
+         //    1GB                         1000000
+         //  256MB                         0100000
+         //   16MB                         0010000
+         //    1MB                         0001000
+         //  256KB                         0000100
+         //   64KB                         0000010
+         //   16KB                         0000001
+         //    4KB                         0000000
+         assign pgsize_eq_1G   = entry_xbitmask[0];
+         assign pgsize_eq_256M = entry_xbitmask[1];
+         assign pgsize_eq_16M  = entry_xbitmask[2];
+         assign pgsize_eq_1M   = entry_xbitmask[3];
+         assign pgsize_eq_256K = entry_xbitmask[4];
+         assign pgsize_eq_64K  = entry_xbitmask[5];
+         assign pgsize_eq_16K  = entry_xbitmask[6];
+
+         assign unused[1] = 1'b0;
+       end
+
+       if (HAVE_XBIT == 0)
+       begin
+         assign function_34_51 = 1'b0;
+         assign function_36_51 = 1'b0;
+         assign function_40_51 = 1'b0;
+         assign function_44_51 = 1'b0;
+         assign function_46_51 = 1'b0;
+         assign function_48_51 = 1'b0;
+         assign function_50_51 = 1'b0;
+	 assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51,
+                              function_46_51, function_48_51, function_50_51, entry_xbit,
+                              entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M,
+                              pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K};
+       end
+
+       if (HAVE_XBIT != 0)
+       begin
+         assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G))   | (|(entry_epn_b[34:51] & addr_in[34:51]));
+         assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51]));
+         assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M))  | (|(entry_epn_b[40:51] & addr_in[40:51]));
+         assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M))   | (|(entry_epn_b[44:51] & addr_in[44:51]));
+         assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51]));
+         assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K))  | (|(entry_epn_b[48:51] & addr_in[48:51]));
+         assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K))  | (|(entry_epn_b[50:51] & addr_in[50:51]));
+         assign unused[2] = 1'b0;
+       end
+
+       assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K;
+       assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K;
+       assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K;
+       assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M;
+       assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
+       assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M;
+       assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G;
+
+       if (HAVE_XBIT == 0)
+       begin
+         assign addr_match = (comp_or_34_35 &		//  Ignore functions based on page size
+                              comp_or_36_39 &
+                              comp_or_40_43 &
+                              comp_or_44_45 &
+                              comp_or_46_47 &
+                              comp_or_48_49 &
+                              comp_or_50_51 &
+                              (&(match_line[31:33])) &		//  Regular compare largest page size
+                              ((&(match_line[0:30])) | (~(addr_enable[1])))) |         // ignored part of epn
+                            (~(addr_enable[0]));       //  Include address as part of compare,
+                                                       //  should never ignore for regular compare/read.
+                                                       //  Could ignore for compare/invalidate
+       end
+
+       if (HAVE_XBIT != 0)
+       begin
+         assign addr_match = (function_50_51 &		//  Exclusion functions
+                              function_48_51 &
+                              function_46_51 &
+                              function_44_51 &
+                              function_40_51 &
+                              function_36_51 &
+                              function_34_51 &
+                              comp_or_34_35 &		//  Ignore functions based on page size
+                              comp_or_36_39 &
+                              comp_or_40_43 &
+                              comp_or_44_45 &
+                              comp_or_46_47 &
+                              comp_or_48_49 &
+                              comp_or_50_51 &
+                              (&(match_line[31:33])) &         //  Regular compare largest page size
+                              (&(match_line[0:30]) | (~(addr_enable[1])))) |         // ignored part of epn
+                            (~(addr_enable[0]));           //  Include address as part of compare,
+                                                           //  should never ignore for regular compare/read.
+                                                           //  Could ignore for compare/invalidate
+       end
+     end  // numpgsz8: NUM_PGSIZES = 8
+
+
+     if (NUM_PGSIZES == 5)
+     begin : numpgsz5
+       // tie off unused signals
+       assign function_50_51 = 1'b0;
+       assign function_46_51 = 1'b0;
+       assign function_36_51 = 1'b0;
+       assign pgsize_eq_16K = 1'b0;
+       assign pgsize_eq_256K = 1'b0;
+       assign pgsize_eq_256M = 1'b0;
+       assign pgsize_gte_16K = 1'b0;
+       assign pgsize_gte_256K = 1'b0;
+       assign pgsize_gte_256M = 1'b0;
+       assign comp_or_34_35 = 1'b0;
+       assign comp_or_36_39 = 1'b0;
+       assign comp_or_44_45 = 1'b0;
+       assign comp_or_46_47 = 1'b0;
+       assign comp_or_48_49 = 1'b0;
+       assign comp_or_50_51 = 1'b0;
+       assign unused[0] = |{function_50_51, function_46_51, function_36_51,
+                            pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M,
+                            pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M,
+                            comp_or_34_35, comp_or_36_39, comp_or_44_45,
+                            comp_or_46_47, comp_or_48_49, comp_or_50_51};
+
+       assign entry_epn_b[34:51] = (~(entry_epn[34:51]));
+
+       if (HAVE_CMPMASK == 0)
+       begin
+         // 110
+         assign pgsize_eq_1G  = (   entry_size[0]   &    entry_size[1]   & (~(entry_size[2])));
+         // 111
+         assign pgsize_eq_16M = (   entry_size[0]   &    entry_size[1]   &    entry_size[2]);
+         // 101
+         assign pgsize_eq_1M  = (   entry_size[0]   & (~(entry_size[1])) &    entry_size[2]);
+         // 011
+         assign pgsize_eq_64K = ((~(entry_size[0])) &    entry_size[1]   &    entry_size[2]);
+
+         assign pgsize_gte_1G  = (   entry_size[0]   &    entry_size[1]   & (~(entry_size[2])));
+         assign pgsize_gte_16M = (   entry_size[0]   &    entry_size[1]   & entry_size[2]) | pgsize_gte_1G;
+         assign pgsize_gte_1M  = (   entry_size[0]   & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M;
+         assign pgsize_gte_64K = ((~(entry_size[0])) &    entry_size[1]   & entry_size[2]) | pgsize_gte_1M;
+
+         assign unused[1] = |{entry_cmpmask, entry_xbitmask};
+       end
+
+       if (HAVE_CMPMASK == 1)
+       begin
+         //  size           entry_cmpmask: 0123
+         //    1GB                         0000
+         //   16MB                         1000
+         //    1MB                         1100
+         //   64KB                         1110
+         //    4KB                         1111
+         assign pgsize_gte_1G  = (~entry_cmpmask[0]);
+         assign pgsize_gte_16M = (~entry_cmpmask[1]);
+         assign pgsize_gte_1M  = (~entry_cmpmask[2]);
+         assign pgsize_gte_64K = (~entry_cmpmask[3]);
+
+         //  size          entry_xbitmask: 0123
+         //    1GB                         1000
+         //   16MB                         0100
+         //    1MB                         0010
+         //   64KB                         0001
+         //    4KB                         0000
+         assign pgsize_eq_1G  = entry_xbitmask[0];
+         assign pgsize_eq_16M = entry_xbitmask[1];
+         assign pgsize_eq_1M  = entry_xbitmask[2];
+         assign pgsize_eq_64K = entry_xbitmask[3];
+
+         assign unused[1] = 1'b0;
+       end
+
+       if (HAVE_XBIT == 0)
+       begin
+         assign function_34_51 = 1'b0;
+         assign function_40_51 = 1'b0;
+         assign function_44_51 = 1'b0;
+         assign function_48_51 = 1'b0;
+	 assign unused[2] = |{function_34_51, function_40_51, function_44_51,
+                              function_48_51, entry_xbit, entry_epn_b,
+                              pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K};
+       end
+
+       if (HAVE_XBIT != 0)
+       begin
+         // 1G
+         assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G))  | (|(entry_epn_b[34:51] & addr_in[34:51]));
+         // 16M
+         assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
+         // 1M
+         assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M))  | (|(entry_epn_b[44:51] & addr_in[44:51]));
+         // 64K
+         assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
+         assign unused[2] = 1'b0;
+       end
+
+       assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K;
+       assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M;
+       assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
+       assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G;
+
+       if (HAVE_XBIT == 0)
+       begin
+         assign addr_match = (comp_or_34_39 &		//  Ignore functions based on page size
+                              comp_or_40_43 &
+                              comp_or_44_47 &
+                              comp_or_48_51 &
+                              (&(match_line[31:33])) &		//  Regular compare largest page size
+                              ((&(match_line[0:30])) | (~(addr_enable[1])))) |         // ignored part of epn
+                            (~(addr_enable[0]));       //  Include address as part of compare,
+                                                       //  should never ignore for regular compare/read.
+                                                       //  Could ignore for compare/invalidate
+       end
+
+       if (HAVE_XBIT != 0)
+       begin
+         assign addr_match = (function_48_51 &
+                              function_44_51 &
+                              function_40_51 &
+                              function_34_51 &
+                              comp_or_34_39 &		//  Ignore functions based on page size
+                              comp_or_40_43 &
+                              comp_or_44_47 &
+                              comp_or_48_51 &
+                              (&(match_line[31:33])) &         //  Regular compare largest page size
+                              ((&(match_line[0:30])) | (~(addr_enable[1])))) |         // ignored part of epn
+                            (~(addr_enable[0]));             //  Include address as part of compare,
+                                                             //  should never ignore for regular compare/read.
+                                                             //  Could ignore for compare/invalidate
+       end
+     end // numpgsz5: NUM_PGSIZES = 5
+
+
+     assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable));
+
+     assign class_match = (match_line[55] | (~(class_enable[0]))) &
+                          (match_line[56] | (~(class_enable[1]))) &
+                          ((&(match_line[55:56])) | (~(class_enable[2])) |
+                           ((~(entry_extclass[1])) & (~comp_invalidate)));		// pid_nz bit
+
+     assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) &               // iprot bit
+                             (match_line[58] | (~(extclass_enable[1])));		// pid_nz bit
+
+     assign state_match = (match_line[59] | (~(state_enable[0]))) &
+                          (match_line[60] | (~(state_enable[1])));
+
+     assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) &
+                          (&(match_line[69:72]) | (~(thdid_enable[1])) |
+                           ((~(entry_extclass[1])) & (~comp_invalidate)));		// pid_nz bit
+
+     assign pid_match = (&(match_line[61:68])) |
+                        // entry_pid=0 ignores pid match for compares,
+                        //  but not for invalidates.
+                        ((~(entry_extclass[1])) & (~comp_invalidate)) |		// pid_nz bit
+                        (~(pid_enable));
+
+     assign match = addr_match &        //  Address compare
+                    pgsize_match &      //  Size compare
+                    class_match &       //  Class compare
+                    extclass_match &    //  ExtClass compare
+                    state_match &       //  State compare
+                    thdid_match &       //  ThdID compare
+                    pid_match &         //  PID compare
+                    entry_v;            //  Valid
+   end
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_csa22.v

@@ -0,0 +1,53 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+//*****************************************************************************
+//  Description:  XU Population Count
+//
+//*****************************************************************************
+
+module tri_csa22(
+   a,
+   b,
+   car,
+   sum
+);
+   input   a;
+   input   b;
+   output  car;
+   output  sum;
+
+   wire    car_b;
+   wire    sum_b;
+
+   assign car_b = (~(a & b));
+   assign sum_b = (~(car_b & (a | b)));      // this is equiv to an xnor
+   assign car = (~car_b);
+   assign sum = (~sum_b);
+
+endmodule

rel/src/verilog/trilib/tri_csa32.v

@@ -0,0 +1,65 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+module tri_csa32(
+   a,
+   b,
+   c,
+   car,
+   sum,
+   vd,
+   gd
+);
+   input   a;
+   input   b;
+   input   c;
+   output  car;
+   output  sum;
+   (* ANALYSIS_NOT_ASSIGNED="TRUE" *)
+   (* ANALYSIS_NOT_REFERENCED="TRUE" *)
+   inout   vd;
+   (* ANALYSIS_NOT_ASSIGNED="TRUE" *)
+   (* ANALYSIS_NOT_REFERENCED="TRUE" *)
+   inout   gd;
+
+   wire    carn1;
+   wire    carn2;
+   wire    carn3;
+
+//   assign sum = a ^ b ^ c;
+   tri_xor3 CSA42_XOR3_1(sum, a, b, c);
+
+//   assign car = (a & b) | (a & c) | (b & c);
+   tri_nand2 CSA42_NAND2_1(carn1, a, b);
+   tri_nand2 CSA42_NAND2_2(carn2, a, c);
+   tri_nand2 CSA42_NAND2_3(carn3, b, c);
+   tri_nand3 CSA42_NAND3_4(car, carn1, carn2, carn3);
+
+
+endmodule

rel/src/verilog/trilib/tri_csa42.v

@@ -0,0 +1,85 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+
+module tri_csa42(
+   a,
+   b,
+   c,
+   d,
+   ki,
+   ko,
+   car,
+   sum,
+   vd,
+   gd
+);
+   input   a;
+   input   b;
+   input   c;
+   input   d;
+   input   ki;
+   output  ko;
+   output  car;
+   output  sum;
+   (* ANALYSIS_NOT_ASSIGNED="TRUE" *)
+   (* ANALYSIS_NOT_REFERENCED="TRUE" *)
+   inout   vd;
+   (* ANALYSIS_NOT_ASSIGNED="TRUE" *)
+   (* ANALYSIS_NOT_REFERENCED="TRUE" *)
+   inout   gd;
+
+   wire    s1;
+
+   wire    carn1;
+   wire    carn2;
+   wire    carn3;
+   wire    kon1;
+   wire    kon2;
+   wire    kon3;
+
+//   assign  s1 = b ^ c ^ d;
+   tri_xor3 CSA42_XOR3_1(s1,b,c,d);
+
+//   assign sum = s1 ^ a ^ ki;
+   tri_xor3 CSA42_XOR3_2(sum,s1,a,ki);
+
+//   assign car = (s1 & a) | (s1 & ki) | (a & ki);
+   tri_nand2 CSA42_NAND2_1(carn1,s1,a);
+   tri_nand2 CSA42_NAND2_2(carn2,s1,ki);
+   tri_nand2 CSA42_NAND2_3(carn3,a,ki);
+   tri_nand3 CSA42_NAND3_4(car,carn1,carn2,carn3);
+
+//   assign ko = (b & c) | (b & d) | (c & d);
+   tri_nand2 CSA42_NAND2_5(kon1,b,c);
+   tri_nand2 CSA42_NAND2_6(kon2,b,d);
+   tri_nand2 CSA42_NAND2_7(kon3,c,d);
+   tri_nand3 CSA42_NAND3_8(ko,kon1,kon2,kon3);
+
+
+endmodule

rel/src/verilog/trilib/tri_debug_mux16.v

@@ -0,0 +1,157 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+//********************************************************************
+//*
+//* TITLE: Debug Mux Component (16:1 Debug Groups; 4:1 Trigger Groups)
+//*
+//* NAME: tri_debug_mux16.vhdl
+//*
+//********************************************************************
+
+module tri_debug_mux16(
+//   vd,
+//   gd,
+   select_bits,
+   dbg_group0,
+   dbg_group1,
+   dbg_group2,
+   dbg_group3,
+   dbg_group4,
+   dbg_group5,
+   dbg_group6,
+   dbg_group7,
+   dbg_group8,
+   dbg_group9,
+   dbg_group10,
+   dbg_group11,
+   dbg_group12,
+   dbg_group13,
+   dbg_group14,
+   dbg_group15,
+   trace_data_in,
+   trace_data_out,
+   // Instruction Trace (HTM) Controls
+   coretrace_ctrls_in,
+   coretrace_ctrls_out
+);
+
+// Include model build parameters
+   parameter              DBG_WIDTH = 32;	// A2o=32; A2i=88
+
+//=====================================================================
+// Port Definitions
+//=====================================================================
+
+   input [0:10]           select_bits;
+   input [0:DBG_WIDTH-1]  dbg_group0;
+   input [0:DBG_WIDTH-1]  dbg_group1;
+   input [0:DBG_WIDTH-1]  dbg_group2;
+   input [0:DBG_WIDTH-1]  dbg_group3;
+   input [0:DBG_WIDTH-1]  dbg_group4;
+   input [0:DBG_WIDTH-1]  dbg_group5;
+   input [0:DBG_WIDTH-1]  dbg_group6;
+   input [0:DBG_WIDTH-1]  dbg_group7;
+   input [0:DBG_WIDTH-1]  dbg_group8;
+   input [0:DBG_WIDTH-1]  dbg_group9;
+   input [0:DBG_WIDTH-1]  dbg_group10;
+   input [0:DBG_WIDTH-1]  dbg_group11;
+   input [0:DBG_WIDTH-1]  dbg_group12;
+   input [0:DBG_WIDTH-1]  dbg_group13;
+   input [0:DBG_WIDTH-1]  dbg_group14;
+   input [0:DBG_WIDTH-1]  dbg_group15;
+   input [0:DBG_WIDTH-1]  trace_data_in;
+   output [0:DBG_WIDTH-1] trace_data_out;
+
+// Instruction Trace (HTM) Control Signals:
+//  0    - ac_an_coretrace_first_valid
+//  1    - ac_an_coretrace_valid
+//  2:3  - ac_an_coretrace_type[0:1]
+   input  [0:3]           coretrace_ctrls_in;
+   output [0:3]           coretrace_ctrls_out;
+
+//=====================================================================
+// Signal Declarations / Misc
+//=====================================================================
+   parameter              DBG_1FOURTH = DBG_WIDTH/4;
+   parameter              DBG_2FOURTH = DBG_WIDTH/2;
+   parameter              DBG_3FOURTH = 3 * DBG_WIDTH/4;
+
+   wire [0:DBG_WIDTH-1]   debug_grp_selected;
+   wire [0:DBG_WIDTH-1]   debug_grp_rotated;
+
+// Don't reference unused inputs:
+(* analysis_not_referenced="true" *)
+   wire                   unused;
+   assign unused = select_bits[4];
+
+// Instruction Trace controls are passed-through:
+   assign coretrace_ctrls_out =  coretrace_ctrls_in ;
+
+//=====================================================================
+// Mux Function
+//=====================================================================
+   // Debug Mux
+   assign debug_grp_selected = (select_bits[0:3] == 4'b0000) ? dbg_group0 :
+                               (select_bits[0:3] == 4'b0001) ? dbg_group1 :
+                               (select_bits[0:3] == 4'b0010) ? dbg_group2 :
+                               (select_bits[0:3] == 4'b0011) ? dbg_group3 :
+                               (select_bits[0:3] == 4'b0100) ? dbg_group4 :
+                               (select_bits[0:3] == 4'b0101) ? dbg_group5 :
+                               (select_bits[0:3] == 4'b0110) ? dbg_group6 :
+                               (select_bits[0:3] == 4'b0111) ? dbg_group7 :
+                               (select_bits[0:3] == 4'b1000) ? dbg_group8 :
+                               (select_bits[0:3] == 4'b1001) ? dbg_group9 :
+                               (select_bits[0:3] == 4'b1010) ? dbg_group10 :
+                               (select_bits[0:3] == 4'b1011) ? dbg_group11 :
+                               (select_bits[0:3] == 4'b1100) ? dbg_group12 :
+                               (select_bits[0:3] == 4'b1101) ? dbg_group13 :
+                               (select_bits[0:3] == 4'b1110) ? dbg_group14 :
+                               dbg_group15;
+
+   assign debug_grp_rotated  = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
+                               (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
+                               (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
+                               debug_grp_selected[0:DBG_WIDTH - 1];
+
+
+   assign trace_data_out[0:DBG_1FOURTH - 1]           = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
+                                                        debug_grp_rotated[0:DBG_1FOURTH - 1];
+
+   assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
+                                                        debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
+
+   assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
+                                                        debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
+
+   assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1]   = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
+                                                        debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
+
+
+endmodule
+

rel/src/verilog/trilib/tri_debug_mux32.v

@@ -0,0 +1,202 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+//********************************************************************
+//*
+//* TITLE: Debug Mux Component (32:1 Debug Groups; 4:1 Trigger Groups)
+//*
+//* NAME: tri_debug_mux32.vhdl
+//*
+//********************************************************************
+
+
+module tri_debug_mux32(
+//   vd,
+//   gd,
+   select_bits,
+   dbg_group0,
+   dbg_group1,
+   dbg_group2,
+   dbg_group3,
+   dbg_group4,
+   dbg_group5,
+   dbg_group6,
+   dbg_group7,
+   dbg_group8,
+   dbg_group9,
+   dbg_group10,
+   dbg_group11,
+   dbg_group12,
+   dbg_group13,
+   dbg_group14,
+   dbg_group15,
+   dbg_group16,
+   dbg_group17,
+   dbg_group18,
+   dbg_group19,
+   dbg_group20,
+   dbg_group21,
+   dbg_group22,
+   dbg_group23,
+   dbg_group24,
+   dbg_group25,
+   dbg_group26,
+   dbg_group27,
+   dbg_group28,
+   dbg_group29,
+   dbg_group30,
+   dbg_group31,
+   trace_data_in,
+   trace_data_out,
+
+   // Instruction Trace (HTM) Controls
+   coretrace_ctrls_in,
+   coretrace_ctrls_out
+);
+
+// Include model build parameters
+   parameter              DBG_WIDTH = 32;	// A2o=32; A2i=88
+
+//=====================================================================
+// Port Definitions
+//=====================================================================
+
+   input [0:10]           select_bits;
+   input [0:DBG_WIDTH-1]  dbg_group0;
+   input [0:DBG_WIDTH-1]  dbg_group1;
+   input [0:DBG_WIDTH-1]  dbg_group2;
+   input [0:DBG_WIDTH-1]  dbg_group3;
+   input [0:DBG_WIDTH-1]  dbg_group4;
+   input [0:DBG_WIDTH-1]  dbg_group5;
+   input [0:DBG_WIDTH-1]  dbg_group6;
+   input [0:DBG_WIDTH-1]  dbg_group7;
+   input [0:DBG_WIDTH-1]  dbg_group8;
+   input [0:DBG_WIDTH-1]  dbg_group9;
+   input [0:DBG_WIDTH-1]  dbg_group10;
+   input [0:DBG_WIDTH-1]  dbg_group11;
+   input [0:DBG_WIDTH-1]  dbg_group12;
+   input [0:DBG_WIDTH-1]  dbg_group13;
+   input [0:DBG_WIDTH-1]  dbg_group14;
+   input [0:DBG_WIDTH-1]  dbg_group15;
+   input [0:DBG_WIDTH-1]  dbg_group16;
+   input [0:DBG_WIDTH-1]  dbg_group17;
+   input [0:DBG_WIDTH-1]  dbg_group18;
+   input [0:DBG_WIDTH-1]  dbg_group19;
+   input [0:DBG_WIDTH-1]  dbg_group20;
+   input [0:DBG_WIDTH-1]  dbg_group21;
+   input [0:DBG_WIDTH-1]  dbg_group22;
+   input [0:DBG_WIDTH-1]  dbg_group23;
+   input [0:DBG_WIDTH-1]  dbg_group24;
+   input [0:DBG_WIDTH-1]  dbg_group25;
+   input [0:DBG_WIDTH-1]  dbg_group26;
+   input [0:DBG_WIDTH-1]  dbg_group27;
+   input [0:DBG_WIDTH-1]  dbg_group28;
+   input [0:DBG_WIDTH-1]  dbg_group29;
+   input [0:DBG_WIDTH-1]  dbg_group30;
+   input [0:DBG_WIDTH-1]  dbg_group31;
+   input [0:DBG_WIDTH-1]  trace_data_in;
+   output [0:DBG_WIDTH-1] trace_data_out;
+
+// Instruction Trace (HTM) Control Signals:
+//  0    - ac_an_coretrace_first_valid
+//  1    - ac_an_coretrace_valid
+//  2:3  - ac_an_coretrace_type[0:1]
+   input  [0:3]           coretrace_ctrls_in;
+   output [0:3]           coretrace_ctrls_out;
+
+//=====================================================================
+// Signal Declarations / Misc
+//=====================================================================
+   parameter              DBG_1FOURTH = DBG_WIDTH/4;
+   parameter              DBG_2FOURTH = DBG_WIDTH/2;
+   parameter              DBG_3FOURTH = 3 * DBG_WIDTH/4;
+
+   wire [0:DBG_WIDTH-1]   debug_grp_selected;
+   wire [0:DBG_WIDTH-1]   debug_grp_rotated;
+
+// Instruction Trace controls are passed-through:
+   assign coretrace_ctrls_out =  coretrace_ctrls_in ;
+
+//=====================================================================
+// Mux Function
+//=====================================================================
+   // Debug Mux
+   assign debug_grp_selected = (select_bits[0:4] == 5'b00000) ? dbg_group0 :
+                               (select_bits[0:4] == 5'b00001) ? dbg_group1 :
+                               (select_bits[0:4] == 5'b00010) ? dbg_group2 :
+                               (select_bits[0:4] == 5'b00011) ? dbg_group3 :
+                               (select_bits[0:4] == 5'b00100) ? dbg_group4 :
+                               (select_bits[0:4] == 5'b00101) ? dbg_group5 :
+                               (select_bits[0:4] == 5'b00110) ? dbg_group6 :
+                               (select_bits[0:4] == 5'b00111) ? dbg_group7 :
+                               (select_bits[0:4] == 5'b01000) ? dbg_group8 :
+                               (select_bits[0:4] == 5'b01001) ? dbg_group9 :
+                               (select_bits[0:4] == 5'b01010) ? dbg_group10 :
+                               (select_bits[0:4] == 5'b01011) ? dbg_group11 :
+                               (select_bits[0:4] == 5'b01100) ? dbg_group12 :
+                               (select_bits[0:4] == 5'b01101) ? dbg_group13 :
+                               (select_bits[0:4] == 5'b01110) ? dbg_group14 :
+                               (select_bits[0:4] == 5'b01111) ? dbg_group15 :
+                               (select_bits[0:4] == 5'b10000) ? dbg_group16 :
+                               (select_bits[0:4] == 5'b10001) ? dbg_group17 :
+                               (select_bits[0:4] == 5'b10010) ? dbg_group18 :
+                               (select_bits[0:4] == 5'b10011) ? dbg_group19 :
+                               (select_bits[0:4] == 5'b10100) ? dbg_group20 :
+                               (select_bits[0:4] == 5'b10101) ? dbg_group21 :
+                               (select_bits[0:4] == 5'b10110) ? dbg_group22 :
+                               (select_bits[0:4] == 5'b10111) ? dbg_group23 :
+                               (select_bits[0:4] == 5'b11000) ? dbg_group24 :
+                               (select_bits[0:4] == 5'b11001) ? dbg_group25 :
+                               (select_bits[0:4] == 5'b11010) ? dbg_group26 :
+                               (select_bits[0:4] == 5'b11011) ? dbg_group27 :
+                               (select_bits[0:4] == 5'b11100) ? dbg_group28 :
+                               (select_bits[0:4] == 5'b11101) ? dbg_group29 :
+                               (select_bits[0:4] == 5'b11110) ? dbg_group30 :
+                               dbg_group31;
+
+   assign debug_grp_rotated  = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
+                               (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
+                               (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
+                               debug_grp_selected[0:DBG_WIDTH - 1];
+
+
+   assign trace_data_out[0:DBG_1FOURTH - 1]           = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
+                                                        debug_grp_rotated[0:DBG_1FOURTH - 1];
+
+   assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
+                                                        debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
+
+   assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
+                                                        debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
+
+   assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1]   = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
+                                                        debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
+
+
+endmodule
+

rel/src/verilog/trilib/tri_debug_mux4.v

@@ -0,0 +1,122 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+//********************************************************************
+//*
+//* TITLE: Debug Mux Component (4:1 Debug Groups; 4:1 Trigger Groups)
+//*
+//* NAME: tri_debug_mux4.vhdl
+//*
+//********************************************************************
+
+
+module tri_debug_mux4(
+//   vd,
+//   gd,
+   select_bits,
+   dbg_group0,
+   dbg_group1,
+   dbg_group2,
+   dbg_group3,
+   trace_data_in,
+   trace_data_out,
+
+   // Instruction Trace (HTM) Controls
+   coretrace_ctrls_in,
+   coretrace_ctrls_out
+);
+
+// Include model build parameters
+   parameter              DBG_WIDTH = 32;	// A2o=32; A2i=88
+
+//=====================================================================
+// Port Definitions
+//=====================================================================
+
+   input  [0:10]          select_bits;
+   input  [0:DBG_WIDTH-1] dbg_group0;
+   input  [0:DBG_WIDTH-1] dbg_group1;
+   input  [0:DBG_WIDTH-1] dbg_group2;
+   input  [0:DBG_WIDTH-1] dbg_group3;
+   input  [0:DBG_WIDTH-1] trace_data_in;
+   output [0:DBG_WIDTH-1] trace_data_out;
+
+// Instruction Trace (HTM) Control Signals:
+//  0    - ac_an_coretrace_first_valid
+//  1    - ac_an_coretrace_valid
+//  2:3  - ac_an_coretrace_type[0:1]
+   input  [0:3]           coretrace_ctrls_in;
+   output [0:3]           coretrace_ctrls_out;
+
+//=====================================================================
+// Signal Declarations / Misc
+//=====================================================================
+   parameter              DBG_1FOURTH = DBG_WIDTH/4;
+   parameter              DBG_2FOURTH = DBG_WIDTH/2;
+   parameter              DBG_3FOURTH = 3 * DBG_WIDTH/4;
+
+   wire [0:DBG_WIDTH-1]   debug_grp_selected;
+   wire [0:DBG_WIDTH-1]   debug_grp_rotated;
+
+// Don't reference unused inputs:
+(* analysis_not_referenced="true" *)
+   wire                   unused;
+   assign unused = (|select_bits[2:4]) ;
+
+// Instruction Trace controls are passed-through:
+   assign coretrace_ctrls_out =  coretrace_ctrls_in ;
+
+//=====================================================================
+// Mux Function
+//=====================================================================
+   // Debug Mux
+   assign debug_grp_selected = (select_bits[0:1] == 2'b00) ? dbg_group0 :
+                               (select_bits[0:1] == 2'b01) ? dbg_group1 :
+                               (select_bits[0:1] == 2'b10) ? dbg_group2 :
+                               dbg_group3;
+
+   assign debug_grp_rotated  = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
+                               (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
+                               (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
+                               debug_grp_selected[0:DBG_WIDTH - 1];
+
+
+   assign trace_data_out[0:DBG_1FOURTH - 1]		= (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
+				                              debug_grp_rotated[0:DBG_1FOURTH - 1];
+
+   assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1]	= (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
+                                                          debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
+
+   assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1]	= (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
+                                                          debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
+
+   assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1]	= (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
+                                                          debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
+
+
+endmodule

rel/src/verilog/trilib/tri_debug_mux8.v

@@ -0,0 +1,132 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+//********************************************************************
+//*
+//* TITLE: Debug Mux Component (8:1 Debug Groups; 4:1 Trigger Groups)
+//*
+//* NAME: tri_debug_mux8.vhdl
+//*
+//********************************************************************
+
+module tri_debug_mux8(
+//   vd,
+//   gd,
+   select_bits,
+   dbg_group0,
+   dbg_group1,
+   dbg_group2,
+   dbg_group3,
+   dbg_group4,
+   dbg_group5,
+   dbg_group6,
+   dbg_group7,
+   trace_data_in,
+   trace_data_out,
+   // Instruction Trace (HTM) Controls
+   coretrace_ctrls_in,
+   coretrace_ctrls_out
+);
+
+// Include model build parameters
+   parameter              DBG_WIDTH = 32;	// A2o=32; A2i=88
+
+//=====================================================================
+// Port Definitions
+//=====================================================================
+
+   input [0:10]           select_bits;
+   input [0:DBG_WIDTH-1]  dbg_group0;
+   input [0:DBG_WIDTH-1]  dbg_group1;
+   input [0:DBG_WIDTH-1]  dbg_group2;
+   input [0:DBG_WIDTH-1]  dbg_group3;
+   input [0:DBG_WIDTH-1]  dbg_group4;
+   input [0:DBG_WIDTH-1]  dbg_group5;
+   input [0:DBG_WIDTH-1]  dbg_group6;
+   input [0:DBG_WIDTH-1]  dbg_group7;
+   input [0:DBG_WIDTH-1]  trace_data_in;
+   output [0:DBG_WIDTH-1] trace_data_out;
+
+// Instruction Trace (HTM) Control Signals:
+//  0    - ac_an_coretrace_first_valid
+//  1    - ac_an_coretrace_valid
+//  2:3  - ac_an_coretrace_type[0:1]
+   input  [0:3]           coretrace_ctrls_in;
+   output [0:3]           coretrace_ctrls_out;
+
+//=====================================================================
+// Signal Declarations / Misc
+//=====================================================================
+   parameter              DBG_1FOURTH = DBG_WIDTH/4;
+   parameter              DBG_2FOURTH = DBG_WIDTH/2;
+   parameter              DBG_3FOURTH = 3 * DBG_WIDTH/4;
+
+   wire [0:DBG_WIDTH-1]   debug_grp_selected;
+   wire [0:DBG_WIDTH-1]   debug_grp_rotated;
+
+// Don't reference unused inputs:
+(* analysis_not_referenced="true" *)
+   wire                   unused;
+   assign unused = (|select_bits[3:4]) ;
+
+// Instruction Trace controls are passed-through:
+   assign coretrace_ctrls_out =  coretrace_ctrls_in ;
+
+//=====================================================================
+// Mux Function
+//=====================================================================
+   // Debug Mux
+
+   assign debug_grp_selected = (select_bits[0:2] == 3'b000) ? dbg_group0 :
+                               (select_bits[0:2] == 3'b001) ? dbg_group1 :
+                               (select_bits[0:2] == 3'b010) ? dbg_group2 :
+                               (select_bits[0:2] == 3'b011) ? dbg_group3 :
+                               (select_bits[0:2] == 3'b100) ? dbg_group4 :
+                               (select_bits[0:2] == 3'b101) ? dbg_group5 :
+                               (select_bits[0:2] == 3'b110) ? dbg_group6 :
+                               dbg_group7;
+
+   assign debug_grp_rotated  = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
+                               (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
+                               (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
+                               debug_grp_selected[0:DBG_WIDTH - 1];
+
+
+   assign trace_data_out[0:DBG_1FOURTH - 1]           = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
+                                                        debug_grp_rotated[0:DBG_1FOURTH - 1];
+
+   assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
+                                                        debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
+
+   assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
+                                                        debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
+
+   assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1]   = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
+                                                        debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
+
+endmodule

rel/src/verilog/trilib/tri_direct_err_rpt.v

@@ -0,0 +1,57 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_direct_err_rpt.v
+// *! DESCRIPTION : Error Reporting Component
+// *!****************************************************************
+
+module tri_direct_err_rpt(
+   vd,
+   gd,
+   err_in,
+   err_out
+);
+   parameter          WIDTH = 1;		// use to bundle error reporting checkers of the same exact type
+   inout              vd;
+   inout              gd;
+
+   input [0:WIDTH-1]  err_in;
+   output [0:WIDTH-1] err_out;
+
+   // tri_direct_err_rpt
+
+    (* analysis_not_referenced="true" *)
+   wire               unused;
+
+   assign unused = vd | gd;
+
+   assign err_out = err_in;
+endmodule

rel/src/verilog/trilib/tri_eccchk.v

@@ -0,0 +1,284 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+//  Description:  XU ECC Check Macro
+//
+//*****************************************************************************
+
+module tri_eccchk(
+   din,
+   encorr,
+   nsyn,
+   corrd,
+   sbe,
+   ue
+);
+
+   parameter                REGSIZE = 64;
+
+   input [0:REGSIZE-1]      din;
+   input                    encorr;
+   input [0:8-(64/REGSIZE)] nsyn;
+   output [0:REGSIZE-1]     corrd;
+   output                   sbe;
+   output                   ue;
+
+      generate		// syndrome bits inverted
+         if (REGSIZE == 64)
+         begin : ecc64
+            wire [0:7]                syn;
+            wire [0:71]               DcdD;		// decode data bits
+            wire                      synzero;
+            wire                      sbe_int;
+            wire [0:3]                A0to1;
+            wire [0:3]                A2to3;
+            wire [0:3]                A4to5;
+            wire [0:2]                A6to7;
+
+            // ====================================================================
+            // 64 Data Bits, 8 Check bits
+            // Single bit error correction, Double bit error detection
+            // ====================================================================
+            //                        ECC Matrix Description
+            // ====================================================================
+            // Syn 0   111011010011101001100101101101001100101101001011001101001110100110000000
+            // Syn 1   110110101011010101010101011010101010101010101010101010101101010101000000
+            // Syn 2   101101100110110011001100110110011001100110011001100110011011001100100000
+            // Syn 3   011100011110001111000011110001111000011110000111100001111000111100010000
+            // Syn 4   000011111110000000111111110000000111111110000000011111111000000000001000
+            // Syn 5   000000000001111111111111110000000000000001111111111111111000000000000100
+            // Syn 6   000000000000000000000000001111111111111111111111111111111000000000000010
+            // Syn 7   000000000000000000000000000000000000000000000000000000000111111100000001
+
+            assign syn = (~nsyn[0:7]);
+
+            assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr));
+            assign A0to1[1] = (~(nsyn[0] &  syn[1] & encorr));
+            assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr));
+            assign A0to1[3] = (~( syn[0] &  syn[1] & encorr));
+
+            assign A2to3[0] = (~(nsyn[2] & nsyn[3]));
+            assign A2to3[1] = (~(nsyn[2] &  syn[3]));
+            assign A2to3[2] = (~( syn[2] & nsyn[3]));
+            assign A2to3[3] = (~( syn[2] &  syn[3]));
+
+            assign A4to5[0] = (~(nsyn[4] & nsyn[5]));
+            assign A4to5[1] = (~(nsyn[4] &  syn[5]));
+            assign A4to5[2] = (~( syn[4] & nsyn[5]));
+            assign A4to5[3] = (~( syn[4] &  syn[5]));
+
+            assign A6to7[0] = (~(nsyn[6] & nsyn[7]));
+            assign A6to7[1] = (~(nsyn[6] &  syn[7]));
+            assign A6to7[2] = (~( syn[6] & nsyn[7]));
+            //assign A6to7[3] = (~( syn[6] &  syn[7]));
+
+            assign DcdD[0]  = (~(A0to1[3] | A2to3[2] | A4to5[0] | A6to7[0]));		// 11 10 00 00
+            assign DcdD[1]  = (~(A0to1[3] | A2to3[1] | A4to5[0] | A6to7[0]));		// 11 01 00 00
+            assign DcdD[2]  = (~(A0to1[2] | A2to3[3] | A4to5[0] | A6to7[0]));		// 10 11 00 00
+            assign DcdD[3]  = (~(A0to1[1] | A2to3[3] | A4to5[0] | A6to7[0]));		// 01 11 00 00
+            assign DcdD[4]  = (~(A0to1[3] | A2to3[0] | A4to5[2] | A6to7[0]));		// 11 00 10 00
+            assign DcdD[5]  = (~(A0to1[2] | A2to3[2] | A4to5[2] | A6to7[0]));		// 10 10 10 00
+            assign DcdD[6]  = (~(A0to1[1] | A2to3[2] | A4to5[2] | A6to7[0]));		// 01 10 10 00
+            assign DcdD[7]  = (~(A0to1[2] | A2to3[1] | A4to5[2] | A6to7[0]));		// 10 01 10 00
+            assign DcdD[8]  = (~(A0to1[1] | A2to3[1] | A4to5[2] | A6to7[0]));		// 01 01 10 00
+            assign DcdD[9]  = (~(A0to1[0] | A2to3[3] | A4to5[2] | A6to7[0]));		// 00 11 10 00
+            assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to5[2] | A6to7[0]));		// 11 11 10 00
+            assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to5[1] | A6to7[0]));		// 11 00 01 00
+            assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to5[1] | A6to7[0]));		// 10 10 01 00
+            assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to5[1] | A6to7[0]));		// 01 10 01 00
+            assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to5[1] | A6to7[0]));		// 10 01 01 00
+            assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to5[1] | A6to7[0]));		// 01 01 01 00
+            assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to5[1] | A6to7[0]));		// 00 11 01 00
+            assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to5[1] | A6to7[0]));		// 11 11 01 00
+            assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to5[3] | A6to7[0]));		// 10 00 11 00
+            assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to5[3] | A6to7[0]));		// 01 00 11 00
+            assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to5[3] | A6to7[0]));		// 00 10 11 00
+            assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to5[3] | A6to7[0]));		// 11 10 11 00
+            assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to5[3] | A6to7[0]));		// 00 01 11 00
+            assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to5[3] | A6to7[0]));		// 11 01 11 00
+            assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to5[3] | A6to7[0]));		// 10 11 11 00
+            assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to5[3] | A6to7[0]));		// 01 11 11 00
+            assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[2]));		// 11 00 00 10
+            assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[2]));		// 10 10 00 10
+            assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[2]));		// 01 10 00 10
+            assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[2]));		// 10 01 00 10
+            assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[2]));		// 01 01 00 10
+            assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[2]));		// 00 11 00 10
+            assign DcdD[32] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[2]));		// 11 11 00 10
+            assign DcdD[33] = (~(A0to1[2] | A2to3[0] | A4to5[2] | A6to7[2]));		// 10 00 10 10
+            assign DcdD[34] = (~(A0to1[1] | A2to3[0] | A4to5[2] | A6to7[2]));		// 01 00 10 10
+            assign DcdD[35] = (~(A0to1[0] | A2to3[2] | A4to5[2] | A6to7[2]));		// 00 10 10 10
+            assign DcdD[36] = (~(A0to1[3] | A2to3[2] | A4to5[2] | A6to7[2]));		// 11 10 10 10
+            assign DcdD[37] = (~(A0to1[0] | A2to3[1] | A4to5[2] | A6to7[2]));		// 00 01 10 10
+            assign DcdD[38] = (~(A0to1[3] | A2to3[1] | A4to5[2] | A6to7[2]));		// 11 01 10 10
+            assign DcdD[39] = (~(A0to1[2] | A2to3[3] | A4to5[2] | A6to7[2]));		// 10 11 10 10
+            assign DcdD[40] = (~(A0to1[1] | A2to3[3] | A4to5[2] | A6to7[2]));		// 01 11 10 10
+            assign DcdD[41] = (~(A0to1[2] | A2to3[0] | A4to5[1] | A6to7[2]));		// 10 00 01 10
+            assign DcdD[42] = (~(A0to1[1] | A2to3[0] | A4to5[1] | A6to7[2]));		// 01 00 01 10
+            assign DcdD[43] = (~(A0to1[0] | A2to3[2] | A4to5[1] | A6to7[2]));		// 00 10 01 10
+            assign DcdD[44] = (~(A0to1[3] | A2to3[2] | A4to5[1] | A6to7[2]));		// 11 10 01 10
+            assign DcdD[45] = (~(A0to1[0] | A2to3[1] | A4to5[1] | A6to7[2]));		// 00 01 01 10
+            assign DcdD[46] = (~(A0to1[3] | A2to3[1] | A4to5[1] | A6to7[2]));		// 11 01 01 10
+            assign DcdD[47] = (~(A0to1[2] | A2to3[3] | A4to5[1] | A6to7[2]));		// 10 11 01 10
+            assign DcdD[48] = (~(A0to1[1] | A2to3[3] | A4to5[1] | A6to7[2]));		// 01 11 01 10
+            assign DcdD[49] = (~(A0to1[0] | A2to3[0] | A4to5[3] | A6to7[2]));		// 00 00 11 10
+            assign DcdD[50] = (~(A0to1[3] | A2to3[0] | A4to5[3] | A6to7[2]));		// 11 00 11 10
+            assign DcdD[51] = (~(A0to1[2] | A2to3[2] | A4to5[3] | A6to7[2]));		// 10 10 11 10
+            assign DcdD[52] = (~(A0to1[1] | A2to3[2] | A4to5[3] | A6to7[2]));		// 01 10 11 10
+            assign DcdD[53] = (~(A0to1[2] | A2to3[1] | A4to5[3] | A6to7[2]));		// 10 01 11 10
+            assign DcdD[54] = (~(A0to1[1] | A2to3[1] | A4to5[3] | A6to7[2]));		// 01 01 11 10
+            assign DcdD[55] = (~(A0to1[0] | A2to3[3] | A4to5[3] | A6to7[2]));		// 00 11 11 10
+            assign DcdD[56] = (~(A0to1[3] | A2to3[3] | A4to5[3] | A6to7[2]));		// 11 11 11 10
+            assign DcdD[57] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[1]));		// 11 00 00 01
+            assign DcdD[58] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[1]));		// 10 10 00 01
+            assign DcdD[59] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[1]));		// 01 10 00 01
+            assign DcdD[60] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[1]));		// 10 01 00 01
+            assign DcdD[61] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[1]));		// 01 01 00 01
+            assign DcdD[62] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[1]));		// 00 11 00 01
+            assign DcdD[63] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[1]));		// 11 11 00 01
+            assign DcdD[64] = (~(A0to1[2] | A2to3[0] | A4to5[0] | A6to7[0]));		// 10 00 00 00
+            assign DcdD[65] = (~(A0to1[1] | A2to3[0] | A4to5[0] | A6to7[0]));		// 01 00 00 00
+            assign DcdD[66] = (~(A0to1[0] | A2to3[2] | A4to5[0] | A6to7[0]));		// 00 10 00 00
+            assign DcdD[67] = (~(A0to1[0] | A2to3[1] | A4to5[0] | A6to7[0]));		// 00 01 00 00
+            assign DcdD[68] = (~(A0to1[0] | A2to3[0] | A4to5[2] | A6to7[0]));		// 00 00 10 00
+            assign DcdD[69] = (~(A0to1[0] | A2to3[0] | A4to5[1] | A6to7[0]));		// 00 00 01 00
+            assign DcdD[70] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[2]));		// 00 00 00 10
+            assign DcdD[71] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[1]));		// 00 00 00 01
+            assign synzero  = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[0]));		// 00 00 00 00
+
+            assign corrd[0:63] = din[0:63] ^ DcdD[0:63];
+
+            assign sbe_int = (DcdD[0:71] != {72{1'b0}}) ? 1'b1 :
+                             1'b0;
+            assign sbe = sbe_int;
+            assign ue = (~sbe_int) & (~synzero) & encorr;
+         end
+      endgenerate
+
+      generate		// syndrome bits inverted
+         if (REGSIZE == 32)
+         begin : ecc32
+            wire [0:6]                syn;
+            wire [0:38]               DcdD;		// decode data bits
+            wire                      synzero;
+            wire                      sbe_int;
+            wire [0:3]                A0to1;
+            wire [0:3]                A2to3;
+            wire [0:7]                A4to6;
+
+            // ====================================================================
+            // 32 Data Bits, 7 Check bits
+            // Single bit error correction, Double bit error detection
+            // ====================================================================
+            //                        ECC Matrix Description
+            // ====================================================================
+            // Syn 0   111011010011101001100101101101001000000
+            // Syn 1   110110101011010101010101011010100100000
+            // Syn 2   101101100110110011001100110110010010000
+            // Syn 3   011100011110001111000011110001110001000
+            // Syn 4   000011111110000000111111110000000000100
+            // Syn 5   000000000001111111111111110000000000010
+            // Syn 6   000000000000000000000000001111110000001
+
+            assign syn = (~nsyn[0:6]);
+
+            assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr));
+            assign A0to1[1] = (~(nsyn[0] &  syn[1] & encorr));
+            assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr));
+            assign A0to1[3] = (~( syn[0] &  syn[1] & encorr));
+
+            assign A2to3[0] = (~(nsyn[2] & nsyn[3]));
+            assign A2to3[1] = (~(nsyn[2] &  syn[3]));
+            assign A2to3[2] = (~( syn[2] & nsyn[3]));
+            assign A2to3[3] = (~( syn[2] &  syn[3]));
+
+            assign A4to6[0] = (~(nsyn[4] & nsyn[5] & nsyn[6]));
+            assign A4to6[1] = (~(nsyn[4] & nsyn[5] &  syn[6]));
+            assign A4to6[2] = (~(nsyn[4] &  syn[5] & nsyn[6]));
+            assign A4to6[3] = (~(nsyn[4] &  syn[5] &  syn[6]));
+            assign A4to6[4] = (~( syn[4] & nsyn[5] & nsyn[6]));
+            assign A4to6[5] = (~( syn[4] & nsyn[5] &  syn[6]));
+            assign A4to6[6] = (~( syn[4] &  syn[5] & nsyn[6]));
+            assign A4to6[7] = (~( syn[4] &  syn[5] &  syn[6]));
+
+            assign DcdD[0]  = (~(A0to1[3] | A2to3[2] | A4to6[0]));		// 11 10 000
+            assign DcdD[1]  = (~(A0to1[3] | A2to3[1] | A4to6[0]));		// 11 01 000
+            assign DcdD[2]  = (~(A0to1[2] | A2to3[3] | A4to6[0]));		// 10 11 000
+            assign DcdD[3]  = (~(A0to1[1] | A2to3[3] | A4to6[0]));		// 01 11 000
+            assign DcdD[4]  = (~(A0to1[3] | A2to3[0] | A4to6[4]));		// 11 00 100
+            assign DcdD[5]  = (~(A0to1[2] | A2to3[2] | A4to6[4]));		// 10 10 100
+            assign DcdD[6]  = (~(A0to1[1] | A2to3[2] | A4to6[4]));		// 01 10 100
+            assign DcdD[7]  = (~(A0to1[2] | A2to3[1] | A4to6[4]));		// 10 01 100
+            assign DcdD[8]  = (~(A0to1[1] | A2to3[1] | A4to6[4]));		// 01 01 100
+            assign DcdD[9]  = (~(A0to1[0] | A2to3[3] | A4to6[4]));		// 00 11 100
+            assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to6[4]));		// 11 11 100
+            assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to6[2]));		// 11 00 010
+            assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to6[2]));		// 10 10 010
+            assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to6[2]));		// 01 10 010
+            assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to6[2]));		// 10 01 010
+            assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to6[2]));		// 01 01 010
+            assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to6[2]));		// 00 11 010
+            assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to6[2]));		// 11 11 010
+            assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to6[6]));		// 10 00 110
+            assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to6[6]));		// 01 00 110
+            assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to6[6]));		// 00 10 110
+            assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to6[6]));		// 11 10 110
+            assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to6[6]));		// 00 01 110
+            assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to6[6]));		// 11 01 110
+            assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to6[6]));		// 10 11 110
+            assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to6[6]));		// 01 11 110
+            assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to6[1]));		// 11 00 001
+            assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to6[1]));		// 10 10 001
+            assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to6[1]));		// 01 10 001
+            assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to6[1]));		// 10 01 001
+            assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to6[1]));		// 01 01 001
+            assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to6[1]));		// 00 11 001
+            assign DcdD[32] = (~(A0to1[2] | A2to3[0] | A4to6[0]));		// 10 00 000
+            assign DcdD[33] = (~(A0to1[1] | A2to3[0] | A4to6[0]));		// 01 00 000
+            assign DcdD[34] = (~(A0to1[0] | A2to3[2] | A4to6[0]));		// 00 10 000
+            assign DcdD[35] = (~(A0to1[0] | A2to3[1] | A4to6[0]));		// 00 01 000
+            assign DcdD[36] = (~(A0to1[0] | A2to3[0] | A4to6[4]));		// 00 00 100
+            assign DcdD[37] = (~(A0to1[0] | A2to3[0] | A4to6[2]));		// 00 00 010
+            assign DcdD[38] = (~(A0to1[0] | A2to3[0] | A4to6[1]));		// 00 00 001
+            assign synzero  = (~(A0to1[0] | A2to3[0] | A4to6[0]));		// 00 00 000
+
+            assign corrd[0:31] = din[0:31] ^ DcdD[0:31];
+
+            assign sbe_int = (DcdD[0:38] != {39{1'b0}}) ? 1'b1 :
+                             1'b0;
+            assign sbe = sbe_int;
+            assign ue = (~sbe_int) & (~synzero) & encorr;
+
+            //mark_unused(A4to6(3));
+            //mark_unused(A4to6(5));
+            //mark_unused(A4to6(7));
+         end
+      endgenerate
+endmodule

rel/src/verilog/trilib/tri_eccgen.v

@@ -0,0 +1,145 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+//  Description:  XU ECC Generation Macro
+//
+//*****************************************************************************
+
+module tri_eccgen(
+   din,
+   syn
+);
+   parameter                        REGSIZE = 64;
+   input [0:REGSIZE+8-(64/REGSIZE)] din;
+   output [0:8-(64/REGSIZE)]        syn;
+
+      generate		// syndrome bits inverted
+         if (REGSIZE == 64)
+         begin : ecc64
+            wire [0:71]                       e;
+            wire [0:22]                       l1term;
+
+            // ====================================================================
+            // 64 data bits, 8 check bits
+            // single bit error correction, double bit error detection
+            // ====================================================================
+            //                        ecc matrix description
+            // ====================================================================
+            // syn 0   111011010011101001100101101101001100101101001011001101001110100110000000
+            // syn 1   110110101011010101010101011010101010101010101010101010101101010101000000
+            // syn 2   101101100110110011001100110110011001100110011001100110011011001100100000
+            // syn 3   011100011110001111000011110001111000011110000111100001111000111100010000
+            // syn 4   000011111110000000111111110000000111111110000000011111111000000000001000
+            // syn 5   000000000001111111111111110000000000000001111111111111111000000000000100
+            // syn 6   000000000000000000000000001111111111111111111111111111111000000000000010
+            // syn 7   000000000000000000000000000000000000000000000000000000000111111100000001
+
+            assign e[0:71] = din[0:71];
+
+            assign l1term[0]  = e[0] ^ e[10] ^ e[17] ^ e[21] ^ e[32] ^ e[36] ^ e[44] ^ e[56];
+            assign l1term[1]  = e[22] ^ e[23] ^ e[24] ^ e[25] ^ e[53] ^ e[54] ^ e[55] ^ e[56];
+            assign l1term[2]  = e[1] ^ e[4] ^ e[11] ^ e[23] ^ e[26] ^ e[38] ^ e[46] ^ e[50];
+            assign l1term[3]  = e[2] ^ e[5] ^ e[12] ^ e[24] ^ e[27] ^ e[39] ^ e[47] ^ e[51];
+            assign l1term[4]  = e[3] ^ e[6] ^ e[13] ^ e[25] ^ e[28] ^ e[40] ^ e[48] ^ e[52];
+            assign l1term[5]  = e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[37] ^ e[38] ^ e[39] ^ e[40];
+            assign l1term[6]  = e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[45] ^ e[46] ^ e[47] ^ e[48];
+            assign l1term[7]  = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[49] ^ e[50] ^ e[51] ^ e[52];
+            assign l1term[8]  = e[7] ^ e[14] ^ e[18] ^ e[29] ^ e[33] ^ e[41] ^ e[53] ^ e[57];
+            assign l1term[9]  = e[58] ^ e[60] ^ e[63] ^ e[64];
+            assign l1term[10] = e[8] ^ e[15] ^ e[19] ^ e[30] ^ e[34] ^ e[42] ^ e[54] ^ e[57];
+            assign l1term[11] = e[59] ^ e[61] ^ e[63] ^ e[65];
+            assign l1term[12] = e[9] ^ e[16] ^ e[20] ^ e[31] ^ e[35] ^ e[43] ^ e[55] ^ e[58];
+            assign l1term[13] = e[59] ^ e[62] ^ e[63] ^ e[66];
+            assign l1term[14] = e[1] ^ e[2] ^ e[3] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[60];
+            assign l1term[15] = e[61] ^ e[62] ^ e[63] ^ e[67];
+            assign l1term[16] = e[4] ^ e[5] ^ e[6] ^ e[33] ^ e[34] ^ e[35] ^ e[36] ^ e[68];
+            assign l1term[17] = e[11] ^ e[12] ^ e[13] ^ e[41] ^ e[42] ^ e[43] ^ e[44] ^ e[69];
+            assign l1term[18] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[33];
+            assign l1term[19] = e[34] ^ e[35] ^ e[36] ^ e[37] ^ e[38] ^ e[39] ^ e[40] ^ e[41];
+            assign l1term[20] = e[42] ^ e[43] ^ e[44] ^ e[45] ^ e[46] ^ e[47] ^ e[48] ^ e[49];
+            assign l1term[21] = e[50] ^ e[51] ^ e[52] ^ e[53] ^ e[54] ^ e[55] ^ e[56] ^ e[70];
+            assign l1term[22] = e[57] ^ e[58] ^ e[59] ^ e[60] ^ e[61] ^ e[62] ^ e[63] ^ e[71];
+            assign syn[0] = l1term[0] ^ l1term[2] ^ l1term[3] ^ l1term[8] ^ l1term[9];
+            assign syn[1] = l1term[0] ^ l1term[2] ^ l1term[4] ^ l1term[10] ^ l1term[11];
+            assign syn[2] = l1term[0] ^ l1term[3] ^ l1term[4] ^ l1term[12] ^ l1term[13];
+            assign syn[3] = l1term[1] ^ l1term[5] ^ l1term[6] ^ l1term[14] ^ l1term[15];
+            assign syn[4] = l1term[1] ^ l1term[5] ^ l1term[7] ^ l1term[16];
+            assign syn[5] = l1term[1] ^ l1term[6] ^ l1term[7] ^ l1term[17];
+            assign syn[6] = l1term[18] ^ l1term[19] ^ l1term[20] ^ l1term[21];
+            assign syn[7] = l1term[22];
+         end
+      endgenerate
+
+      generate		// syndrome bits inverted
+         if (REGSIZE == 32)
+         begin : ecc32
+            wire [0:38]                       e;
+            wire [0:13]                       l1term;
+
+            // ====================================================================
+            // 32 Data Bits, 7 Check bits
+            // Single bit error correction, Double bit error detection
+            // ====================================================================
+            //                        ECC Matrix Description
+            // ====================================================================
+            // Syn 0   111011010011101001100101101101001000000
+            // Syn 1   110110101011010101010101011010100100000
+            // Syn 2   101101100110110011001100110110010010000
+            // Syn 3   011100011110001111000011110001110001000
+            // Syn 4   000011111110000000111111110000000000100
+            // Syn 5   000000000001111111111111110000000000010
+            // Syn 6   000000000000000000000000001111110000001
+
+            assign e[0:38] = din[0:38];
+
+            assign l1term[0]  = e[0] ^ e[1] ^ e[4] ^ e[10] ^ e[11] ^ e[17] ^ e[21] ^ e[23];
+            assign l1term[1]  = e[2] ^ e[3] ^ e[9] ^ e[10] ^ e[16] ^ e[17] ^ e[24] ^ e[25];
+            assign l1term[2]  = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[22] ^ e[23] ^ e[24] ^ e[25];
+            assign l1term[3]  = e[2] ^ e[5] ^ e[7] ^ e[12] ^ e[14] ^ e[18] ^ e[24] ^ e[26];
+            assign l1term[4]  = e[27] ^ e[29] ^ e[32];
+            assign l1term[5]  = e[3] ^ e[6] ^ e[8] ^ e[13] ^ e[15] ^ e[19] ^ e[25] ^ e[26];
+            assign l1term[6]  = e[28] ^ e[30] ^ e[33];
+            assign l1term[7]  = e[0] ^ e[5] ^ e[6] ^ e[12] ^ e[13] ^ e[20] ^ e[21] ^ e[27];
+            assign l1term[8]  = e[28] ^ e[31] ^ e[34];
+            assign l1term[9]  = e[1] ^ e[7] ^ e[8] ^ e[14] ^ e[15] ^ e[22] ^ e[23] ^ e[29];
+            assign l1term[10] = e[30] ^ e[31] ^ e[35];
+            assign l1term[11] = e[4] ^ e[5] ^ e[6] ^ e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[36];
+            assign l1term[12] = e[11] ^ e[12] ^ e[13] ^ e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[37];
+            assign l1term[13] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[38];
+            assign syn[0] = l1term[0] ^ l1term[3] ^ l1term[4];
+            assign syn[1] = l1term[0] ^ l1term[5] ^ l1term[6];
+            assign syn[2] = l1term[1] ^ l1term[7] ^ l1term[8];
+            assign syn[3] = l1term[1] ^ l1term[9] ^ l1term[10];
+            assign syn[4] = l1term[2] ^ l1term[11];
+            assign syn[5] = l1term[2] ^ l1term[12];
+            assign syn[6] = l1term[13];
+         end
+      endgenerate
+endmodule

rel/src/verilog/trilib/tri_err_rpt.v

@@ -0,0 +1,142 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_err_rpt.v
+// *! DESCRIPTION : Error Reporting Component
+// *!****************************************************************
+
+`include "tri.vh"
+
+module tri_err_rpt(
+   vd,
+   gd,
+   err_d1clk,
+   err_d2clk,
+   err_lclk,
+   err_scan_in,
+   err_scan_out,
+   mode_dclk,
+   mode_lclk,
+   mode_scan_in,
+   mode_scan_out,
+   err_in,
+   err_out,
+   hold_out,
+   mask_out
+);
+   parameter                     WIDTH = 1;		// number of errors of the same type
+   parameter                     MASK_RESET_VALUE = 1'b0;	// use to set default/flush value for mask bits
+   parameter                     INLINE = 1'b0;		// make hold latch be inline; err_out is sticky -- default to shadow
+   parameter                     SHARE_MASK = 1'b0;		// PERMISSION NEEDED for true
+                                                                // used for WIDTH >1 to reduce area of mask (common error disable)
+   parameter                     USE_NLATS = 1'b0;		// only necessary in standby area to be able to reset to init value
+   parameter                     NEEDS_SRESET = 1;		// for inferred latches
+
+   inout                         vd;
+   inout                         gd;
+   input                         err_d1clk;     // caution1: if lcb uses powersavings, errors must always get reported
+   input                         err_d2clk;     // caution2: if use_nlats is used these are also the clocks for the mask latches
+   input [0:`NCLK_WIDTH-1]       err_lclk;      // caution2:   hence these have to be the mode clocks
+                                                // caution2:   and all bits in the "func" chain have to be connected to the mode chain
+   // error scan chain (func or mode)
+   input [0:WIDTH-1]             err_scan_in;   // NOTE: connected to mode or func ring
+   output [0:WIDTH-1]            err_scan_out;
+   // clock gateable mode clocks
+   input                         mode_dclk;
+   input [0:`NCLK_WIDTH-1]       mode_lclk;
+   // mode scan chain
+   input [0:WIDTH-1]             mode_scan_in;
+   output [0:WIDTH-1]            mode_scan_out;
+
+   input [0:WIDTH-1]             err_in;
+   output [0:WIDTH-1]            err_out;
+
+   output [0:WIDTH-1]            hold_out;		// sticky error hold latch for trap usage
+   output [0:WIDTH-1]            mask_out;
+
+   // tri_err_rpt
+
+   parameter [0:WIDTH-1]         mask_initv = MASK_RESET_VALUE;
+   wire [0:WIDTH-1]              hold_in;
+   wire [0:WIDTH-1]              hold_lt;
+   wire [0:WIDTH-1]              mask_lt;
+    (* analysis_not_referenced="true" *)
+   wire                          unused;
+   wire [0:WIDTH-1]              unused_q_b;
+   // hold latches
+   assign hold_in = err_in | hold_lt;
+
+   tri_nlat_scan #(.WIDTH(WIDTH), .NEEDS_SRESET(NEEDS_SRESET))
+       hold(
+            .vd(vd),
+            .gd(gd),
+            .d1clk(err_d1clk),
+            .d2clk(err_d2clk),
+            .lclk(err_lclk),
+            .scan_in(err_scan_in[0:WIDTH - 1]),
+            .scan_out(err_scan_out[0:WIDTH - 1]),
+            .din(hold_in),
+            .q(hold_lt),
+            .q_b(unused_q_b)
+            );
+
+   generate
+   begin
+      // mask
+     if (SHARE_MASK == 1'b0)
+     begin : m
+       assign mask_lt = mask_initv;
+     end
+     if (SHARE_MASK == 1'b1)
+     begin : sm
+       assign mask_lt = {WIDTH{MASK_RESET_VALUE[0]}};
+     end
+
+     assign mode_scan_out = {WIDTH{1'b0}};
+
+     // assign outputs
+     assign hold_out = hold_lt;
+     assign mask_out = mask_lt;
+
+     if (INLINE == 1'b1)
+     begin : inline_hold
+       assign err_out = hold_lt & (~mask_lt);
+     end
+
+     if (INLINE == 1'b0)
+     begin : side_hold
+       assign err_out = err_in & (~mask_lt);
+     end
+
+     assign unused = | {mode_dclk, mode_lclk, mode_scan_in, unused_q_b};
+   end
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_event_mux1t.v

@@ -0,0 +1,164 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+//********************************************************************
+//*
+//* TITLE: Performance Event Mux Component - 1 Thread; 4 bits
+//*
+//* NAME:  tri_event_mux1t.v
+//*
+//********************************************************************
+
+module tri_event_mux1t(
+   vd,
+   gd,
+   select_bits,
+   unit_events_in,
+   event_bus_in,
+   event_bus_out
+);
+   parameter                             	EVENTS_IN = 32; // Valid Settings: 16; 32; 64
+   parameter                                 	EVENTS_OUT = 4;	// Valid Settings: 4 outputs per event mux
+   // Select bit size depends on total events: 16 events=16, 32 events=20; 64 events=24
+   input  [0:((EVENTS_IN/32+4)*EVENTS_OUT)-1] 	select_bits;
+
+   input  [1:EVENTS_IN-1]                   	unit_events_in;
+
+   input  [0:EVENTS_OUT-1]                   	event_bus_in;
+
+   output [0:EVENTS_OUT-1]                   	event_bus_out;
+
+   inout                  			vd;
+
+   inout                  			gd;
+
+
+//=====================================================================
+// Signal and Function Declarations
+//=====================================================================
+// Constants used to split up select_bits for the decoder
+//                                                                       Mux Size:  16 32 64
+   parameter                                 	INCR = EVENTS_IN/32 + 4;  // INCR:   4  5  6
+
+   // For each output bit decode select bits to select an input mux to use.
+   wire [0:EVENTS_OUT*EVENTS_IN-1]         	inMuxDec;
+   wire [0:EVENTS_OUT*EVENTS_IN-1]         	inMuxOut;
+
+// Paramaterized decoder function - decode mux value based on input select_bits
+// Input size based on EVENTS_IN parameter: 	16=4, 32=5, 64=6
+   function [0:EVENTS_IN-1] decode_a;
+  	input [0:INCR-1] decode_input;
+  	(* analysis_not_referenced="true" *)
+  	integer i;
+
+	for(i=0; i<EVENTS_IN; i=i+1)
+  	begin
+  	   if({{32-INCR{1'b0}},decode_input} == i)
+  		decode_a[i] = 1'b1;
+  	   else
+  		decode_a[i] = 1'b0;
+      	end
+   endfunction
+
+
+//=====================================================================
+// Start of event mux
+//=====================================================================
+   // For each output bit, decode its select_bits to select the input mux it's using
+   generate
+      begin : xhdl0
+	 genvar      X;
+	 for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
+	 begin : decode
+	    if (EVENTS_IN == 16)
+	    begin : Mux16		// 4to16 decode; select_bits(0:3,  4:7,  8:11, 12:15 ) per output bit
+	       assign inMuxDec[X * EVENTS_IN:X * EVENTS_IN + 15] = decode_a(select_bits[X * INCR:X * INCR + 3]);
+	    end
+
+	    if (EVENTS_IN == 32)
+	    begin : Mux32		// 5to32 decode; select_bits(0:4,  5:9, 10:14, 15:19 ) per output bit
+	       assign inMuxDec[X * EVENTS_IN:X * EVENTS_IN + 31] = decode_a(select_bits[X * INCR:X * INCR + 4]);
+	    end
+
+            if (EVENTS_IN == 64)
+            begin : Mux64		// 6to64 decode; select_bits(0:5, 6:11, 12:17, 18:23 ) per output bit
+	       assign inMuxDec[X * EVENTS_IN:X * EVENTS_IN + 63] = decode_a(select_bits[X * INCR:X * INCR + 5]);
+            end
+         end
+      end
+   endgenerate
+
+   // For each output bit, inMux decodes gate the selected unit event input; or event_bus_in when decode=0
+   generate
+      begin : xhdl2
+         genvar      X;
+         for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
+         begin : inpMux
+
+                  assign inMuxOut[X * EVENTS_IN + 0] = (inMuxDec[X * EVENTS_IN + 0] & event_bus_in[X]) ;
+
+            begin : xhdl1
+               genvar      I;
+               for (I = 1; I <= EVENTS_IN - 1; I = I + 1)
+               begin : eventSel
+
+                  assign inMuxOut[X * EVENTS_IN + I] = (inMuxDec[X * EVENTS_IN + I] & unit_events_in[I]) ;
+
+               end
+            end
+         end
+      end
+   endgenerate
+
+
+   // ORing the input mux outputs to drive each event output bit.
+   // Only one selected at a time by each output bit's inMux decode value.
+   generate
+      begin : xhdl5
+         genvar      X;
+         for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
+         begin : bitOutHi
+            if (EVENTS_IN == 16)
+            begin : Mux16
+               assign event_bus_out[X] = (|inMuxOut[X * EVENTS_IN:X * EVENTS_IN + 15]);
+            end
+
+            if (EVENTS_IN == 32)
+            begin : Mux32
+               assign event_bus_out[X] = (|inMuxOut[X * EVENTS_IN:X * EVENTS_IN + 31]);
+            end
+
+            if (EVENTS_IN == 64)
+            begin : Mux64
+               assign event_bus_out[X] = (|inMuxOut[X * EVENTS_IN:X * EVENTS_IN + 63]);
+            end
+         end
+      end
+   endgenerate
+
+endmodule

rel/src/verilog/trilib/tri_fu_csa22_h2.v

@@ -0,0 +1,53 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+   `include "tri_a2o.vh"
+
+
+module tri_fu_csa22_h2(
+   a,
+   b,
+   car,
+   sum
+);
+   input   a;
+   input   b;
+   output  car;
+   output  sum;
+
+   wire    car_b;
+   wire    sum_b;
+
+   assign car_b = (~(a & b));
+   assign sum_b = (~(car_b & (a | b)));		// this is equiv to an xnor
+   assign car = (~car_b);
+   assign sum = (~sum_b);
+
+endmodule

rel/src/verilog/trilib/tri_fu_mul.v

@@ -0,0 +1,323 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+   `include "tri_a2o.vh"
+
+
+module tri_fu_mul(
+   vdd,
+   gnd,
+   clkoff_b,
+   act_dis,
+   flush,
+   delay_lclkr,
+   mpw1_b,
+   mpw2_b,
+   sg_1,
+   thold_1,
+   fpu_enable,
+   nclk,
+   f_mul_si,
+   f_mul_so,
+   ex2_act,
+   f_fmt_ex2_a_frac,
+   f_fmt_ex2_a_frac_17,
+   f_fmt_ex2_a_frac_35,
+   f_fmt_ex2_c_frac,
+   f_mul_ex3_sum,
+   f_mul_ex3_car
+);
+
+   inout          vdd;
+   inout          gnd;
+   input          clkoff_b;		// tiup
+   input          act_dis;		// ??tidn??
+   input          flush;		// ??tidn??
+   input          delay_lclkr;		// tidn,
+   input          mpw1_b;		// tidn,
+   input          mpw2_b;		// tidn,
+   input          sg_1;
+   input          thold_1;
+   input          fpu_enable;		//dc_act
+   input  [0:`NCLK_WIDTH-1]         nclk;
+
+   input          f_mul_si;		//perv
+   output         f_mul_so;		//perv
+   input          ex2_act;		//act
+
+   input [0:52]   f_fmt_ex2_a_frac;		// implicit bit already generated
+   input          f_fmt_ex2_a_frac_17;		// new port for replicated bit
+   input          f_fmt_ex2_a_frac_35;		// new port for replicated bit
+   input [0:53]   f_fmt_ex2_c_frac;		// implicit bit already generated
+
+   output [1:108] f_mul_ex3_sum;
+   output [1:108] f_mul_ex3_car;
+
+   // ENTITY
+
+
+   parameter      tiup = 1'b1;
+   parameter      tidn = 1'b0;
+
+   wire           thold_0_b;
+   wire           thold_0;
+   wire           force_t;
+   wire           sg_0;
+   wire [0:3]     spare_unused;
+   //--------------------------------------
+   wire [0:3]     act_so;		//SCAN
+   wire [0:3]     act_si;
+   wire           m92_0_so;
+   wire           m92_1_so;
+   wire           m92_2_so;
+   //--------------------------------------
+   wire [36:108]  pp3_05;
+   wire [35:108]  pp3_04;
+   wire [18:90]   pp3_03;
+   wire [17:90]   pp3_02;
+   wire [0:72]    pp3_01;
+   wire [0:72]    pp3_00;
+
+   wire           hot_one_msb_unused;
+   wire           hot_one_74;
+   wire           hot_one_92;
+   wire           xtd_unused;
+
+   wire [1:108]   pp5_00;
+   wire [1:108]   pp5_01;
+
+   ////################################################################
+   ////# pervasive
+   ////################################################################
+
+
+   tri_plat  thold_reg_0(
+      .vd(vdd),
+      .gd(gnd),
+      .nclk(nclk),
+      .flush(flush),
+      .din(thold_1),
+      .q(thold_0)
+   );
+
+
+   tri_plat  sg_reg_0(
+      .vd(vdd),
+      .gd(gnd),
+      .nclk(nclk),
+      .flush(flush),
+      .din(sg_1),
+      .q(sg_0)
+   );
+
+
+   tri_lcbor  lcbor_0(
+      .clkoff_b(clkoff_b),
+      .thold(thold_0),
+      .sg(sg_0),
+      .act_dis(act_dis),
+      .force_t(force_t),
+      .thold_b(thold_0_b)
+   );
+
+   ////################################################################
+   ////# act
+   ////################################################################
+
+
+   tri_rlmreg_p #(.WIDTH(4),  .NEEDS_SRESET(0)) act_lat(
+      .force_t(force_t),		//i-- tidn,
+      .d_mode(tiup),
+      .delay_lclkr(delay_lclkr),		//i-- tidn,
+      .mpw1_b(mpw1_b),		//i-- tidn,
+      .mpw2_b(mpw2_b),		//i-- tidn,
+      .vd(vdd),
+      .gd(gnd),
+      .nclk(nclk),
+      .act(fpu_enable),
+      .thold_b(thold_0_b),
+      .sg(sg_0),
+      .scout(act_so),
+      .scin(act_si),
+      //-----------------
+      .din({ spare_unused[0],
+             spare_unused[1],
+             spare_unused[2],
+             spare_unused[3]}),
+      //-----------------
+      .dout({spare_unused[0],
+             spare_unused[1],
+             spare_unused[2],
+             spare_unused[3]})
+   );
+
+   assign act_si[0:3] = {act_so[1:3], m92_2_so};
+
+   assign f_mul_so = act_so[0];
+
+   ////################################################################
+   ////# ex2 logic
+   ////################################################################
+
+   ////# NUMBERING SYSTEM RELATIVE TO COMPRESSOR TREE
+   ////#
+   ////#    0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111
+   ////#    0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000
+   ////#    0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
+   ////#  0 ..DdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................................................
+   ////#  1 ..1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................................
+   ////#  2 ....1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............................................
+   ////#  3 ......1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................................
+   ////#  4 ........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........................................
+   ////#  5 ..........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................................
+   ////#  6 ............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......................................
+   ////#  7 ..............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....................................
+   ////#  8 ................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................................
+
+   ////#  9 ..................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................
+   ////# 10 ....................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............................
+   ////# 11 ......................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................
+   ////# 12 ........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........................
+   ////# 13 ..........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................
+   ////# 14 ............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......................
+   ////# 15 ..............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....................
+   ////# 16 ................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................
+   ////# 17 ..................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................
+
+   ////# 18 ....................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............
+   ////# 19 ......................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............
+   ////# 20 ........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........
+   ////# 21 ..........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........
+   ////# 22 ............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......
+   ////# 23 ..............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....
+   ////# 24 ................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..
+   ////# 25 ..................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s
+   ////# 26 ...................................................assDdddddddddddddddddddddddddddddddddddddddddddddddddddddD
+
+
+   tri_fu_mul_92 #(.inst(2)) m92_2(
+      .vdd(vdd),		//i--
+      .gnd(gnd),		//i--
+      .nclk(nclk),		//i--
+      .force_t(force_t),		//i--
+      .lcb_delay_lclkr(delay_lclkr),		//i-- tidn
+      .lcb_mpw1_b(mpw1_b),		//i-- mpw1_b   others=0
+      .lcb_mpw2_b(mpw2_b),		//i-- mpw2_b   others=0
+      .thold_b(thold_0_b),		//i--
+      .lcb_sg(sg_0),		//i--
+      .si(f_mul_si),		//i--
+      .so(m92_0_so),		//o--
+      .ex2_act(ex2_act),		//i--
+      //--------------------
+      .c_frac(f_fmt_ex2_c_frac[0:53]),		//i-- Multiplicand (shift me)
+      .a_frac({f_fmt_ex2_a_frac[35:52],		//i-- Multiplier   (recode me)
+              tidn}),		//i-- Multiplier   (recode me)
+      .hot_one_out(hot_one_92),		//o--
+      .sum92(pp3_05[36:108]),		//o--
+      .car92(pp3_04[35:108])		//o--
+   );
+
+
+   tri_fu_mul_92 #(.inst(1)) m92_1(
+      .vdd(vdd),		//i--
+      .gnd(gnd),		//i--
+      .nclk(nclk),		//i--
+      .force_t(force_t),		//i--
+      .lcb_delay_lclkr(delay_lclkr),		//i-- tidn
+      .lcb_mpw1_b(mpw1_b),		//i-- mpw1_b   others=0
+      .lcb_mpw2_b(mpw2_b),		//i-- mpw2_b   others=0
+      .thold_b(thold_0_b),		//i--
+      .lcb_sg(sg_0),		//i--
+      .si(m92_0_so),		//i--
+      .so(m92_1_so),		//o-- v
+      .ex2_act(ex2_act),		//i--
+      //-------------------
+      .c_frac(f_fmt_ex2_c_frac[0:53]),		//i-- Multiplicand (shift me)
+      .a_frac({f_fmt_ex2_a_frac[17:34],		//i-- Multiplier   (recode me)
+               f_fmt_ex2_a_frac_35}),		//i-- Multiplier   (recode me)
+      .hot_one_out(hot_one_74),		//o--
+      .sum92(pp3_03[18:90]),		//o--
+      .car92(pp3_02[17:90])		//o--
+   );
+
+
+   tri_fu_mul_92 #(.inst(0)) m92_0(
+      .vdd(vdd),		//i--
+      .gnd(gnd),		//i--
+      .nclk(nclk),		//i--
+      .force_t(force_t),		//i--
+      .lcb_delay_lclkr(delay_lclkr),		//i-- tidn
+      .lcb_mpw1_b(mpw1_b),		//i-- mpw1_b   others=0
+      .lcb_mpw2_b(mpw2_b),		//i-- mpw2_b   others=0
+      .thold_b(thold_0_b),		//i--
+      .lcb_sg(sg_0),		//i--
+      .si(m92_1_so),		//i--
+      .so(m92_2_so),		//o--
+      .ex2_act(ex2_act),		//i--
+      //-------------------
+      .c_frac(f_fmt_ex2_c_frac[0:53]),		//i-- Multiplicand (shift me)
+      .a_frac({tidn,		//i-- Multiplier (recode me)
+               f_fmt_ex2_a_frac[0:16],		//i-- Multiplier (recode me)
+               f_fmt_ex2_a_frac_17}),		//i-- Multiplier (recode me)
+      .hot_one_out(hot_one_msb_unused),		//o--
+      .sum92(pp3_01[0:72]),		//o--
+      .car92({xtd_unused,		//o--
+              pp3_00[0:72]})		//o--
+   );
+
+   ////##################################################
+   ////# Compressor Level 4  , 5
+   ////##################################################
+
+
+   tri_fu_mul_62 m62(
+      .vdd(vdd),
+      .gnd(gnd),
+      .hot_one_92(hot_one_92),		//i--
+      .hot_one_74(hot_one_74),		//i--
+      .pp3_05(pp3_05[36:108]),		//i--
+      .pp3_04(pp3_04[35:108]),		//i--
+      .pp3_03(pp3_03[18:90]),		//i--
+      .pp3_02(pp3_02[17:90]),		//i--
+      .pp3_01(pp3_01[0:72]),		//i--
+      .pp3_00(pp3_00[0:72]),		//i--
+
+      .sum62(pp5_01[1:108]),		//o--
+      .car62(pp5_00[1:108])		//o--
+   );
+
+   ////################################################################
+   ////# ex3 logic
+   ////################################################################
+
+   assign f_mul_ex3_sum[1:108] = pp5_01[1:108];		//output
+   assign f_mul_ex3_car[1:108] = pp5_00[1:108];		//output
+
+endmodule

rel/src/verilog/trilib/tri_fu_mul_bthdcd.v

@@ -0,0 +1,104 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILE NAME    :  tri_fu_mul_bthdcd.vhdl
+// *! DESCRIPTION  :  Booth Decode
+// *!****************************************************************
+
+   `include "tri_a2o.vh"
+
+module tri_fu_mul_bthdcd(
+   i0,
+   i1,
+   i2,
+   s_neg,
+   s_x,
+   s_x2
+);
+   input   i0;
+   input   i1;
+   input   i2;
+   output  s_neg;
+   output  s_x;
+   output  s_x2;
+
+   //  ATTRIBUTE btr_name   OF tri_fu_mul_bthdcd          : ENTITY IS "tri_fu_mul_bthdcd";
+
+   wire    s_add;
+   wire    sx1_a0_b;
+   wire    sx1_a1_b;
+   wire    sx1_t;
+   wire    sx1_i;
+   wire    sx2_a0_b;
+   wire    sx2_a1_b;
+   wire    sx2_t;
+   wire    sx2_i;
+   wire    i0_b;
+   wire    i1_b;
+   wire    i2_b;
+
+   // i0:2      booth recode table
+   //--------------------------------
+   // 000  add  sh1=0 sh2=0  sub_adj=0
+   // 001  add  sh1=1 sh2=0  sub_adj=0
+   // 010  add  sh1=1 sh2=0  sub_adj=0
+   // 011  add  sh1=0 sh2=1  sub_adj=0
+   // 100  sub  sh1=0 sh2=1  sub_adj=1
+   // 101  sub  sh1=1 sh2=0  sub_adj=1
+   // 110  sub  sh1=1 sh2=0  sub_adj=1
+   // 111  sub  sh1=0 sh2=0  sub_adj=0
+
+   // logically correct
+   //----------------------------------
+   //  s_neg <= (i0);
+   //  s_x   <= (       not i1 and     i2) or (           i1 and not i2);
+   //  s_x2  <= (i0 and not i1 and not i2) or (not i0 and i1 and     i2);
+
+   assign i0_b = (~(i0));
+   assign i1_b = (~(i1));
+   assign i2_b = (~(i2));
+
+   assign s_add = (~(i0));
+   assign s_neg = (~(s_add));
+
+   assign sx1_a0_b = (~(i1_b & i2));
+   assign sx1_a1_b = (~(i1 & i2_b));
+   assign sx1_t = (~(sx1_a0_b & sx1_a1_b));
+   assign sx1_i = (~(sx1_t));
+   assign s_x = (~(sx1_i));
+
+   assign sx2_a0_b = (~(i0 & i1_b & i2_b));
+   assign sx2_a1_b = (~(i0_b & i1 & i2));
+   assign sx2_t = (~(sx2_a0_b & sx2_a1_b));
+   assign sx2_i = (~(sx2_t));
+   assign s_x2 = (~(sx2_i));
+
+endmodule

rel/src/verilog/trilib/tri_fu_mul_bthmux.v

@@ -0,0 +1,66 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILE NAME    :  tri_fu_mul_bthdcd.vhdl
+// *! DESCRIPTION  :  Booth Decode
+// *!****************************************************************
+
+   `include "tri_a2o.vh"
+
+module tri_fu_mul_bthmux(
+   x,
+   sneg,
+   sx,
+   sx2,
+   right,
+   left,
+   q
+);
+   input   x;
+   input   sneg;		// do not flip the input (add)
+   input   sx;		// shift by 1
+   input   sx2;		// shift by 2
+   input   right;		// bit from the right (lsb)
+   output  left;		// bit from the left
+   output  q;		// final output
+
+   wire    center;
+   wire    q_b;
+
+   assign center = x ^ sneg;
+
+   assign left = center;		//output-- rename, no gate
+
+   assign q_b = (~((sx & center) | (sx2 & right)));
+
+   assign q = (~q_b);		// output--
+
+endmodule

rel/src/verilog/trilib/tri_fu_mul_bthrow.v

@@ -0,0 +1,673 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+// *!****************************************************************
+// *! FILE NAME    :  tri_fu_mul_bthrow.vhdl
+// *! DESCRIPTION  :  Booth Decode
+// *!****************************************************************
+
+module tri_fu_mul_bthrow(
+   x,
+   s_neg,
+   s_x,
+   s_x2,
+   hot_one,
+   q
+);
+   input [0:53]  x;
+   input         s_neg;		// negate the row
+   input         s_x;		// shift by 1
+   input         s_x2;		// shift by 2
+   output        hot_one;		// lsb term for row below
+   output [0:54] q;		// final output
+
+   // ENTITY
+
+
+   parameter     tiup = 1'b1;
+   parameter     tidn = 1'b0;
+
+   wire [0:54]   left;
+   wire          unused;
+
+   assign unused = left[0];		// dangling pin from edge bit
+
+   ////###############################################################
+   //# A row of the repeated part of the booth_mux row
+   ////###############################################################
+
+   tri_fu_mul_bthmux u00(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(tidn),		//i--  ********
+      .right(left[1]),		//i--  [n+1]
+      .left(left[0]),		//o--  [n]
+      .q(q[0])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u01(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[0]),		//i--  [n-1]
+      .right(left[2]),		//i--  [n+1]
+      .left(left[1]),		//o--  [n]
+      .q(q[1])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u02(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[1]),		//i--
+      .right(left[3]),		//i--
+      .left(left[2]),		//o--
+      .q(q[2])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u03(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[2]),		//i--
+      .right(left[4]),		//i--
+      .left(left[3]),		//o--
+      .q(q[3])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u04(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[3]),		//i--
+      .right(left[5]),		//i--
+      .left(left[4]),		//o--
+      .q(q[4])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u05(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[4]),		//i--
+      .right(left[6]),		//i--
+      .left(left[5]),		//o--
+      .q(q[5])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u06(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[5]),		//i--
+      .right(left[7]),		//i--
+      .left(left[6]),		//o--
+      .q(q[6])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u07(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[6]),		//i--
+      .right(left[8]),		//i--
+      .left(left[7]),		//o--
+      .q(q[7])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u08(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[7]),		//i--
+      .right(left[9]),		//i--
+      .left(left[8]),		//o--
+      .q(q[8])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u09(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[8]),		//i--
+      .right(left[10]),		//i--
+      .left(left[9]),		//o--
+      .q(q[9])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u10(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[9]),		//i--
+      .right(left[11]),		//i--
+      .left(left[10]),		//o--
+      .q(q[10])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u11(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[10]),		//i--
+      .right(left[12]),		//i--
+      .left(left[11]),		//o--
+      .q(q[11])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u12(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[11]),		//i--
+      .right(left[13]),		//i--
+      .left(left[12]),		//o--
+      .q(q[12])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u13(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[12]),		//i--
+      .right(left[14]),		//i--
+      .left(left[13]),		//o--
+      .q(q[13])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u14(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[13]),		//i--
+      .right(left[15]),		//i--
+      .left(left[14]),		//o--
+      .q(q[14])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u15(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[14]),		//i--
+      .right(left[16]),		//i--
+      .left(left[15]),		//o--
+      .q(q[15])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u16(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[15]),		//i--
+      .right(left[17]),		//i--
+      .left(left[16]),		//o--
+      .q(q[16])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u17(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[16]),		//i--
+      .right(left[18]),		//i--
+      .left(left[17]),		//o--
+      .q(q[17])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u18(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[17]),		//i--
+      .right(left[19]),		//i--
+      .left(left[18]),		//o--
+      .q(q[18])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u19(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[18]),		//i--
+      .right(left[20]),		//i--
+      .left(left[19]),		//o--
+      .q(q[19])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u20(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[19]),		//i--
+      .right(left[21]),		//i--
+      .left(left[20]),		//o--
+      .q(q[20])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u21(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[20]),		//i--
+      .right(left[22]),		//i--
+      .left(left[21]),		//o--
+      .q(q[21])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u22(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[21]),		//i--
+      .right(left[23]),		//i--
+      .left(left[22]),		//o--
+      .q(q[22])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u23(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[22]),		//i--
+      .right(left[24]),		//i--
+      .left(left[23]),		//o--
+      .q(q[23])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u24(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[23]),		//i--
+      .right(left[25]),		//i--
+      .left(left[24]),		//o--
+      .q(q[24])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u25(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[24]),		//i--
+      .right(left[26]),		//i--
+      .left(left[25]),		//o--
+      .q(q[25])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u26(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[25]),		//i--
+      .right(left[27]),		//i--
+      .left(left[26]),		//o--
+      .q(q[26])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u27(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[26]),		//i--
+      .right(left[28]),		//i--
+      .left(left[27]),		//o--
+      .q(q[27])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u28(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[27]),		//i--
+      .right(left[29]),		//i--
+      .left(left[28]),		//o--
+      .q(q[28])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u29(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[28]),		//i--
+      .right(left[30]),		//i--
+      .left(left[29]),		//o--
+      .q(q[29])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u30(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[29]),		//i--
+      .right(left[31]),		//i--
+      .left(left[30]),		//o--
+      .q(q[30])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u31(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[30]),		//i--
+      .right(left[32]),		//i--
+      .left(left[31]),		//o--
+      .q(q[31])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u32(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[31]),		//i--
+      .right(left[33]),		//i--
+      .left(left[32]),		//o--
+      .q(q[32])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u33(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[32]),		//i--
+      .right(left[34]),		//i--
+      .left(left[33]),		//o--
+      .q(q[33])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u34(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[33]),		//i--
+      .right(left[35]),		//i--
+      .left(left[34]),		//o--
+      .q(q[34])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u35(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[34]),		//i--
+      .right(left[36]),		//i--
+      .left(left[35]),		//o--
+      .q(q[35])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u36(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[35]),		//i--
+      .right(left[37]),		//i--
+      .left(left[36]),		//o--
+      .q(q[36])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u37(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[36]),		//i--
+      .right(left[38]),		//i--
+      .left(left[37]),		//o--
+      .q(q[37])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u38(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[37]),		//i--
+      .right(left[39]),		//i--
+      .left(left[38]),		//o--
+      .q(q[38])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u39(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[38]),		//i--
+      .right(left[40]),		//i--
+      .left(left[39]),		//o--
+      .q(q[39])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u40(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[39]),		//i--
+      .right(left[41]),		//i--
+      .left(left[40]),		//o--
+      .q(q[40])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u41(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[40]),		//i--
+      .right(left[42]),		//i--
+      .left(left[41]),		//o--
+      .q(q[41])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u42(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[41]),		//i--
+      .right(left[43]),		//i--
+      .left(left[42]),		//o--
+      .q(q[42])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u43(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[42]),		//i--
+      .right(left[44]),		//i--
+      .left(left[43]),		//o--
+      .q(q[43])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u44(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[43]),		//i--
+      .right(left[45]),		//i--
+      .left(left[44]),		//o--
+      .q(q[44])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u45(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[44]),		//i--
+      .right(left[46]),		//i--
+      .left(left[45]),		//o--
+      .q(q[45])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u46(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[45]),		//i--
+      .right(left[47]),		//i--
+      .left(left[46]),		//o--
+      .q(q[46])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u47(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[46]),		//i--
+      .right(left[48]),		//i--
+      .left(left[47]),		//o--
+      .q(q[47])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u48(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[47]),		//i--
+      .right(left[49]),		//i--
+      .left(left[48]),		//o--
+      .q(q[48])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u49(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[48]),		//i--
+      .right(left[50]),		//i--
+      .left(left[49]),		//o--
+      .q(q[49])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u50(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[49]),		//i--
+      .right(left[51]),		//i--
+      .left(left[50]),		//o--
+      .q(q[50])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u51(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[50]),		//i--
+      .right(left[52]),		//i--
+      .left(left[51]),		//o--
+      .q(q[51])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u52(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[51]),		//i--
+      .right(left[53]),		//i--
+      .left(left[52]),		//o--
+      .q(q[52])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u53(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[52]),		//i--
+      .right(left[54]),		//i--
+      .left(left[53]),		//o--
+      .q(q[53])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u54(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[53]),		//i--
+      .right(s_neg),		//i--
+      .left(left[54]),		//o--
+      .q(q[54])		//o--
+   );
+
+   // For negate -A = !A + 1 ... this term is the plus 1.
+   // this has same bit weight as LSB, so it jumps down a row to free spot in compressor tree.
+
+   assign hot_one = (s_neg & (s_x | s_x2));
+
+endmodule

rel/src/verilog/trilib/tri_fu_tblmul_bthdcd.v

@@ -0,0 +1,112 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILE NAME    :  tri_fu_tblmul_bthdcd.vhdl
+// *! DESCRIPTION  :  Booth Decode
+// *!****************************************************************
+
+   `include "tri_a2o.vh"
+
+module tri_fu_tblmul_bthdcd(
+   i0,
+   i1,
+   i2,
+   s_neg,
+   s_x,
+   s_x2
+);
+   input   i0;
+   input   i1;
+   input   i2;
+   output  s_neg;
+   output  s_x;
+   output  s_x2;
+
+   wire    s_add;
+   wire    sx1_a0_b;
+   wire    sx1_a1_b;
+   wire    sx1_t;
+   wire    sx1_i;
+   wire    sx2_a0_b;
+   wire    sx2_a1_b;
+   wire    sx2_t;
+   wire    sx2_i;
+   wire    i0_b;
+   wire    i1_b;
+   wire    i2_b;
+
+
+   ////    -- 000  add  sh1=0 sh2=0  sub_adj=0
+   ////    -- 001  add  sh1=1 sh2=0  sub_adj=0
+   ////    -- 010  add  sh1=1 sh2=0  sub_adj=0
+   ////    -- 011  add  sh1=0 sh2=1  sub_adj=0
+   ////    -- 100  sub  sh1=0 sh2=1  sub_adj=1
+   ////    -- 101  sub  sh1=1 sh2=0  sub_adj=1
+   ////    -- 110  sub  sh1=1 sh2=0  sub_adj=1
+   ////    -- 111  sub  sh1=0 sh2=0  sub_adj=0
+   ////
+   ////    s_neg    <= (     i0                       );
+   ////
+   ////    s_x      <= (            not i1 and     i2 ) or
+   ////                (                i1 and not i2 );
+   ////    s_x2     <= (     i0 and not i1 and not i2 ) or
+   ////                ( not i0 and     i1 and     i2 );
+   ////
+   ////    sub_adj  <= i0 and not( i1 and i2 );
+   ////
+
+   // logically correct
+   //----------------------------------
+   //  s_neg <= (i0);
+   //  s_x   <= (       not i1 and     i2) or (           i1 and not i2);
+   //  s_x2  <= (i0 and not i1 and not i2) or (not i0 and i1 and     i2);
+
+   assign i0_b = (~(i0));
+   assign i1_b = (~(i1));
+   assign i2_b = (~(i2));
+
+   assign s_add = (~(i0));
+   assign s_neg = (~(s_add));
+
+   assign sx1_a0_b = (~(i1_b & i2));
+   assign sx1_a1_b = (~(i1 & i2_b));
+   assign sx1_t = (~(sx1_a0_b & sx1_a1_b));
+   assign sx1_i = (~(sx1_t));
+   assign s_x = (~(sx1_i));
+
+   assign sx2_a0_b = (~(i0 & i1_b & i2_b));
+   assign sx2_a1_b = (~(i0_b & i1 & i2));
+   assign sx2_t = (~(sx2_a0_b & sx2_a1_b));
+   assign sx2_i = (~(sx2_t));
+   assign s_x2 = (~(sx2_i));
+
+
+endmodule

rel/src/verilog/trilib/tri_fu_tblmul_bthrow.v

@@ -0,0 +1,248 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+   `include "tri_a2o.vh"
+
+module tri_fu_tblmul_bthrow(
+   x,
+   s_neg,
+   s_x,
+   s_x2,
+   q
+);
+
+   input [0:15]  x;		//
+   input         s_neg;		// negate the row
+   input         s_x;		// shift by 1
+   input         s_x2;		// shift by 2
+   output [0:16] q;		// final output
+
+   // ENTITY
+
+
+   parameter     tiup = 1'b1;
+   parameter     tidn = 1'b0;
+
+   wire [0:16]   left;
+   wire          unused;
+
+   ////################################################################
+   ////# A row of the repeated part of the booth_mux row
+   ////################################################################
+
+   assign unused = left[0];
+
+   tri_fu_mul_bthmux u00(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(tidn),		//i--  ********
+      .left(left[0]),		//o--  [n]
+      .right(left[1]),		//i--  [n+1]
+      .q(q[0])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u01(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[0]),		//i--  [n-1]
+      .left(left[1]),		//o--  [n]
+      .right(left[2]),		//i--  [n+1]
+      .q(q[1])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u02(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[1]),		//i--
+      .left(left[2]),		//o--
+      .right(left[3]),		//i--
+      .q(q[2])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u03(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[2]),		//i--
+      .left(left[3]),		//o--
+      .right(left[4]),		//i--
+      .q(q[3])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u04(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[3]),		//i--
+      .left(left[4]),		//o--
+      .right(left[5]),		//i--
+      .q(q[4])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u05(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[4]),		//i--
+      .left(left[5]),		//o--
+      .right(left[6]),		//i--
+      .q(q[5])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u06(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[5]),		//i--
+      .left(left[6]),		//o--
+      .right(left[7]),		//i--
+      .q(q[6])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u07(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[6]),		//i--
+      .left(left[7]),		//o--
+      .right(left[8]),		//i--
+      .q(q[7])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u08(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[7]),		//i--
+      .left(left[8]),		//o--
+      .right(left[9]),		//i--
+      .q(q[8])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u09(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[8]),		//i--
+      .left(left[9]),		//o--
+      .right(left[10]),		//i--
+      .q(q[9])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u10(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[9]),		//i--
+      .left(left[10]),		//o--
+      .right(left[11]),		//i--
+      .q(q[10])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u11(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[10]),		//i--
+      .left(left[11]),		//o--
+      .right(left[12]),		//i--
+      .q(q[11])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u12(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[11]),		//i--
+      .left(left[12]),		//o--
+      .right(left[13]),		//i--
+      .q(q[12])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u13(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[12]),		//i--
+      .left(left[13]),		//o--
+      .right(left[14]),		//i--
+      .q(q[13])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u14(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[13]),		//i--
+      .left(left[14]),		//o--
+      .right(left[15]),		//i--
+      .q(q[14])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u15(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[14]),		//i--
+      .left(left[15]),		//o--
+      .right(left[16]),		//i--
+      .q(q[15])		//o--
+   );
+
+
+   tri_fu_mul_bthmux u16(
+      .sneg(s_neg),		//i--
+      .sx(s_x),		//i--
+      .sx2(s_x2),		//i--
+      .x(x[15]),		//i--
+      .left(left[16]),		//o--
+      .right(s_neg),		//i--
+      .q(q[16])		//o--
+   );
+
+endmodule

rel/src/verilog/trilib/tri_inv.v

@@ -0,0 +1,61 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_inv.v
+// *! DESCRIPTION : INVERTER gate
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_inv(
+   y,
+   a
+);
+   parameter                      WIDTH = 1;
+   parameter                      BTR = "INV_X2M_NONE";  //Specify full BTR name, else let tool select
+   output [0:WIDTH-1]  y;
+   input [0:WIDTH-1]   a;
+
+   // tri_nand2
+   genvar 	       i;
+
+   generate
+      begin : t
+	 for (i = 0; i < WIDTH; i = i + 1)
+	   begin : w
+
+	      not I0(y[i], a[i]);
+
+	   end // block: w
+      end
+
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_inv_nlats.v

@@ -0,0 +1,120 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_inv_nlats.v
+// *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with inv gate in front
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_inv_nlats(
+   vd,
+   gd,
+   lclk,
+   d1clk,
+   d2clk,
+   scanin,
+   scanout,
+   d,
+   qb
+);
+   parameter                      OFFSET = 0;
+   parameter                      WIDTH = 1;
+   parameter                      INIT = 0;
+   parameter                      L2_LATCH_TYPE = 2;            //L2_LATCH_TYPE = slave_latch;
+                                                                //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
+   parameter                      SYNTHCLONEDLATCH = "";
+   parameter                      BTR = "NLI0001_X1_A12TH";
+   parameter                      NEEDS_SRESET = 1;		// for inferred latches
+   parameter                      DOMAIN_CROSSING = 0;
+
+   inout                          vd;
+   inout                          gd;
+   input [0:`NCLK_WIDTH-1]        lclk;
+   input                          d1clk;
+   input                          d2clk;
+   input [OFFSET:OFFSET+WIDTH-1]  scanin;
+   output [OFFSET:OFFSET+WIDTH-1] scanout;
+   input [OFFSET:OFFSET+WIDTH-1]  d;
+   output [OFFSET:OFFSET+WIDTH-1] qb;
+
+   // tri_inv_nlats
+
+   parameter [0:WIDTH-1]          init_v = INIT;
+   parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};
+
+   generate
+   begin
+      wire                          sreset;
+      wire [0:WIDTH-1]              int_din;
+      reg [0:WIDTH-1]               int_dout;
+      wire [0:WIDTH-1]              vact;
+      wire [0:WIDTH-1]              vact_b;
+      wire [0:WIDTH-1]              vsreset;
+      wire [0:WIDTH-1]              vsreset_b;
+      wire [0:WIDTH-1]              vthold;
+      wire [0:WIDTH-1]              vthold_b;
+      wire [0:WIDTH-1]              din;
+       (* analysis_not_referenced="true" *)
+      wire                          unused;
+
+      if (NEEDS_SRESET == 1)
+      begin : rst
+        assign sreset = lclk[1];
+      end
+      if (NEEDS_SRESET != 1)
+      begin : no_rst
+        assign sreset = 1'b0;
+      end
+
+      assign vsreset = {WIDTH{sreset}};
+      assign vsreset_b = {WIDTH{~sreset}};
+      assign din = d;		// Output is inverted, so don't invert here
+      assign int_din = (vsreset_b & din) | (vsreset & init_v);
+
+      assign vact = {WIDTH{d1clk}};
+      assign vact_b = {WIDTH{~d1clk}};
+
+      assign vthold_b = {WIDTH{d2clk}};
+      assign vthold = {WIDTH{~d2clk}};
+
+
+      always @(posedge lclk[0])
+      begin: l
+        int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
+      end
+      assign qb = (~int_dout);
+      assign scanout = ZEROS;
+
+      assign unused = | {vd, gd, lclk, scanin};
+   end
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_iuq_cpl_arr.v

@@ -0,0 +1,333 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 fs / 1 fs
+
+// *!****************************************************************
+// *! FILENAME    : tri_iuq_cpl_arr.v
+// *! DESCRIPTION : iuq completion array (fpga model)
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, force_t, thold_0_b, sg_0, scan_in, scan_out, re0, ra0, do0, re1, ra1, do1, we0, wa0, di0, we1, wa1, di1, perr);
+   parameter                    ADDRESSABLE_PORTS = 64;         // number of addressable register in this array
+   parameter                    ADDRESSBUS_WIDTH = 6;		// width of the bus to address all ports (2^ADDRESSBUS_WIDTH >= addressable_ports)
+   parameter                    PORT_BITWIDTH = 64;		// bitwidth of ports
+   parameter                    LATCHED_READ = 1'b1;
+   parameter                    LATCHED_READ_DATA = 1'b1;
+   parameter                    LATCHED_WRITE = 1'b1;
+
+   // POWER PINS
+   (* ground_pin=1 *)
+   inout                        gnd;
+   (* power_pin=1 *)
+   inout                        vdd;
+
+   input [0:`NCLK_WIDTH-1]      nclk;
+
+   //-------------------------------------------------------------------
+   // Pervasive
+   //-------------------------------------------------------------------
+   input                        delay_lclkr_dc;
+   input                        mpw1_dc_b;
+   input                        mpw2_dc_b;
+   input                        force_t;
+   input                        thold_0_b;
+   input                        sg_0;
+   input                        scan_in;
+   output                       scan_out;
+
+   //-------------------------------------------------------------------
+   // Functional
+   //-------------------------------------------------------------------
+   input                        re0;
+   input [0:ADDRESSBUS_WIDTH-1] ra0;
+   output [0:PORT_BITWIDTH-1]   do0;
+
+   input                        re1;
+   input [0:ADDRESSBUS_WIDTH-1] ra1;
+   output [0:PORT_BITWIDTH-1]   do1;
+
+   input                        we0;
+   input [0:ADDRESSBUS_WIDTH-1] wa0;
+   input [0:PORT_BITWIDTH-1]    di0;
+
+   input                        we1;
+   input [0:ADDRESSBUS_WIDTH-1] wa1;
+   input [0:PORT_BITWIDTH-1]    di1;
+
+   output                       perr;
+
+   reg                          re0_q;
+   reg                          we0_q;
+   reg  [0:ADDRESSBUS_WIDTH-1]  ra0_q;
+   reg  [0:ADDRESSBUS_WIDTH-1]  wa0_q;
+   reg  [0:PORT_BITWIDTH-1]     do0_q;
+   wire [0:PORT_BITWIDTH-1]     do0_d;
+   reg  [0:PORT_BITWIDTH-1]     di0_q;
+
+   reg                          re1_q;
+   reg                          we1_q;
+   reg  [0:ADDRESSBUS_WIDTH-1]  ra1_q;
+   reg  [0:ADDRESSBUS_WIDTH-1]  wa1_q;
+   reg  [0:PORT_BITWIDTH-1]     do1_q;
+   wire [0:PORT_BITWIDTH-1]     do1_d;
+   reg  [0:PORT_BITWIDTH-1]     di1_q;
+
+   wire                         correct_clk;
+   wire                         reset;
+   wire                         reset_hi;
+   reg                          reset_q;
+
+   wire [0:PORT_BITWIDTH-1]     dout0;		//std
+   wire                         wen0;		//std
+   wire [0:ADDRESSBUS_WIDTH-1]  addr_w0;        //std
+   wire [0:ADDRESSBUS_WIDTH-1]  addr_r0;	//std
+   wire [0:PORT_BITWIDTH-1]     din0;		//std
+
+   wire [0:PORT_BITWIDTH-1]     dout1;		//std
+   wire                         wen1;		//std
+   wire [0:ADDRESSBUS_WIDTH-1]  addr_w1;	//std
+   wire [0:ADDRESSBUS_WIDTH-1]  addr_r1;	//std
+   wire [0:PORT_BITWIDTH-1]     din1;		//std
+
+   reg                          we1_latch_q;
+   reg [0:ADDRESSBUS_WIDTH-1]   wa1_latch_q;
+   reg [0:PORT_BITWIDTH-1]      di1_latch_q;
+
+
+   (* analysis_not_referenced="true" *)
+   wire 								  unused_SPO_0;
+   (* analysis_not_referenced="true" *)
+   wire 								  unused_SPO_1;
+
+
+   generate
+      assign reset = nclk[1];
+      assign correct_clk = nclk[0];
+
+      assign reset_hi = reset;
+
+
+      // Slow Latches (nclk)
+
+      always @(posedge correct_clk or posedge reset)
+      begin: slatch
+         begin
+            if (reset == 1'b1)
+               we1_latch_q <= 1'b0;
+            else
+            begin
+               we1_latch_q <= we1_q;
+               wa1_latch_q <= wa1_q;
+               di1_latch_q <= di1_q;
+            end
+         end
+      end
+
+
+      // repower latches for resets
+      always @(posedge correct_clk)
+      begin: rlatch
+         reset_q <= reset_hi;
+      end
+
+      // need to select which array to write based on the lowest order bit of the address which will indicate odd or even itag
+      // when both we0 and we1 are both asserted it is assumed that the low order bit of wa0 will not be equal to the low order
+      // bit of wa1
+      assign addr_w0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
+      assign wen0    = (wa0_q[ADDRESSBUS_WIDTH-1]) ?  we1_q  : we0_q;
+      assign din0    = (wa0_q[ADDRESSBUS_WIDTH-1]) ?  di1_q  : di0_q;
+      assign addr_r0 = (ra0_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
+
+      assign addr_w1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
+      assign wen1    = (wa1_q[ADDRESSBUS_WIDTH-1]) ?  we1_q  : we0_q;
+      assign din1    = (wa1_q[ADDRESSBUS_WIDTH-1]) ?  di1_q  : di0_q;
+      assign addr_r1 = (ra1_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
+
+      assign perr = 1'b0;
+
+      begin : xhdl0
+         genvar i;
+         for (i = 0; i <= PORT_BITWIDTH - 1; i = i + 1)
+         begin : array_gen0
+            RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D0(
+               .DPO(dout0[i]),
+               .SPO(unused_SPO_0),
+
+               .A0(addr_w0[0]),
+               .A1(addr_w0[1]),
+               .A2(addr_w0[2]),
+               .A3(addr_w0[3]),
+               .A4(addr_w0[4]),
+               .A5(addr_w0[5]),
+               .D(din0[i]),
+               .DPRA0(addr_r0[0]),
+               .DPRA1(addr_r0[1]),
+               .DPRA2(addr_r0[2]),
+               .DPRA3(addr_r0[3]),
+               .DPRA4(addr_r0[4]),
+               .DPRA5(addr_r0[5]),
+               .WCLK(correct_clk),
+               .WE(wen0)
+            );
+
+            RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D1(
+               .DPO(dout1[i]),
+               .SPO(unused_SPO_1),
+
+               .A0(addr_w1[0]),
+               .A1(addr_w1[1]),
+               .A2(addr_w1[2]),
+               .A3(addr_w1[3]),
+               .A4(addr_w1[4]),
+               .A5(addr_w1[5]),
+               .D(din1[i]),
+               .DPRA0(addr_r1[0]),
+               .DPRA1(addr_r1[1]),
+               .DPRA2(addr_r1[2]),
+               .DPRA3(addr_r1[3]),
+               .DPRA4(addr_r1[4]),
+               .DPRA5(addr_r1[5]),
+               .WCLK(correct_clk),
+               .WE(wen1)
+            );
+
+
+         end
+      end
+
+      assign do0_d = (ra0_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0;
+      assign do1_d = (ra1_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0;
+      assign do0 = do0_q;
+      assign do1 = do1_q;
+
+      if (LATCHED_READ == 1'b0)
+      begin : read_latched_false
+         always @(*)
+         begin
+            re0_q <= re0;
+            ra0_q <= ra0;
+            re1_q <= re1;
+            ra1_q <= ra1;
+         end
+      end
+      if (LATCHED_READ == 1'b1)
+      begin : read_latched_true
+         always @(posedge correct_clk)
+         begin: read_latches
+            if (correct_clk == 1'b1)
+            begin
+               if (reset_q == 1'b1)
+               begin
+                  re0_q <= 1'b0;
+                  ra0_q <= {ADDRESSBUS_WIDTH{1'b0}};
+                  re1_q <= 1'b0;
+                  ra1_q <= {ADDRESSBUS_WIDTH{1'b0}};
+               end
+               else
+               begin
+                  re0_q <= re0;
+                  ra0_q <= ra0;
+                  re1_q <= re1;
+                  ra1_q <= ra1;
+               end
+            end
+         end
+      end
+
+      if (LATCHED_WRITE == 1'b0)
+      begin : write_latched_false
+         always @(*)
+         begin
+            we0_q <= we0;
+            wa0_q <= wa0;
+            di0_q <= di0;
+            we1_q <= we1;
+            wa1_q <= wa1;
+            di1_q <= di1;
+         end
+      end
+      if (LATCHED_WRITE == 1'b1)
+      begin : write_latched_true
+         always @(posedge correct_clk)
+         begin: write_latches
+            if (correct_clk == 1'b1)
+            begin
+               if (reset_q == 1'b1)
+               begin
+                  we0_q <= 1'b0;
+                  wa0_q <= {ADDRESSBUS_WIDTH{1'b0}};
+                  di0_q <= {PORT_BITWIDTH{1'b0}};
+                  we1_q <= 1'b0;
+                  wa1_q <= {ADDRESSBUS_WIDTH{1'b0}};
+                  di1_q <= {PORT_BITWIDTH{1'b0}};
+               end
+               else
+               begin
+                  we0_q <= we0;
+                  wa0_q <= wa0;
+                  di0_q <= di0;
+                  we1_q <= we1;
+                  wa1_q <= wa1;
+                  di1_q <= di1;
+               end
+            end
+         end
+      end
+
+      if (LATCHED_READ_DATA == 1'b0)
+      begin : read_data_latched_false
+         always @(*)
+         begin
+            do0_q <= do0_d;
+            do1_q <= do1_d;
+         end
+      end
+      if (LATCHED_READ_DATA == 1'b1)
+      begin : read_data_latched_true
+         always @(posedge correct_clk)
+         begin: read_data_latches
+            if (correct_clk == 1'b1)
+            begin
+               if (reset_q == 1'b1)
+               begin
+                  do0_q <= {PORT_BITWIDTH{1'b0}};
+                  do1_q <= {PORT_BITWIDTH{1'b0}};
+               end
+               else
+               begin
+                  do0_q <= do0_d;
+                  do1_q <= do1_d;
+               end
+            end
+         end
+      end
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_lcbcntl_array_mac.v

@@ -0,0 +1,83 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_lcbcntl_array_mac.v
+// *! DESCRIPTION : Used to generate control signals for LCBs
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_lcbcntl_array_mac(
+   vdd,
+   gnd,
+   sg,
+   nclk,
+   scan_in,
+   scan_diag_dc,
+   thold,
+   clkoff_dc_b,
+   delay_lclkr_dc,
+   act_dis_dc,
+   d_mode_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   scan_out
+);
+   inout        vdd;
+   inout        gnd;
+   input        sg;
+   input [0:`NCLK_WIDTH-1] nclk;
+   input        scan_in;
+   input        scan_diag_dc;
+   input        thold;
+   output       clkoff_dc_b;
+   output [0:4] delay_lclkr_dc;
+   output       act_dis_dc;
+   output       d_mode_dc;
+   output [0:4] mpw1_dc_b;
+   output       mpw2_dc_b;
+   output       scan_out;
+
+   // tri_lcbcntl_array_mac
+
+    (* analysis_not_referenced="true" *)
+   wire         unused;
+
+   assign clkoff_dc_b = 1'b1;
+   assign delay_lclkr_dc = 5'b00000;
+   assign act_dis_dc = 1'b0;
+   assign d_mode_dc = 1'b0;
+   assign mpw1_dc_b = 5'b11111;
+   assign mpw2_dc_b = 1'b1;
+   assign scan_out = 1'b0;
+
+   assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold;
+endmodule

rel/src/verilog/trilib/tri_lcbcntl_mac.v

@@ -0,0 +1,83 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_lcbcntl_mac.v
+// *! DESCRIPTION : Used to generate control signals for LCBs
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_lcbcntl_mac(
+   vdd,
+   gnd,
+   sg,
+   nclk,
+   scan_in,
+   scan_diag_dc,
+   thold,
+   clkoff_dc_b,
+   delay_lclkr_dc,
+   act_dis_dc,
+   d_mode_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   scan_out
+);
+   inout        vdd;
+   inout        gnd;
+   input        sg;
+   input [0:`NCLK_WIDTH-1] nclk;
+   input        scan_in;
+   input        scan_diag_dc;
+   input        thold;
+   output       clkoff_dc_b;
+   output [0:4] delay_lclkr_dc;
+   output       act_dis_dc;
+   output       d_mode_dc;
+   output [0:4] mpw1_dc_b;
+   output       mpw2_dc_b;
+   output       scan_out;
+
+   // tri_lcbcntl_mac
+
+    (* analysis_not_referenced="true" *)
+   wire         unused;
+
+   assign clkoff_dc_b = 1'b1;
+   assign delay_lclkr_dc = 5'b00000;
+   assign act_dis_dc = 1'b0;
+   assign d_mode_dc = 1'b0;
+   assign mpw1_dc_b = 5'b11111;
+   assign mpw2_dc_b = 1'b1;
+   assign scan_out = 1'b0;
+
+   assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold;
+endmodule

rel/src/verilog/trilib/tri_lcbnd.v

@@ -0,0 +1,81 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_lcbnd.v
+// *! DESCRIPTION : Wrapper for nlat LCB - will not run in pulsed mode
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_lcbnd(
+   vd,
+   gd,
+   act,
+   delay_lclkr,
+   mpw1_b,
+   mpw2_b,
+   nclk,
+   force_t,
+   sg,
+   thold_b,
+   d1clk,
+   d2clk,
+   lclk
+);
+   parameter                      DOMAIN_CROSSING = 0;
+
+   inout      vd;
+   inout      gd;
+   input      act;
+   input      delay_lclkr;
+   input      mpw1_b;
+   input      mpw2_b;
+   input[0:`NCLK_WIDTH-1]  nclk;
+   input      force_t;
+   input      sg;
+   input      thold_b;
+   output     d1clk;
+   output     d2clk;
+   output[0:`NCLK_WIDTH-1]  lclk;
+
+   // tri_lcbnd
+   wire       gate_b;
+    (* analysis_not_referenced="true" *)
+   wire       unused;
+
+   assign unused = vd | gd | delay_lclkr | mpw1_b | mpw2_b | sg;
+
+   assign gate_b = force_t | act;
+
+   assign d1clk = gate_b;
+   assign d2clk = thold_b;
+   assign lclk = nclk;
+endmodule

rel/src/verilog/trilib/tri_lcbor.v

@@ -0,0 +1,51 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_lcbor.v
+// *! DESCRIPTION : Used to generate LCB controls
+// *!****************************************************************
+
+module tri_lcbor(clkoff_b, thold, sg, act_dis, force_t, thold_b);
+   input      clkoff_b;
+   input      thold;
+   input      sg;
+   input      act_dis;
+   output     force_t;
+   output     thold_b;
+
+   (* analysis_not_referenced="true" *)
+   wire       unused;
+
+   assign unused = clkoff_b | sg | act_dis;
+
+   assign force_t = 1'b0;
+   assign thold_b = (~thold);
+endmodule

rel/src/verilog/trilib/tri_lcbs.v

@@ -0,0 +1,67 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_lcbs.v
+// *! DESCRIPTION : Wrapper for slat LCB
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_lcbs(
+   vd,
+   gd,
+   delay_lclkr,
+   nclk,
+   force_t,
+   thold_b,
+   dclk,
+   lclk
+);
+   inout      vd;
+   inout      gd;
+   input      delay_lclkr;
+   input[0:`NCLK_WIDTH-1]  nclk;
+   input      force_t;
+   input      thold_b;
+   output     dclk;
+   output[0:`NCLK_WIDTH-1]  lclk;
+
+   //  tri_lcbs
+
+   (* analysis_not_referenced="true" *)
+   wire       unused;
+
+   assign unused = vd | gd | delay_lclkr | force_t;
+
+   // No scan chain in this methodology
+   assign dclk = thold_b;
+   assign lclk = nclk;
+endmodule

rel/src/verilog/trilib/tri_lq_rmw.v

@@ -0,0 +1,735 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+//  Description:  XU LSU Load Data Rotator
+//
+//*****************************************************************************
+
+// ##########################################################################################
+// Contents
+// 1) 16 bit Unaligned Rotate to the Right Rotator
+// 2) Little/Big Endian Support
+// ##########################################################################################
+
+`include "tri_a2o.vh"
+
+
+module tri_lq_rmw(
+   ex2_stq4_rd_stg_act,
+   ex2_stq4_rd_addr,
+   stq6_rd_data_wa,
+   stq6_rd_data_wb,
+   stq6_rd_data_wc,
+   stq6_rd_data_wd,
+   stq6_rd_data_we,
+   stq6_rd_data_wf,
+   stq6_rd_data_wg,
+   stq6_rd_data_wh,
+   stq5_stg_act,
+   stq5_arr_wren,
+   stq5_arr_wr_way,
+   stq5_arr_wr_addr,
+   stq5_arr_wr_bytew,
+   stq5_arr_wr_data,
+   stq7_byp_val_wabcd,
+   stq7_byp_val_wefgh,
+   stq7_byp_data_wabcd,
+   stq7_byp_data_wefgh,
+   stq8_byp_data_wabcd,
+   stq8_byp_data_wefgh,
+   stq_byp_val_wabcd,
+   stq_byp_val_wefgh,
+   dcarr_rd_stg_act,
+   dcarr_wr_stg_act,
+   dcarr_wr_way,
+   dcarr_wr_addr,
+   dcarr_wr_data_wabcd,
+   dcarr_wr_data_wefgh,
+   nclk,
+   vdd,
+   gnd,
+   d_mode_dc,
+   delay_lclkr_dc,
+   mpw1_dc_b,
+   mpw2_dc_b,
+   func_sl_force,
+   func_sl_thold_0_b,
+   sg_0,
+   scan_in,
+   scan_out
+);
+
+// EX2/STQ4 Read Operation
+input               ex2_stq4_rd_stg_act;
+input [52:59]       ex2_stq4_rd_addr;
+
+// Read data for Read-Modify-Write
+input [0:143]       stq6_rd_data_wa;
+input [0:143]       stq6_rd_data_wb;
+input [0:143]       stq6_rd_data_wc;
+input [0:143]       stq6_rd_data_wd;
+input [0:143]       stq6_rd_data_we;
+input [0:143]       stq6_rd_data_wf;
+input [0:143]       stq6_rd_data_wg;
+input [0:143]       stq6_rd_data_wh;
+
+// Write Data for Read-Modify-Write
+input               stq5_stg_act;
+input               stq5_arr_wren;
+input [0:7]         stq5_arr_wr_way;
+input [52:59]       stq5_arr_wr_addr;
+input [0:15]        stq5_arr_wr_bytew;
+input [0:143]       stq5_arr_wr_data;
+
+// EX4 Load Bypass Data for Read/Write Collision detected in EX2
+output [0:3]        stq7_byp_val_wabcd;
+output [0:3]        stq7_byp_val_wefgh;
+output [0:143]      stq7_byp_data_wabcd;
+output [0:143]      stq7_byp_data_wefgh;
+output [0:143]      stq8_byp_data_wabcd;
+output [0:143]      stq8_byp_data_wefgh;
+output [0:3]        stq_byp_val_wabcd;
+output [0:3]        stq_byp_val_wefgh;
+
+// Data Cache Array Write
+output [0:7]        dcarr_rd_stg_act;
+output [0:7]        dcarr_wr_stg_act;
+output [0:7]        dcarr_wr_way;
+output [52:59]      dcarr_wr_addr;
+output [0:143]      dcarr_wr_data_wabcd;
+output [0:143]      dcarr_wr_data_wefgh;
+
+(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
+input [0:`NCLK_WIDTH-1] nclk;
+inout               vdd;
+inout               gnd;
+input               d_mode_dc;
+input               delay_lclkr_dc;
+input               mpw1_dc_b;
+input               mpw2_dc_b;
+input               func_sl_force;
+input               func_sl_thold_0_b;
+input               sg_0;
+
+(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
+input               scan_in;
+(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
+output              scan_out;
+
+wire [52:59]        ex3_stq5_rd_addr_d;
+wire [52:59]        ex3_stq5_rd_addr_q;
+wire                stq6_stg_act_d;
+wire                stq6_stg_act_q;
+wire                stq7_stg_act_d;
+wire                stq7_stg_act_q;
+wire                stq6_wren_d;
+wire                stq6_wren_q;
+wire                stq7_wren_d;
+wire                stq7_wren_q;
+wire [0:7]          stq6_way_en_d;
+wire [0:7]          stq6_way_en_q;
+wire [0:7]          stq7_way_en_d;
+wire [0:7]          stq7_way_en_q;
+wire [0:7]          stq6_wr_way;
+wire [52:59]        stq6_addr_d;
+wire [52:59]        stq6_addr_q;
+wire [52:59]        stq7_addr_d;
+wire [52:59]        stq7_addr_q;
+wire [0:143]        stq6_gate_rd_data_wa;
+wire [0:143]        stq6_gate_rd_data_wb;
+wire [0:143]        stq6_gate_rd_data_wc;
+wire [0:143]        stq6_gate_rd_data_wd;
+wire [0:143]        stq6_gate_rd_data_we;
+wire [0:143]        stq6_gate_rd_data_wf;
+wire [0:143]        stq6_gate_rd_data_wg;
+wire [0:143]        stq6_gate_rd_data_wh;
+wire [0:143]        stq6_rd_data_wabcd;
+wire [0:143]        stq6_wr_data_wabcd;
+wire [0:143]        stq7_wr_data_wabcd_d;
+wire [0:143]        stq7_wr_data_wabcd_q;
+wire [0:143]        stq8_wr_data_wabcd_d;
+wire [0:143]        stq8_wr_data_wabcd_q;
+wire [0:143]        stq6_rd_data_wefgh;
+wire [0:143]        stq6_wr_data_wefgh;
+wire [0:143]        stq7_wr_data_wefgh_d;
+wire [0:143]        stq7_wr_data_wefgh_q;
+wire [0:143]        stq8_wr_data_wefgh_d;
+wire [0:143]        stq8_wr_data_wefgh_q;
+wire                ex2_stq4_addr_coll;
+wire [0:7]          ex2_stq4_way_coll;
+wire                stq6_rd_byp_val;
+wire                stq7_rd_byp_val;
+wire                stq6_wr_byp_val;
+wire                stq7_wr_byp_val;
+wire                stq5_byp_val;
+wire [0:143]        stq5_wr_bit;
+wire [0:143]        stq5_msk_bit;
+wire [0:15]         stq5_byte_en;
+wire [0:15]         stq6_byte_en_wabcd_d;
+wire [0:15]         stq6_byte_en_wabcd_q;
+wire [0:143]        stq6_wr_bit_wabcd;
+wire [0:143]        stq6_msk_bit_wabcd;
+wire [0:15]         stq6_byte_en_wefgh_d;
+wire [0:15]         stq6_byte_en_wefgh_q;
+wire [0:143]        stq6_wr_bit_wefgh;
+wire [0:143]        stq6_msk_bit_wefgh;
+wire [0:143]        stq6_stq7_byp_data_wabcd;
+wire [0:143]        stq5_byp_wr_data_wabcd;
+wire [0:143]        stq6_byp_wr_data_wabcd_d;
+wire [0:143]        stq6_byp_wr_data_wabcd_q;
+wire [0:143]        stq6_stq7_byp_data_wefgh;
+wire [0:143]        stq5_byp_wr_data_wefgh;
+wire [0:143]        stq6_byp_wr_data_wefgh_d;
+wire [0:143]        stq6_byp_wr_data_wefgh_q;
+wire [0:3]          stq7_byp_val_wabcd_d;
+wire [0:3]          stq7_byp_val_wabcd_q;
+wire [0:3]          stq7_byp_val_wefgh_d;
+wire [0:3]          stq7_byp_val_wefgh_q;
+wire [0:3]          stq_byp_val_wabcd_d;
+wire [0:3]          stq_byp_val_wabcd_q;
+wire [0:3]          stq_byp_val_wefgh_d;
+wire [0:3]          stq_byp_val_wefgh_q;
+
+parameter           stq6_stg_act_offset = 0;
+parameter           stq7_stg_act_offset = stq6_stg_act_offset + 1;
+parameter           ex3_stq5_rd_addr_offset = stq7_stg_act_offset + 1;
+parameter           stq6_wren_offset = ex3_stq5_rd_addr_offset + 8;
+parameter           stq7_wren_offset = stq6_wren_offset + 1;
+parameter           stq6_way_en_offset = stq7_wren_offset + 1;
+parameter           stq7_way_en_offset = stq6_way_en_offset + 8;
+parameter           stq6_addr_offset = stq7_way_en_offset + 8;
+parameter           stq7_addr_offset = stq6_addr_offset + 8;
+parameter           stq7_wr_data_wabcd_offset = stq7_addr_offset + 8;
+parameter           stq7_wr_data_wefgh_offset = stq7_wr_data_wabcd_offset + 144;
+parameter           stq8_wr_data_wabcd_offset = stq7_wr_data_wefgh_offset + 144;
+parameter           stq8_wr_data_wefgh_offset = stq8_wr_data_wabcd_offset + 144;
+parameter           stq6_byte_en_wabcd_offset = stq8_wr_data_wefgh_offset + 144;
+parameter           stq6_byte_en_wefgh_offset = stq6_byte_en_wabcd_offset + 16;
+parameter           stq6_byp_wr_data_wabcd_offset = stq6_byte_en_wefgh_offset + 16;
+parameter           stq6_byp_wr_data_wefgh_offset = stq6_byp_wr_data_wabcd_offset + 144;
+parameter           stq7_byp_val_wabcd_offset = stq6_byp_wr_data_wefgh_offset + 144;
+parameter           stq7_byp_val_wefgh_offset = stq7_byp_val_wabcd_offset + 4;
+parameter           stq_byp_val_wabcd_offset = stq7_byp_val_wefgh_offset + 4;
+parameter           stq_byp_val_wefgh_offset = stq_byp_val_wabcd_offset + 4;
+parameter           scan_right = stq_byp_val_wefgh_offset + 4 - 1;
+
+wire                tiup;
+wire [0:scan_right] siv;
+wire [0:scan_right] sov;
+
+assign tiup = 1'b1;
+assign ex3_stq5_rd_addr_d = ex2_stq4_rd_addr;
+assign stq6_stg_act_d     = stq5_stg_act;
+assign stq7_stg_act_d     = stq6_stg_act_q;
+assign stq6_wren_d        = stq5_arr_wren;
+assign stq7_wren_d        = stq6_wren_q;
+assign stq6_way_en_d      = stq5_arr_wr_way;
+assign stq7_way_en_d      = stq6_way_en_q;
+assign stq6_wr_way        = {8{stq6_wren_q}} & stq6_way_en_q;
+assign stq6_addr_d        = stq5_arr_wr_addr;
+assign stq7_addr_d        = stq6_addr_q;
+
+// #############################################################################################
+// Data Cache Read/Write Merge
+// #############################################################################################
+// Gate Way that is being updated
+assign stq6_gate_rd_data_wa = {144{stq6_way_en_q[0]}} & stq6_rd_data_wa;
+assign stq6_gate_rd_data_wb = {144{stq6_way_en_q[1]}} & stq6_rd_data_wb;
+assign stq6_gate_rd_data_wc = {144{stq6_way_en_q[2]}} & stq6_rd_data_wc;
+assign stq6_gate_rd_data_wd = {144{stq6_way_en_q[3]}} & stq6_rd_data_wd;
+assign stq6_gate_rd_data_we = {144{stq6_way_en_q[4]}} & stq6_rd_data_we;
+assign stq6_gate_rd_data_wf = {144{stq6_way_en_q[5]}} & stq6_rd_data_wf;
+assign stq6_gate_rd_data_wg = {144{stq6_way_en_q[6]}} & stq6_rd_data_wg;
+assign stq6_gate_rd_data_wh = {144{stq6_way_en_q[7]}} & stq6_rd_data_wh;
+
+// Merge Data Way A,B,C,D
+assign stq6_rd_data_wabcd   = stq6_gate_rd_data_wa | stq6_gate_rd_data_wb |
+                              stq6_gate_rd_data_wc | stq6_gate_rd_data_wd;
+assign stq6_wr_data_wabcd   = (stq6_wr_bit_wabcd & stq6_byp_wr_data_wabcd_q) | (stq6_msk_bit_wabcd & stq6_rd_data_wabcd);
+assign stq7_wr_data_wabcd_d = stq6_wr_data_wabcd;
+assign stq8_wr_data_wabcd_d = stq7_wr_data_wabcd_q;
+
+// Merge Data Way E,F,G,H
+assign stq6_rd_data_wefgh   = stq6_gate_rd_data_we | stq6_gate_rd_data_wf |
+                              stq6_gate_rd_data_wg | stq6_gate_rd_data_wh;
+assign stq6_wr_data_wefgh   = (stq6_wr_bit_wefgh & stq6_byp_wr_data_wefgh_q) | (stq6_msk_bit_wefgh & stq6_rd_data_wefgh);
+assign stq7_wr_data_wefgh_d = stq6_wr_data_wefgh;
+assign stq8_wr_data_wefgh_d = stq7_wr_data_wefgh_q;
+
+// #############################################################################################
+// Data Cache Write Data Bypass
+// #############################################################################################
+// Read/Write Address Match
+assign ex2_stq4_addr_coll = (ex2_stq4_rd_addr == stq6_addr_q);
+assign ex2_stq4_way_coll  = {8{ex2_stq4_addr_coll}} & stq6_wr_way;
+
+// Bypass Select Control
+assign stq6_rd_byp_val = (ex3_stq5_rd_addr_q == stq6_addr_q) & stq6_wren_q;
+assign stq7_rd_byp_val = (ex3_stq5_rd_addr_q == stq7_addr_q) & stq7_wren_q;
+assign stq6_wr_byp_val = stq6_rd_byp_val & |(stq5_arr_wr_way & stq6_way_en_q);
+assign stq7_wr_byp_val = stq7_rd_byp_val & |(stq5_arr_wr_way & stq7_way_en_q);
+assign stq5_byp_val    = stq6_wr_byp_val | stq7_wr_byp_val;
+
+// Byte Enable and Byte Mask generation
+assign stq5_wr_bit          = {9{ stq5_arr_wr_bytew}};
+assign stq5_msk_bit         = {9{~stq5_arr_wr_bytew}};
+assign stq5_byte_en         = stq5_arr_wr_bytew | {16{stq5_byp_val}};
+assign stq6_byte_en_wabcd_d = stq5_byte_en;
+assign stq6_wr_bit_wabcd    = {9{ stq6_byte_en_wabcd_q}};
+assign stq6_msk_bit_wabcd   = {9{~stq6_byte_en_wabcd_q}};
+assign stq6_byte_en_wefgh_d = stq5_byte_en;
+assign stq6_wr_bit_wefgh    = {9{ stq6_byte_en_wefgh_q}};
+assign stq6_msk_bit_wefgh   = {9{~stq6_byte_en_wefgh_q}};
+
+// Need to add bypass logic with merged data from stq6 and stq7 for Way A,B,C,D groups
+assign stq6_stq7_byp_data_wabcd = ({144{~stq6_wr_byp_val}} & stq7_wr_data_wabcd_q) | ({144{stq6_wr_byp_val}} & stq6_wr_data_wabcd);
+assign stq5_byp_wr_data_wabcd   = (stq5_wr_bit & stq5_arr_wr_data) | (stq5_msk_bit & stq6_stq7_byp_data_wabcd);
+assign stq6_byp_wr_data_wabcd_d = stq5_byp_wr_data_wabcd;
+
+// Need to add bypass logic with merged data from stq6 and stq7 for Way E,F,G,H groups
+assign stq6_stq7_byp_data_wefgh = ({144{~stq6_wr_byp_val}} & stq7_wr_data_wefgh_q) | ({144{stq6_wr_byp_val}} & stq6_wr_data_wefgh);
+assign stq5_byp_wr_data_wefgh   = (stq5_wr_bit & stq5_arr_wr_data) | (stq5_msk_bit & stq6_stq7_byp_data_wefgh);
+assign stq6_byp_wr_data_wefgh_d = stq5_byp_wr_data_wefgh;
+
+// Data that needs to be bypassed between EX2 Load Pipe Read collision detected with STQ6 Store Pipe Write
+assign stq7_byp_val_wabcd_d = {4{stq6_rd_byp_val}} & stq6_way_en_q[0:3];
+assign stq7_byp_val_wefgh_d = {4{stq6_rd_byp_val}} & stq6_way_en_q[4:7];
+//assign stq7_byp_data_wefgh = stq7_wr_data_wefgh_q;
+assign stq_byp_val_wabcd_d  = ({4{stq7_rd_byp_val}} & stq7_way_en_q[0:3]) | ({4{stq6_rd_byp_val}} & stq6_way_en_q[0:3]);
+assign stq_byp_val_wefgh_d  = ({4{stq7_rd_byp_val}} & stq7_way_en_q[4:7]) | ({4{stq6_rd_byp_val}} & stq6_way_en_q[4:7]);
+
+// #############################################################################################
+// Outputs
+// #############################################################################################
+// Data Cache Array Read ACT
+assign dcarr_rd_stg_act    = {8{ex2_stq4_rd_stg_act}} & ~ex2_stq4_way_coll;
+
+// Data Cache Array Update
+assign dcarr_wr_stg_act    = stq6_wr_way;
+assign dcarr_wr_way        = stq6_wr_way;
+assign dcarr_wr_addr       = stq6_addr_q;
+assign dcarr_wr_data_wabcd = stq6_wr_data_wabcd;
+assign dcarr_wr_data_wefgh = stq6_wr_data_wefgh;
+
+// EX4 Load Data Bypass
+assign stq7_byp_val_wabcd  = stq7_byp_val_wabcd_q;
+assign stq7_byp_val_wefgh  = stq7_byp_val_wefgh_q;
+assign stq7_byp_data_wabcd = stq7_wr_data_wabcd_q;
+assign stq7_byp_data_wefgh = stq7_wr_data_wefgh_q;
+assign stq8_byp_data_wabcd = stq8_wr_data_wabcd_q;
+assign stq8_byp_data_wefgh = stq8_wr_data_wefgh_q;
+assign stq_byp_val_wabcd   = stq_byp_val_wabcd_q;
+assign stq_byp_val_wefgh   = stq_byp_val_wefgh_q;
+
+// #############################################################################################
+// Registers
+// #############################################################################################
+tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_stg_act_latch(
+   .nclk(nclk),
+   .vd(vdd),
+   .gd(gnd),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq6_stg_act_offset]),
+   .scout(sov[stq6_stg_act_offset]),
+   .din(stq6_stg_act_d),
+   .dout(stq6_stg_act_q)
+);
+
+tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_stg_act_latch(
+   .nclk(nclk),
+   .vd(vdd),
+   .gd(gnd),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq7_stg_act_offset]),
+   .scout(sov[stq7_stg_act_offset]),
+   .din(stq7_stg_act_d),
+   .dout(stq7_stg_act_q)
+);
+
+tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_stq5_rd_addr_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[ex3_stq5_rd_addr_offset:ex3_stq5_rd_addr_offset + 8 - 1]),
+   .scout(sov[ex3_stq5_rd_addr_offset:ex3_stq5_rd_addr_offset + 8 - 1]),
+   .din(ex3_stq5_rd_addr_d),
+   .dout(ex3_stq5_rd_addr_q)
+);
+
+tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_arr_wren_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq6_wren_offset]),
+   .scout(sov[stq6_wren_offset]),
+   .din(stq6_wren_d),
+   .dout(stq6_wren_q)
+);
+
+tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_arr_wren_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq7_wren_offset]),
+   .scout(sov[stq7_wren_offset]),
+   .din(stq7_wren_d),
+   .dout(stq7_wren_q)
+);
+
+tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_way_en_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq5_stg_act),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq6_way_en_offset:stq6_way_en_offset + 8 - 1]),
+   .scout(sov[stq6_way_en_offset:stq6_way_en_offset + 8 - 1]),
+   .din(stq6_way_en_d),
+   .dout(stq6_way_en_q)
+);
+
+tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_way_en_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq6_stg_act_q),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq7_way_en_offset:stq7_way_en_offset + 8 - 1]),
+   .scout(sov[stq7_way_en_offset:stq7_way_en_offset + 8 - 1]),
+   .din(stq7_way_en_d),
+   .dout(stq7_way_en_q)
+);
+
+tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_addr_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq5_stg_act),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq6_addr_offset:stq6_addr_offset + 8 - 1]),
+   .scout(sov[stq6_addr_offset:stq6_addr_offset + 8 - 1]),
+   .din(stq6_addr_d),
+   .dout(stq6_addr_q)
+);
+
+tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_addr_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq6_stg_act_q),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq7_addr_offset:stq7_addr_offset + 8 - 1]),
+   .scout(sov[stq7_addr_offset:stq7_addr_offset + 8 - 1]),
+   .din(stq7_addr_d),
+   .dout(stq7_addr_q)
+);
+
+tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wabcd_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq6_stg_act_q),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq7_wr_data_wabcd_offset:stq7_wr_data_wabcd_offset + 144 - 1]),
+   .scout(sov[stq7_wr_data_wabcd_offset:stq7_wr_data_wabcd_offset + 144 - 1]),
+   .din(stq7_wr_data_wabcd_d),
+   .dout(stq7_wr_data_wabcd_q)
+);
+
+tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wefgh_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq6_stg_act_q),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq7_wr_data_wefgh_offset:stq7_wr_data_wefgh_offset + 144 - 1]),
+   .scout(sov[stq7_wr_data_wefgh_offset:stq7_wr_data_wefgh_offset + 144 - 1]),
+   .din(stq7_wr_data_wefgh_d),
+   .dout(stq7_wr_data_wefgh_q)
+);
+
+tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wabcd_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq7_stg_act_q),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq8_wr_data_wabcd_offset:stq8_wr_data_wabcd_offset + 144 - 1]),
+   .scout(sov[stq8_wr_data_wabcd_offset:stq8_wr_data_wabcd_offset + 144 - 1]),
+   .din(stq8_wr_data_wabcd_d),
+   .dout(stq8_wr_data_wabcd_q)
+);
+
+tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wefgh_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq7_stg_act_q),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq8_wr_data_wefgh_offset:stq8_wr_data_wefgh_offset + 144 - 1]),
+   .scout(sov[stq8_wr_data_wefgh_offset:stq8_wr_data_wefgh_offset + 144 - 1]),
+   .din(stq8_wr_data_wefgh_d),
+   .dout(stq8_wr_data_wefgh_q)
+);
+
+tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wabcd_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq5_stg_act),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq6_byte_en_wabcd_offset:stq6_byte_en_wabcd_offset + 16 - 1]),
+   .scout(sov[stq6_byte_en_wabcd_offset:stq6_byte_en_wabcd_offset + 16 - 1]),
+   .din(stq6_byte_en_wabcd_d),
+   .dout(stq6_byte_en_wabcd_q)
+);
+
+tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wefgh_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq5_stg_act),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq6_byte_en_wefgh_offset:stq6_byte_en_wefgh_offset + 16 - 1]),
+   .scout(sov[stq6_byte_en_wefgh_offset:stq6_byte_en_wefgh_offset + 16 - 1]),
+   .din(stq6_byte_en_wefgh_d),
+   .dout(stq6_byte_en_wefgh_q)
+);
+
+tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wabcd_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq5_stg_act),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq6_byp_wr_data_wabcd_offset:stq6_byp_wr_data_wabcd_offset + 144 - 1]),
+   .scout(sov[stq6_byp_wr_data_wabcd_offset:stq6_byp_wr_data_wabcd_offset + 144 - 1]),
+   .din(stq6_byp_wr_data_wabcd_d),
+   .dout(stq6_byp_wr_data_wabcd_q)
+);
+
+tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wefgh_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(stq5_stg_act),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq6_byp_wr_data_wefgh_offset:stq6_byp_wr_data_wefgh_offset + 144 - 1]),
+   .scout(sov[stq6_byp_wr_data_wefgh_offset:stq6_byp_wr_data_wefgh_offset + 144 - 1]),
+   .din(stq6_byp_wr_data_wefgh_d),
+   .dout(stq6_byp_wr_data_wefgh_q)
+);
+
+tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wabcd_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq7_byp_val_wabcd_offset:stq7_byp_val_wabcd_offset + 4 - 1]),
+   .scout(sov[stq7_byp_val_wabcd_offset:stq7_byp_val_wabcd_offset + 4 - 1]),
+   .din(stq7_byp_val_wabcd_d),
+   .dout(stq7_byp_val_wabcd_q)
+);
+
+tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wefgh_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq7_byp_val_wefgh_offset:stq7_byp_val_wefgh_offset + 4 - 1]),
+   .scout(sov[stq7_byp_val_wefgh_offset:stq7_byp_val_wefgh_offset + 4 - 1]),
+   .din(stq7_byp_val_wefgh_d),
+   .dout(stq7_byp_val_wefgh_q)
+);
+
+tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wabcd_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq_byp_val_wabcd_offset:stq_byp_val_wabcd_offset + 4 - 1]),
+   .scout(sov[stq_byp_val_wabcd_offset:stq_byp_val_wabcd_offset + 4 - 1]),
+   .din(stq_byp_val_wabcd_d),
+   .dout(stq_byp_val_wabcd_q)
+);
+
+tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wefgh_reg(
+   .vd(vdd),
+   .gd(gnd),
+   .nclk(nclk),
+   .act(tiup),
+   .force_t(func_sl_force),
+   .d_mode(d_mode_dc),
+   .delay_lclkr(delay_lclkr_dc),
+   .mpw1_b(mpw1_dc_b),
+   .mpw2_b(mpw2_dc_b),
+   .thold_b(func_sl_thold_0_b),
+   .sg(sg_0),
+   .scin(siv[stq_byp_val_wefgh_offset:stq_byp_val_wefgh_offset + 4 - 1]),
+   .scout(sov[stq_byp_val_wefgh_offset:stq_byp_val_wefgh_offset + 4 - 1]),
+   .din(stq_byp_val_wefgh_d),
+   .dout(stq_byp_val_wefgh_q)
+);
+
+assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
+assign scan_out = sov[0];
+
+endmodule

rel/src/verilog/trilib/tri_nand2.v

@@ -0,0 +1,63 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_nand2.v
+// *! DESCRIPTION : Two input NAND gate
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_nand2(
+   y,
+   a,
+   b
+);
+   parameter                      WIDTH = 1;
+   parameter                      BTR = "NAND2_X2M_NONE";  //Specify full BTR name, else let tool select
+   output [0:WIDTH-1]  y;
+   input [0:WIDTH-1]   a;
+   input [0:WIDTH-1]   b;
+
+   // tri_nand2
+   genvar 	       i;
+
+   generate
+      begin : t
+	 for (i = 0; i < WIDTH; i = i + 1)
+	   begin : w
+
+	      nand I0(y[i], a[i], b[i]);
+
+	   end // block: w
+      end
+
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_nand2_nlats.v

@@ -0,0 +1,121 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_nand2_nlats.v
+// *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with nand2 gate in front
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_nand2_nlats(
+   vd,
+   gd,
+   lclk,
+   d1clk,
+   d2clk,
+   scanin,
+   scanout,
+   a1,
+   a2,
+   qb
+);
+   parameter                      OFFSET = 0;
+   parameter                      WIDTH = 1;
+   parameter                      INIT = 0;
+   parameter                      L2_LATCH_TYPE = 2;            //L2_LATCH_TYPE = slave_latch;
+                                                                //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
+   parameter                      SYNTHCLONEDLATCH = "";
+   parameter                      BTR = "NLA0001_X1_A12TH";
+   parameter                      NEEDS_SRESET = 1;		// for inferred latches
+
+   inout                          vd;
+   inout                          gd;
+   input [0:`NCLK_WIDTH-1]        lclk;
+   input                          d1clk;
+   input                          d2clk;
+   input [OFFSET:OFFSET+WIDTH-1]  scanin;
+   output [OFFSET:OFFSET+WIDTH-1] scanout;
+   input [OFFSET:OFFSET+WIDTH-1]  a1;
+   input [OFFSET:OFFSET+WIDTH-1]  a2;
+   output [OFFSET:OFFSET+WIDTH-1] qb;
+
+   // tri_nand2_nlats
+
+   parameter [0:WIDTH-1]          init_v = INIT;
+   parameter [0:WIDTH-1]          ZEROS = {WIDTH{1'b0}};
+
+   generate
+   begin
+      wire                          sreset;
+      wire [0:WIDTH-1]              int_din;
+      reg [0:WIDTH-1]               int_dout;
+      wire [0:WIDTH-1]              vact;
+      wire [0:WIDTH-1]              vact_b;
+      wire [0:WIDTH-1]              vsreset;
+      wire [0:WIDTH-1]              vsreset_b;
+      wire [0:WIDTH-1]              vthold;
+      wire [0:WIDTH-1]              vthold_b;
+      wire [0:WIDTH-1]              din;
+       (* analysis_not_referenced="true" *)
+      wire                          unused;
+
+      if (NEEDS_SRESET == 1)
+      begin : rst
+        assign sreset = lclk[1];
+      end
+      if (NEEDS_SRESET != 1)
+      begin : no_rst
+        assign sreset = 1'b0;
+      end
+
+      assign vsreset = {WIDTH{sreset}};
+      assign vsreset_b = {WIDTH{~sreset}};
+      assign din = a1 & a2;		// Output is inverted, so just AND2 here
+      assign int_din = (vsreset_b & din) | (vsreset & init_v);
+
+      assign vact = {WIDTH{d1clk}};
+      assign vact_b = {WIDTH{~d1clk}};
+
+      assign vthold_b = {WIDTH{d2clk}};
+      assign vthold = {WIDTH{~d2clk}};
+
+
+      always @(posedge lclk[0])
+      begin: l
+        int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
+      end
+      assign qb = (~int_dout);
+      assign scanout = ZEROS;
+
+      assign unused = | {vd, gd, lclk, scanin};
+   end
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_nand3.v

@@ -0,0 +1,66 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_nand3.v
+// *! DESCRIPTION : Three input NAND gate
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_nand3(
+   y,
+   a,
+   b,
+   c
+);
+   parameter                      WIDTH = 1;
+   parameter                      BTR = "NAND3_X2M_NONE";  //Specify full BTR name, else let tool select
+   output [0:WIDTH-1]  y;
+   input [0:WIDTH-1]   a;
+   input [0:WIDTH-1]   b;
+   input [0:WIDTH-1]   c;
+
+   // tri_nand3
+   genvar 	       i;
+
+   generate
+      begin : t
+	 for (i = 0; i < WIDTH; i = i + 1)
+	   begin : w
+
+      	      nand I0(y[i], a[i], b[i], c[i]);
+
+
+	   end // block: w
+      end
+
+   endgenerate
+endmodule

rel/src/verilog/trilib/tri_nand4.v

@@ -0,0 +1,67 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.  
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+// 
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org. 
+
+`timescale 1 ns / 1 ns
+
+// *!****************************************************************
+// *! FILENAME    : tri_nand4.v
+// *! DESCRIPTION : Four input NAND gate
+// *!****************************************************************
+
+`include "tri_a2o.vh"
+
+module tri_nand4(
+   y,
+   a,
+   b,
+   c,
+   d
+);
+   parameter                      WIDTH = 1;
+   parameter                      BTR = "NAND4_X2M_NONE";  //Specify full BTR name, else let tool select
+   output [0:WIDTH-1]  y;
+   input [0:WIDTH-1]   a;
+   input [0:WIDTH-1]   b;
+   input [0:WIDTH-1]   c;
+   input [0:WIDTH-1]   d;
+   // tri_nand3
+   genvar 	       i;
+
+   generate
+      begin : t
+	 for (i = 0; i < WIDTH; i = i + 1)
+	   begin : w
+
+      	      nand I0(y[i], a[i], b[i], c[i], d[i]);
+
+
+	   end // block: w
+      end
+
+   endgenerate
+endmodule