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Fix uncompliant begin in generate blocks

Browse Source 
Signed-off-by: Flavien Solt <flsolt@ethz.ch>
pull/18/head
Flavien Solt 2 years ago
parent 1b044116f2
commit 9c4e14a338
84 changed files with 582 additions and 902 deletions
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3
dev/verilog/trilib/tri_128x34_4w_1r1w.v
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@ -205,8 +205,7 @@ module tri_128x34_4w_1r1w (
wire [3:0] dopb;
wire [0:scan_right] func_sov;

generate
begin
generate if(1) begin
assign tidn = 1'b0;

if (addressbus_width < ramb_base_addr)

5
dev/verilog/trilib/tri_32x70_2w_1r1w.v
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@ -270,7 +270,7 @@ assign write_enable_CD = wr_act[1] & wr_way[1];

// Read/Write Port Address Generate
generate
begin
if(1) begin
genvar t;
for (t = 0; t < ramb_base_addr; t = t + 1)
begin : rambAddrCalc
@ -296,8 +296,7 @@ assign ramb_addr_wr_rd0 = wr_addr1;
assign data_out_d = {arrA_bit0_out_q, ramb_data_p1_outA[1:34], ramb_data_p1_outB[0:34], arrC_bit0_out_q, ramb_data_p1_outC[1:34], ramb_data_p1_outD[0:34]};
assign data_out = data_out_q;

generate
begin : arr_bit0
generate if(1) begin : arr_bit0
genvar i;
for (i = 0; i <= addressable_ports - 1; i = i + 1)
begin : arr_bit0

3
dev/verilog/trilib/tri_512x162_4w_0.v
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@ -218,8 +218,7 @@ module tri_512x162_4w_0 (
wire [3:0] dopb;
wire [0:port_bitwidth*ways-1] unused_scout;

generate
begin
generate if(1) begin
assign tidn = 1'b0;

if (addressbus_width < ramb_base_addr)

2
dev/verilog/trilib/tri_64x144_1r1w.v
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@ -227,7 +227,7 @@ wire [0:scan_right] sov;
(* analysis_not_referenced="true" *)
wire unused;

generate begin
generate if(1) begin
assign tiup = 1'b1;
assign tidn = 1'b0;
assign wrt_en = {(((((port_bitwidth-1)/36)+1)*36)/9){write_enable}};

2
dev/verilog/trilib/tri_64x34_8w_1r1w.v
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@ -237,7 +237,7 @@ wire [0:35] tidn;
wire [0:scan_right] siv;
wire [0:scan_right] sov;

generate begin
generate if(1) begin

assign tiup = 1'b1;
assign tidn = 36'b0;

3
dev/verilog/trilib/tri_aoi21.v
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@ -53,8 +53,7 @@ module tri_aoi21(
genvar i;
wire [0:WIDTH-1] outA;

generate
begin : t
generate if(1) begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w


3
dev/verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v
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@ -154,8 +154,7 @@ module tri_cam_16x143_1r1w1c_matchline(
assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^
{addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]}));

generate
begin
generate if(1) begin
if (NUM_PGSIZES == 8)
begin : numpgsz8
// tie off unused signals

3
dev/verilog/trilib/tri_err_rpt.v
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@ -111,8 +111,7 @@ module tri_err_rpt(
.q_b(unused_q_b)
);

generate
begin
generate if(1) begin
// mask
if (SHARE_MASK == 1'b0) begin
assign mask_lt = mask_initv;

11
dev/verilog/trilib/tri_event_mux1t.v
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@ -92,8 +92,7 @@ module tri_event_mux1t(
// Start of event mux
//=====================================================================
// For each output bit, decode its select_bits to select the input mux it's using
generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar X;
for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
begin : decode
@ -116,15 +115,14 @@ module tri_event_mux1t(
endgenerate

// For each output bit, inMux decodes gate the selected unit event input; or event_bus_in when decode=0
generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar X;
for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
begin : inpMux

assign inMuxOut[X * EVENTS_IN + 0] = (inMuxDec[X * EVENTS_IN + 0] & event_bus_in[X]) ;

begin : xhdl1
if(1) begin : xhdl1
genvar I;
for (I = 1; I <= EVENTS_IN - 1; I = I + 1)
begin : eventSel
@ -140,8 +138,7 @@ module tri_event_mux1t(

// ORing the input mux outputs to drive each event output bit.
// Only one selected at a time by each output bit's inMux decode value.
generate
begin : xhdl5
generate if(1) begin : xhdl5
genvar X;
for (X = 0; X <= EVENTS_OUT - 1; X = X + 1)
begin : bitOutHi

3
dev/verilog/trilib/tri_inv.v
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@ -47,8 +47,7 @@ module tri_inv(
// tri_nand2
genvar i;

generate
begin : t
generate if(1) begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w


3
dev/verilog/trilib/tri_inv_nlats.v
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@ -73,8 +73,7 @@ module tri_inv_nlats(
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};

generate
begin
generate if(1) begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;

2
dev/verilog/trilib/tri_iuq_cpl_arr.v
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@ -156,7 +156,7 @@ module tri_iuq_cpl_arr (gnd, vdd, clk, rst, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b

assign perr = 1'b0;

begin : xhdl0
if(1) begin : xhdl0
genvar i;
for (i = 0; i <= PORT_BITWIDTH - 1; i = i + 1)
begin : array_gen0

3
dev/verilog/trilib/tri_nlat.v
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@ -76,8 +76,7 @@ module tri_nlat(

parameter [0:WIDTH-1] init_v = INIT;

generate
begin
generate if(1) begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;

3
dev/verilog/trilib/tri_nlat_scan.v
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@ -75,8 +75,7 @@ module tri_nlat_scan(
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};

generate
begin
generate if(1) begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;

3
dev/verilog/trilib/tri_nor2.v
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@ -49,8 +49,7 @@ module tri_nor2(
// tri_nor2
genvar i;

generate
begin : t
generate if(1) begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w


3
dev/verilog/trilib/tri_pri.v
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@ -54,8 +54,7 @@ module tri_pri(
wire [0:s] or_l4;
wire [0:s] or_l5;

generate
begin
generate if(1) begin
if (REV == 0)
begin
assign l0[0:s] = cond[0:s];

3
dev/verilog/trilib/tri_scom_addr_decode.v
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@ -89,8 +89,7 @@ module tri_scom_addr_decode(


//=====================================================================
generate
begin : decode_it
generate if(1) begin : decode_it
genvar i;
for (i=0; i<ADDR_SIZE; i=i+1)
begin : decode_it

9
dev/verilog/trilib/tri_serial_scom2.v
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@ -630,8 +630,7 @@ module tri_serial_scom2 (
end
endgenerate

generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar i;
for (i=0; i<=PAR_NOBITS-1; i=i+1)
begin : wdata_par_check
@ -670,8 +669,7 @@ module tri_serial_scom2 (
assign wpar_err = (^{par_data_lt, datapar_shifter_lt});

//-----------------------------------------------------------------------------
generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i=0; i<=PAR_NOBITS-1; i=i+1)
begin : rdata_parity_gen
@ -768,8 +766,7 @@ module tri_serial_scom2 (
// This was for unused addresses if USE_ADDR was smaller than the 64 bit width.
// From VHDL: short_unused_addr_range: for i in use_addr'high+1 to 63 generate
// Shouldn't be needed for A2, since we always define 64 SCOM addresses.
generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar i;
for (i=WIDTH; i<64; i=i+1)
begin : short_unused_addr_range

3
dev/verilog/trilib/tri_xnor2.v
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@ -49,8 +49,7 @@ module tri_xnor2(

genvar i;

generate
begin : t
generate if(1) begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w


3
dev/verilog/trilib/tri_xor2.v
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@ -49,8 +49,7 @@ module tri_xor2(

genvar i;

generate
begin : t
generate if(1) begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w


3
dev/verilog/trilib/tri_xor3.v
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@ -50,8 +50,7 @@ module tri_xor3(
input [0:WIDTH-1] c;
genvar i;

generate
begin : t
generate if(1) begin : t
for (i = 0; i < WIDTH; i = i + 1)
begin : w


2
dev/verilog/unisims/RAMB16_S18_S18.v
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@ -53,7 +53,7 @@ module RAMB16_S18_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB,
assign bAddrA = ADDRA[(bramAddrWidth)-1:0];
assign bAddrB = ADDRB[(bramAddrWidth)-1:0];

generate begin
generate if(1) begin
genvar i;
for (i = 1; i >= 0; i = i - 1) begin : ra
bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model(

2
dev/verilog/unisims/RAMB16_S36_S36.v
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@ -64,7 +64,7 @@ module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB,
assign bAddrA = ADDRA[(bramAddrWidth)-1:0];
assign bAddrB = ADDRB[(bramAddrWidth)-1:0];

generate begin
generate if(1) begin
genvar i;
for (i = 3; i >= 0; i = i - 1) begin: ra
bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model(

2
dev/verilog/unisims/RAMB16_S9_S9.v
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@ -50,7 +50,7 @@ module RAMB16_S9_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, D
assign bAddrA = ADDRA[(bramAddrWidth)-1:0];
assign bAddrB = ADDRB[(bramAddrWidth)-1:0];

generate begin
generate if(1) begin
genvar i;
for (i = 0; i >= 0; i = i - 1) begin : ra
bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model(

2
dev/verilog/unisims/RAMB36.v
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@ -78,7 +78,7 @@ module RAMB36(CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DO
assign bAddrA = ADDRA[(bramAddrWidth+5)-1:5];
assign bAddrB = ADDRB[(bramAddrWidth+5)-1:5];

generate begin
generate if(1) begin
genvar i;
for (i = 3; i >= 0; i = i - 1) begin: ra
bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model(

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dev/verilog/work/fu_oscr.v
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@ -1583,7 +1583,7 @@ module fu_oscr(



begin : xhdl1
if(1) begin : xhdl1
// genvar i;
for (i = 0; i <= 31; i = i + 1)
begin : writeport_hfpscr_thr0
@ -1835,7 +1835,7 @@ module fu_oscr(



begin : xhdl2
if(1) begin : xhdl2
// genvar i;
for (i = 0; i <= 23; i = i + 1)
begin : writeport_hfpscr_thr0
@ -2012,7 +2012,7 @@ module fu_oscr(
assign fread1_thr1[23] = (ra1_thr1[1:5] == 5'b10111) & re1_thr1;


begin : xhdl3
if(1) begin : xhdl3
// genvar i;
for (i = 0; i <= 23; i = i + 1)
begin : writeport_hfpscr_thr1

8
dev/verilog/work/iuq_bp.v
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@ -1354,8 +1354,7 @@ wire [0:7] bcache_shift;
assign iu3_b_d = iu2_instr_pri[33];
assign iu3_tar_d[6:29] = iu2_instr_pri[6:29];

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 62 - `EFF_IFAR_WIDTH; i <= 61; i = i + 1)
begin : sign_extend
@ -1674,7 +1673,7 @@ assign ex5_btb_repl_new[0:1] = ((ex5_btb_entry_q == 1'b0 & ex5_br_taken_q == 1'b
ex5_btb_repl_cnt[0:1];

generate
begin : xhdl2
if(1) begin : xhdl2
genvar i;
for (i = 0; i <= 63; i = i + 1)
begin : repl_cnt
@ -1699,8 +1698,7 @@ assign iu0_btb_hist_new[0:1] = (ex5_val_q == 1'b0 & ex5_btb_entry_q == 1'b1 & ex
(ex5_br_taken_q == 1'b0 & ex5_btb_hist[0:1] != 2'b00) ? ex5_btb_hist[0:1] - 2'b01 :
ex5_btb_hist[0:1];

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar i;
for (i = 0; i <= 63; i = i + 1)
begin : btb_hist

6
dev/verilog/work/iuq_cpl.v
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@ -908,8 +908,7 @@ module iuq_cpl(
//-----------------------------------------------
// calculate branch target address
//-----------------------------------------------
generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar i;
for (i = 62 - `EFF_IFAR_WIDTH; i <= 61; i = i + 1)
begin : sign_extend_i0
@ -942,8 +941,7 @@ module iuq_cpl(
(rn_cp_iu6_i0_instr[30] == 1'b1) ? bta_abs_i0[62 - `EFF_IFAR_WIDTH:61] :
bta_off_i0[62 - `EFF_IFAR_WIDTH:61];

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 62 - `EFF_IFAR_WIDTH; i <= 61; i = i + 1)
begin : sign_extend_i1

21
dev/verilog/work/iuq_cpl_ctrl.v
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@ -2200,8 +2200,7 @@ module iuq_cpl_ctrl(
//-----------------------------------------------------------------------------
// Update Fields on Dispatch
//-----------------------------------------------------------------------------
generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar e;
for (e = 0; e < `CPL_Q_DEPTH ; e = e + 1)
begin : dispatch_update_gen
@ -2248,8 +2247,7 @@ module iuq_cpl_ctrl(
assign iu6_i0_db_IAC_IVC_event = iac1_dbg_event[0] | iac2_dbg_event[0] | iac3_dbg_event[0] | iac4_dbg_event[0] | ivc_dbg_event[0];
assign iu6_i1_db_IAC_IVC_event = iac1_dbg_event[1] | iac2_dbg_event[1] | iac3_dbg_event[1] | iac4_dbg_event[1] | ivc_dbg_event[1];

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar e;
for (e = 0; e < `CPL_Q_DEPTH; e = e + 1)
begin : db_event_cp_gen
@ -2370,8 +2368,7 @@ module iuq_cpl_ctrl(
//-----------------------------------------------------------------------------
// Update Fields on Execution
//-----------------------------------------------------------------------------
generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar e;
for (e = 0; e < `CPL_Q_DEPTH; e = e + 1)
begin : cp1_executed_update_gen
@ -2834,8 +2831,7 @@ assign select_lq =
assign iu6_ifar[0] = {cp3_nia_q[62 - `EFF_IFAR_ARCH:61 - `EFF_IFAR_WIDTH], iu6_i0_ifar_q};
assign iu6_ifar[1] = {cp3_nia_q[62 - `EFF_IFAR_ARCH:61 - `EFF_IFAR_WIDTH], iu6_i1_ifar_q};

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar e;
for (e = 0; e < `EFF_IFAR_ARCH; e = e + 1)
begin : iac_mask_gen
@ -2845,8 +2841,7 @@ assign select_lq =
end
endgenerate

generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar t;
for (t = 0; t <= 1; t = t + 1)
begin : ifar_cmp
@ -4357,8 +4352,7 @@ assign select_lq =
.dout(cp1_flush2ucode_type_q)
);

generate
begin : xhdl5
generate if(1) begin : xhdl5
genvar i;
for (i = 0; i <= `CPL_Q_DEPTH - 1; i = i + 1)
begin : q_depth_gen
@ -7817,8 +7811,7 @@ assign select_lq =
`define RESET_VECTOR 32'hFFFFFFFC
`endif

generate
begin : xhdl6
generate if(1) begin : xhdl6
genvar i;
for (i = 0; i < `EFF_IFAR_ARCH; i = i + 1)
begin : q_depth_gen

5
dev/verilog/work/iuq_cpl_table.v
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@ -362,7 +362,7 @@ module iuq_cpl_table(

//table_start
//
//?generate begin a(0 to 1);
//?generate if(1) begin a(0 to 1);
//?TABLE NIA<a> LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET);
//*INPUTS*============================*OUTPUTS*=======================*
//| | |
@ -2318,8 +2318,7 @@ assign irpt_taken_async =
({19{cp3_xu_excvec_val}} & xu_db_mask) |
({19{cp3_axu_excvec_val}} & axu_db_mask);

generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar i;
for (i = 0; i <= (19 - 1); i = i + 1)
begin : cp3_db_mask

33
dev/verilog/work/iuq_dispatch.v
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@ -1639,8 +1639,7 @@ module iuq_dispatch(
assign mm_iu_bus_snoop_hold_req_d = mm_iu_bus_snoop_hold_req | (mm_iu_bus_snoop_hold_req_l2 & (in_ucode_l2 | in_fusion_l2));

// Added logic for Erat invalidates to stop dispatch
generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : send_cnt
@ -1707,8 +1706,7 @@ module iuq_dispatch(
end
endgenerate

generate
begin : primux
generate if(1) begin : primux
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : credit_mux
@ -1776,8 +1774,7 @@ tri_nor2 sq_cmdq_send_cnt_t1_zero(sq_cmdq_send_cnt_zero[1], sq_cmdq_send_cnt[1][
tri_xor2 sq_cmdq_send_cnt_t1_one (sq_cmdq_send_cnt_one[1], sq_cmdq_send_cnt[1][0], sq_cmdq_send_cnt[1][1]);
`endif

generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : credit_ok
@ -1880,8 +1877,7 @@ tri_xor2 sq_cmdq_send_cnt_t1_one (sq_cmdq_send_cnt_one[1], sq_cmdq_send_cnt[1][
end
endgenerate

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : send_ok
@ -1928,8 +1924,7 @@ tri_xor2 sq_cmdq_send_cnt_t1_one (sq_cmdq_send_cnt_one[1], sq_cmdq_send_cnt[1][
`endif


generate
begin : local_credit_calc
generate if(1) begin : local_credit_calc
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : local_credit_calc_thread
@ -2123,8 +2118,7 @@ tri_xor2 sq_cmdq_send_cnt_t1_one (sq_cmdq_send_cnt_one[1], sq_cmdq_send_cnt[1][
endgenerate


generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : credit_proc
@ -2533,8 +2527,7 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
assign low_pri_mask_d[1] = spr_high_pri_mask[1] | spr_med_pri_mask[1] | (~spr_high_pri_mask[1] & ~spr_med_pri_mask[1] & low_pri_en[1]);
`endif

generate
begin : pri_mask
generate if(1) begin : pri_mask
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : pri_mask_set
@ -2857,8 +2850,7 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;


// Perf counters
generate
begin : perf_set
generate if(1) begin : perf_set
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : perf_mask_set
@ -2958,8 +2950,7 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
assign iu_pc_sq_credit_ok = iu_pc_sq_credit_ok_l2;


generate
begin : xhdl7
generate if(1) begin : xhdl7
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : thread_latches
@ -3746,8 +3737,7 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
.dout(low_pri_mask_l2)
);

generate
begin : low_pri_counts
generate if(1) begin : low_pri_counts
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : thread_latches
@ -3811,8 +3801,7 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
.dout(perf_iu6_stall_l2)
);

generate
begin : perf_counts
generate if(1) begin : perf_counts
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : thread_latches

9
dev/verilog/work/iuq_ibuf.v
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@ -426,8 +426,7 @@ module iuq_ibuf(
buffer_tail_q[0:`IBUFF_DEPTH - 1];

//configurable depth buffer
generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i <= `IBUFF_DEPTH - 1; i = i + 1)
begin : buffer_gen
@ -522,7 +521,7 @@ endgenerate

// reconstruct buffer data
generate
begin : xhdl2
if(1) begin : xhdl2
genvar i;
for (i = 0; i <= `IBUFF_DEPTH - 1; i = i + 1)
begin : buff0_mux
@ -543,7 +542,7 @@ endgenerate
assign buffer0_ibuff_data = buffer0_data_muxed[`IBUFF_DEPTH - 1];

generate
begin : xhdl3
if(1) begin : xhdl3
genvar i;
for (i = 0; i <= `IBUFF_DEPTH - 1; i = i + 1)
begin : buff1_mux
@ -571,7 +570,7 @@ assign buffer1_data = buffer1_ibuff_data[0:IBUFF_WIDTH - 1];
//--------------------------------------

generate
begin : xhdl4
if(1) begin : xhdl4
genvar i;
for (i = 0; i <= ((`IBUFF_DEPTH/4) - 1); i = i + 1)
begin : fetch_gen

45
dev/verilog/work/iuq_ic_dir.v
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@ -608,8 +608,7 @@ module iuq_ic_dir(
assign stored_erat_act = {`THREADS{iu2_valid_erat_read & (~spr_ic_ierat_byp_dis)}} & iu2_tid_l2;
assign iu1_stored_erat_updating = |(stored_erat_act & iu1_tid_l2); //'1' if stored erat is updating in IU2 for same thread that is in IU1

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : erat_val_gen
@ -683,8 +682,7 @@ module iuq_ic_dir(
assign dir_wr_addr = {icm_icd_dir_write_addr[51:56], (icm_icd_dir_write_addr[57] & (~spr_ic_cls_l2))}; // Use even row for 128B mode
assign dir_rd_addr = {ics_icd_iu0_index51, ics_icd_iu0_ifar[52:56], (ics_icd_iu0_ifar[57] & (~(spr_ic_cls_l2 & (~ics_icd_iu0_spr_idir_read))))};

generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar i;
for (i = 0; i < dir_parity_width*8; i = i + 1)
begin : calc_ext_dir_data
@ -850,8 +848,7 @@ module iuq_ic_dir(
assign data_write_act[2] = (data_way[0] | data_way[1]) & icm_icd_reload_addr[51];
assign data_write_act[3] = (data_way[2] | data_way[3]) & icm_icd_reload_addr[51];

generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar i;
for (i = 0; i < 18; i = i + 1)
begin : gen_data_parity
@ -942,8 +939,7 @@ module iuq_ic_dir(
//---------------------------------------------------------------------
// Compare Tag
//---------------------------------------------------------------------
generate
begin : xhdl5
generate if(1) begin : xhdl5
genvar i;
for (i = 0; i < 4; i = i + 1)
begin : rd_tag_hit0
@ -1021,8 +1017,7 @@ module iuq_ic_dir(
// Check Parity
//---------------------------------------------------------------------
// Dir
generate
begin : xhdl9
generate if(1) begin : xhdl9
genvar w;
for (w = 0; w < 4; w = w + 1)
begin : calc_ext_dir_0
@ -1065,8 +1060,7 @@ module iuq_ic_dir(
);

//Data
generate
begin : xhdl11
generate if(1) begin : xhdl11
genvar w;
for (w = 0; w < 4; w = w + 1)
begin : data_parity_out_gen
@ -1115,8 +1109,7 @@ module iuq_ic_dir(
assign ici_val_d = lq_iu_ici_val;

// update LRU in IU2 on read hit or dir_write
generate
begin : xhdl12
generate if(1) begin : xhdl12
genvar a;
for (a = 0; a < 128; a = a + 1)
begin : dir_lru_gen
@ -1157,8 +1150,7 @@ module iuq_ic_dir(
end
endgenerate

generate
begin : xhdl13
generate if(1) begin : xhdl13
genvar a;
for (a = 0; a < 16; a = a + 1)
begin : dir_lru_act_gen
@ -1210,8 +1202,7 @@ module iuq_ic_dir(
// IU2
//---------------------------------------------------------------------
// IU2 Output
generate
begin : xhdl14
generate if(1) begin : xhdl14
genvar i;
for (i = 0; i < 52; i = i + 1)
begin : mm_epn
@ -1272,8 +1263,7 @@ module iuq_ic_dir(
assign iu3_erat_err_d = iu2_ierat_error[0:2] & {3{iu2_valid_l2}};

// Rotate instructions
generate
begin : xhdl15
generate if(1) begin : xhdl15
genvar w;
for (w = 0; w < 4; w = w + 1)
begin : iu2_instr_rot0
@ -1346,8 +1336,7 @@ module iuq_ic_dir(
// Using xori 0,0,0 (xnop) when erat error
//xnop <= "011010" & ZEROS(6 to 35);

generate
begin : xhdl16
generate if(1) begin : xhdl16
genvar i;
for (i = 0; i < 4; i = i + 1)
begin : gen_instr
@ -1389,8 +1378,7 @@ module iuq_ic_dir(
//---------------------------------------------------------------------
// Performance Events
//---------------------------------------------------------------------
generate
begin : xhdl10
generate if(1) begin : xhdl10
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : gen_perf
@ -1931,8 +1919,7 @@ module iuq_ic_dir(
);

// Dir
generate
begin : xhdl17
generate if(1) begin : xhdl17
genvar a;
for (a = 0; a < 128; a = a + 1)
begin : dir_val_latch_gen
@ -2315,8 +2302,7 @@ module iuq_ic_dir(
.dout(iu2_spr_idir_lru_l2)
);

generate
begin : xhdl19
generate if(1) begin : xhdl19
if (`INCLUDE_IERAT_BYPASS == 0)
begin : gen0
genvar i;
@ -2396,8 +2382,7 @@ module iuq_ic_dir(
end
endgenerate

generate
begin : xhdl18
generate if(1) begin : xhdl18
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : gen_perf_reg

15
dev/verilog/work/iuq_ic_ierat.v
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@ -1513,8 +1513,7 @@ module iuq_ic_ierat(
// 3) tlb-reload hit/miss,
// 4) hold is cleared, tlb-miss sets tlb_miss_q=1, tlb-hit writes erat
// 5) replay of op clears tlb_miss_q if set, erat miss sets hold again but no flush this time
generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : holdTid
@ -1565,8 +1564,7 @@ module iuq_ic_ierat(
assign iu_mm_ierat_snoop_ack = snoop_val_q[2];


generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : rpnTid
@ -4095,8 +4093,7 @@ assign ex6_data_maskpar =
assign ex4_rd_data_calc_par[66] = ^(ex4_rd_array_data_q[38:44]);
assign ex4_rd_data_calc_par[67] = ^(ex4_rd_array_data_q[45:50]);

generate
begin
generate if(1) begin
if (check_parity == 0)
begin
assign iu2_cmp_data_parerr_epn = 1'b0;
@ -4235,8 +4232,7 @@ assign ex6_data_maskpar =
( (|(ex1_valid_q[0:`THREADS-1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]) & (~(snoop_val_q[0] & snoop_val_q[1])) ) | // eratsx, tlbsel=2
( iu_ierat_iu0_val & (~(snoop_val_q[0] & snoop_val_q[1])) ) ); // fetch

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar tid;
for (tid = 0; tid <= 3; tid = tid + 1)
begin : compTids
@ -6378,8 +6374,7 @@ assign ex6_data_maskpar =
.dout(mmucr1_q)
);

generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : rpn_holdreg

57
dev/verilog/work/iuq_ic_miss.v
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@ -517,8 +517,7 @@ module iuq_ic_miss(

assign tidn32 = 32'b0;

generate
begin : xhdl1
generate if(1) begin : xhdl1
if (TAGS_USED < SM_MAX)
begin : gen_unused_t1
assign miss_unused = | {load_tag[TAGS_USED:SM_MAX - 1], reset_state[TAGS_USED:SM_MAX - 1], request_tag[TAGS_USED:SM_MAX - 1], write_dir_val[TAGS_USED:SM_MAX - 1], hold_tid[TAGS_USED:SM_MAX - 1], dir_write[TAGS_USED:SM_MAX - 1], miss_ci_d[TAGS_USED:SM_MAX - 1], miss_flushed_d[TAGS_USED:SM_MAX - 1], miss_inval_d[TAGS_USED:SM_MAX - 1], active_l1_miss[TAGS_USED:SM_MAX-1], miss_tid_sm_d[TAGS_USED], miss_tid_sm_d[SM_MAX - 1]}; // ??? tid_sm isn't covered for (sm_max-tags_used > 2)
@ -568,8 +567,7 @@ module iuq_ic_miss(
//---------------------------------------------------------------------
// Latch Inputs, Reload pipeline
//---------------------------------------------------------------------
generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar i;
for (i = 0; i < TAGS_USED; i = i + 1)
begin : gen_default_reld_act
@ -594,8 +592,7 @@ module iuq_ic_miss(
// Core_tag(0:2) specifies unit (IU is '010'); Core_tag(3:4) is encoded Thread ID
assign reld_r0_vld = an_ac_reld_data_vld_l2 & (an_ac_reld_core_tag_l2[0:2] == 3'b010);

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar i;
for (i = 0; i < TAGS_USED; i = i + 1)
begin : gen_reld_tag
@ -618,8 +615,7 @@ module iuq_ic_miss(
assign an_ac_reld_ecc_err_d = an_ac_reld_ecc_err;
assign an_ac_reld_ecc_err_ue_d = an_ac_reld_ecc_err_ue;

generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : gen_reld_r3_tid
@ -648,8 +644,7 @@ module iuq_ic_miss(
//
// For now, always generating 4 tables, even if only 1 thread. Can't generate based on a generic, and don't want to include config file. Extra tables should optimize out when not needed.
//
generate
begin
generate if(1) begin
genvar i;
for (i = 0; i < SM_MAX; i = i + 1)
begin : miss_sm_loop
@ -689,8 +684,7 @@ module iuq_ic_miss(
assign iu_pc_icache_quiesce = iu_xu_icache_quiesce_int;

// SM0 is only for non-prefetches, SM1 is for prefetches, or for new IFetches if SM1 is free and SM0 is busy (e.g. sometimes after flush)
generate
begin : xhdl5
generate if(1) begin : xhdl5
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : gen_new_miss
@ -833,8 +827,7 @@ module iuq_ic_miss(
//---------------------------------------------------------------------
// Send request
//---------------------------------------------------------------------
generate
begin : xhdl12
generate if(1) begin : xhdl12
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : gen_request
@ -935,8 +928,7 @@ module iuq_ic_miss(
// for first beat of data: create hole in IU0 so we can fastpath data into IU2
assign preload_r0_tag = r0_crit_qw & reld_r0_tag & (~miss_block_fp_l2) & (~miss_flushed_l2[0:TAGS_USED - 1]);

generate
begin : xhdl13
generate if(1) begin : xhdl13
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : gen_preload_r0_tid
@ -954,8 +946,7 @@ module iuq_ic_miss(
assign load_2ucode_type = |(reld_r2_val_l2 & miss_2ucode_type_l2);
assign load_tag_no_block = load_tag[0:TAGS_USED - 1] & (~miss_block_fp_l2[0:TAGS_USED - 1]);

generate
begin : xhdl14
generate if(1) begin : xhdl14
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : gen_load_tid
@ -975,8 +966,7 @@ module iuq_ic_miss(
// Critical Quadword
//---------------------------------------------------------------------
// Note: Could latch reld_crit_qw signal from L2, but we need addr (60:61), so might as well keep whole address
generate
begin : xhdl15
generate if(1) begin : xhdl15
genvar i;
for (i = 0; i < TAGS_USED; i = i + 1)
begin : gen_crit_qw
@ -1004,8 +994,7 @@ module iuq_ic_miss(
assign row_lru = (lru_write_hit == 1'b0) ? icd_icm_row_lru :
hit_lru;

generate
begin : xhdl16
generate if(1) begin : xhdl16
genvar i;
for (i = 0; i < TAGS_USED; i = i + 1)
begin : gen_lru
@ -1230,8 +1219,7 @@ assign next_lru_way[3] =
(val_or_match[3] == 1'b0) ? 4'b0001 :
next_lru_way;

generate
begin : xhdl17
generate if(1) begin : xhdl17
genvar i;
for (i = 0; i < TAGS_USED; i = i + 1)
begin : gen_miss_way
@ -1244,8 +1232,7 @@ assign next_lru_way[3] =
//---------------------------------------------------------------------
// setting output signals
//---------------------------------------------------------------------
generate
begin : xhdl18
generate if(1) begin : xhdl18
genvar i;
for (i = 0; i < `THREADS ; i = i + 1)
begin : gen_hold_thread
@ -1339,8 +1326,7 @@ assign next_lru_way[3] =
assign icm_icd_dir_write_way = reload_way;

// LRU Write: Occurs 2 cycles after Data 2 data_write (64B mode) or Data6 (128B mode)
generate
begin : xhdl19
generate if(1) begin : xhdl19
genvar i;
for (i = 0; i < TAGS_USED; i = i + 1)
begin : gen_lru_write
@ -1367,8 +1353,7 @@ assign next_lru_way[3] =
assign ecc_err[0:TAGS_USED - 1] = new_ecc_err | miss_ecc_err_l2;
assign ecc_err_ue[0:TAGS_USED - 1] = new_ecc_err_ue | miss_ecc_err_ue_l2;

generate
begin : xhdl20
generate if(1) begin : xhdl20
genvar i;
for (i = 0; i < TAGS_USED; i = i + 1)
begin : gen_ecc_inval
@ -1397,8 +1382,7 @@ assign next_lru_way[3] =
//---------------------------------------------------------------------
// Performance Events
//---------------------------------------------------------------------
generate
begin : xhdl11
generate if(1) begin : xhdl11
genvar i;
for (i = 0; i < SM_MAX; i = i + 1)
begin : g11
@ -1834,8 +1818,7 @@ assign next_lru_way[3] =
.dout(iu3_miss_match_l2)
);

generate
begin : xhdl21
generate if(1) begin : xhdl21
genvar i;
for (i = 0; i < TAGS_USED; i = i + 1)
begin : gen_sm
@ -2033,8 +2016,7 @@ assign next_lru_way[3] =
.dout(miss_need_hold_l2)
);

generate
begin : xhdl22
generate if(1) begin : xhdl22
genvar i;
for (i = 0; i < TAGS_USED; i = i + 1)
begin : gen
@ -2212,8 +2194,7 @@ assign next_lru_way[3] =
.dout(lru_write_l2)
);

generate
begin : xhdl23
generate if(1) begin : xhdl23
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : t

54
dev/verilog/work/iuq_ic_select.v
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@ -482,8 +482,7 @@ module iuq_ic_select(
assign oldest_prefetch_v[`THREADS - 1] = oldest_prefetch_l2;
`endif

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : gen_prefetch
@ -520,8 +519,7 @@ module iuq_ic_select(
assign an_ac_back_inv_addr_d = an_ac_back_inv_addr;
assign back_inv_addr_act = an_ac_back_inv_l2 & an_ac_back_inv_target_l2;

generate
begin
generate if(1) begin
if (`THREADS == 1)
begin : gen_icbi_val_t1
assign lq_iu_icbi_val_d[0] = lq_iu_icbi_val[0] | (lq_iu_icbi_val_l2[0] & an_ac_back_inv_l2 & an_ac_back_inv_target_l2);
@ -788,8 +786,7 @@ module iuq_ic_select(
end
end // iu0_ifar_proc

generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar t;
for (t = 0; t < `THREADS; t = t + 1)
begin : thread_iu0_ifar_mask
@ -818,8 +815,7 @@ module iuq_ic_select(
//---------------------------------------------------------------------
// Keep 42:51 to compare, and flush if cp or br flush

generate
begin : xhdl5
generate if(1) begin : xhdl5
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : stored_erat_gen
@ -857,8 +853,7 @@ module iuq_ic_select(
// Outputs
//---------------------------------------------------------------------
// ???? Do I want to split up threaded/non-threaded signals?
generate
begin : xhdl6
generate if(1) begin : xhdl6
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : hold_t
@ -887,8 +882,7 @@ module iuq_ic_select(
assign iu_ierat_iu0_thdid = iu0_erat_tid;
assign iu_ierat_iu0_prefetch = |(prefetch_ready) & (~(|(need_fetch_reduce & (~hold_thread))));

generate
begin : xhdl8
generate if(1) begin : xhdl8
genvar i;
for (i = 0; i < 52; i = i + 1)
begin : ierat_ifar
@ -948,8 +942,7 @@ module iuq_ic_select(
assign ics_icd_iu0_valid = iu0_valid;
assign ics_icd_iu0_tid = iu0_tid | next_prefetch;

generate
begin
generate if(1) begin
if (`THREADS == 1)
begin : gen_bp_iu0_val_t0
assign ic_bp_iu0_val[0] = iu0_tid[0] | icm_ics_iu0_preload_val[0];
@ -967,8 +960,7 @@ module iuq_ic_select(
(iu0_tid[0] == 1'b1) ? iu0_ifar_l2[0][50:59] :
iu0_ifar_l2[`THREADS - 1][50:59];

generate
begin
generate if(1) begin
if (`EFF_IFAR_ARCH > (`REAL_IFAR_WIDTH-2))
begin : iu0_ifar_gen0

@ -1023,8 +1015,7 @@ module iuq_ic_select(
// Performance Events
//---------------------------------------------------------------------

generate
begin : xhdl9
generate if(1) begin : xhdl9
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : perf
@ -1147,8 +1138,7 @@ module iuq_ic_select(
.dout(spr_idir_row_l2)
);

generate
begin
generate if(1) begin
if (`THREADS == 1)
begin : gen_oldest_t1
assign oldest_prefetch_l2 = oldest_prefetch_d & 1'b0;
@ -1197,8 +1187,7 @@ module iuq_ic_select(
.dout(iu0_need_prefetch_l2)
);

generate
begin : xhdl10
generate if(1) begin : xhdl10
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : t
@ -1243,8 +1232,7 @@ module iuq_ic_select(
.dout(lq_iu_icbi_val_l2)
);

generate
begin : xhdl11
generate if(1) begin : xhdl11
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : t
@ -1498,8 +1486,7 @@ module iuq_ic_select(
.dout(iu0_flip_index51_l2)
);

generate
begin
generate if(1) begin
if (`THREADS == 1)
begin : gen_last_tid_t1
assign iu0_last_tid_sent_l2 = 1'b0 & iu0_last_tid_sent_d;
@ -1529,8 +1516,7 @@ module iuq_ic_select(
end
endgenerate

generate
begin : xhdl13
generate if(1) begin : xhdl13
genvar t;
for (t = 0; t < `THREADS; t = t + 1)
begin : th
@ -1561,8 +1547,7 @@ module iuq_ic_select(
endgenerate

// IU0
generate
begin : xhdl14
generate if(1) begin : xhdl14
genvar t;
for (t = 0; t < `THREADS; t = t + 1)
begin : th
@ -1612,8 +1597,7 @@ module iuq_ic_select(
end
endgenerate

generate
begin : xhdl15
generate if(1) begin : xhdl15
if (`INCLUDE_IERAT_BYPASS == 0)
begin : gen0
genvar i;
@ -1749,8 +1733,7 @@ module iuq_ic_select(
.dout(cp_flush_into_uc_l2)
);

generate
begin : xhdl17
generate if(1) begin : xhdl17
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : t
@ -1928,8 +1911,7 @@ module iuq_ic_select(
.dout(iu2_nonspec_l2)
);

generate
begin : xhdl18
generate if(1) begin : xhdl18
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : t

6
dev/verilog/work/iuq_ifetch.v
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@ -1054,8 +1054,7 @@ module iuq_ifetch(
);


generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : bp_gen
@ -1358,8 +1357,7 @@ module iuq_ifetch(
.scan_out(ram_scan_out)
);

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i < `THREADS; i = i + 1)
begin : uc_gen

3
dev/verilog/work/iuq_ram.v
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@ -148,8 +148,7 @@ module iuq_ram(
assign cp_flush_d = cp_flush;
assign ram_done_d = iu_pc_ram_done;

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : issue_gating

21
dev/verilog/work/iuq_rn_map.v
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@ -294,8 +294,7 @@ module iuq_rn_map #(
assign spec_map_arc_act = flush_map | spec_0_wr_val_fast | spec_1_wr_val_fast;
assign spec_map_itag_act = 1'b1;

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : map_set0
@ -332,8 +331,7 @@ module iuq_rn_map #(
end
endgenerate

generate
begin : write_ptr_calc
generate if(1) begin : write_ptr_calc
genvar i;
for(i = 0; i <= (REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1); i = i + 1)
begin : write_ptr_set
@ -350,8 +348,7 @@ module iuq_rn_map #(

assign write_ptr_value = ({pool_free_0_v_l2, pool_free_1_v_l2} == 2'b01) ? pool_free_1_l2 :
pool_free_0_l2;
generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar i;
for (i = 0; i <= REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : buffer_pool_gen
@ -408,8 +405,7 @@ module iuq_rn_map #(
end

// Creating 1 hot muxing from pointers
generate
begin : read_ptr_calc
generate if(1) begin : read_ptr_calc
genvar i;
for(i = 0; i <= (REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1); i = i + 1)
begin : read_ptr_set
@ -443,8 +439,7 @@ module iuq_rn_map #(
end
end

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar i;
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : comp_map0
@ -471,8 +466,7 @@ module iuq_rn_map #(
end
endgenerate

generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar i;
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : spec_map0
@ -519,8 +513,7 @@ module iuq_rn_map #(
end
endgenerate

generate
begin : xhdl5
generate if(1) begin : xhdl5
genvar i;
for (i = 0; i <= REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : buffer_pool_lat

20
dev/verilog/work/iuq_spr.v
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@ -716,7 +716,7 @@ module iuq_spr(
);

generate
begin : xhdl1

genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : thread_regs
@ -882,8 +882,8 @@ module iuq_spr(
.dout(cpcr5_l2[i])
);
end
end
endgenerate
endgenerate

tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cpcr_we_reg(
.vd(vdd),
@ -1485,9 +1485,7 @@ module iuq_spr(
assign priv_mode = (~spr_msr_pr_l2);
assign hypv_mode = (~spr_msr_pr_l2) & (~spr_msr_gs_l2);

generate
begin : priset
genvar i;
generate if(1) begin
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : pricalc
assign lo_pri[i] = ~xu_iu_raise_iss_pri_l2[i] &
@ -1503,8 +1501,8 @@ module iuq_spr(
assign spr_high_pri_mask[i] = hi_pri[i];
assign spr_med_pri_mask[i] = ~hi_pri[i] & ~lo_pri[i];
end
end
endgenerate
end
endgenerate


//-----------------------------------------------
@ -1724,7 +1722,7 @@ module iuq_spr(
`endif

generate
begin : xhdl7
if(1) begin : xhdl7
genvar i;
for (i = 0; i <= 61; i = i + 1)
begin : iac_width
@ -1743,8 +1741,8 @@ module iuq_spr(
assign iac4[61 - i] = 1'b0;
end
end
end
endgenerate
end
endgenerate
assign iac1[62:63] = 2'b00;
assign iac2[62:63] = 2'b00;
assign iac3[62:63] = 2'b00;

9
dev/verilog/work/iuq_uc.v
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@ -1472,8 +1472,7 @@ assign uc_legal =
//---------------------------------------------------------------------
assign iu4_stage_act = data_valid; // ??? Removed "not flush and not skip" from act. Do we want to add in some form of skip check?

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i <= 1; i = i + 1)
begin : gen_iu4_val
@ -1496,8 +1495,7 @@ assign uc_legal =

// Overflow latches
assign iu4_ov_stage_act = iu4_valid_l2[0] & (~iu4_ov_valid_l2[0]);
generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar i;
for (i = 0; i <= 1; i = i + 1)
begin : gen_ov_valid
@ -1517,8 +1515,7 @@ assign uc_legal =
// need to change uc_control so uc_ifar is not bigger than EFF_IFAR_WIDTH
// so that we don't lose part of ifar on flush

generate
begin
generate if(1) begin
if (uc_ifar >= `EFF_IFAR_WIDTH)
begin : ifara
always @(*) uc_ib_ifar0 = iu4_ifar_out[62 - `EFF_IFAR_WIDTH:61];

6
dev/verilog/work/iuq_uc_cplbuffer.v
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@ -169,8 +169,7 @@ module iuq_uc_cplbuffer(
(new_command_l2 == 1'b0 & ((flush_current & valid_l2) == 1'b1)) ? write_ptr_l2 - value_1[32-buffer_depth_log:31] :
write_ptr_l2;

generate
begin : gen_buff
generate if(1) begin : gen_buff
genvar i;
for (i = 0; i < buffer_depth; i = i + 1)
begin : buff_loop
@ -238,8 +237,7 @@ module iuq_uc_cplbuffer(
.dout(buffer_count_l2)
);

generate
begin
generate if(1) begin
genvar i;
for (i = 0; i < buffer_depth; i = i + 1)
begin : gen_b

4
dev/verilog/work/iuq_uc_rom_even.v
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@ -116,7 +116,7 @@ module iuq_uc_rom_even(
wire [0:scan_right] sov;

//64-bit core
//c64: if (regmode = 6) generate begin
//c64: if (regmode = 6) generate if(1) begin

/*
//table_start
@ -2188,7 +2188,7 @@ assign ep =
//| 1111110110 | 1110110000000001-----00001111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsubs s0,s1,s1,FB
//| 1111111000 | 1110110000000001-----00011111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsubs s0,s1,s3,FB
//32-bit core
//c32: if (regmode = 5) generate begin
//c32: if (regmode = 5) generate if(1) begin
//end generate;



4
dev/verilog/work/iuq_uc_rom_odd.v
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@ -115,7 +115,7 @@ module iuq_uc_rom_odd(
wire [0:scan_right] sov;

//64-bit core
//c64: if (regmode = 6) generate begin
//c64: if (regmode = 6) generate if(1) begin

/*
//table_start
@ -1995,7 +1995,7 @@ assign ep =
//| 1111110111 | 1110110001000011-----00011111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsubs s2,s3,s3,FB
//| 1111111001 | 111011-----00001000000000010001- 1 - 0 - --- 0 1 1 1 0 01 00 00 00 0 1 0 0 - 0 ---------- --- - | # fmuls_uc FT,s1,s0,s0 include s0 in 16-20
//32-bit core
//c32: if (regmode = 5) generate begin
//c32: if (regmode = 5) generate if(1) begin
//end generate;



2
dev/verilog/work/lq_arb.v
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@ -565,7 +565,7 @@ module lq_arb(
end
endgenerate

generate begin : parGen
generate if(1) begin : parGen
genvar t;
for (t = 0; t <= 15; t = t + 1) begin : parGen
assign stq2_store_parity[t] = ^(stq2_store_data_q[t * 8:(t * 8) + 7]);

8
dev/verilog/work/lq_byp.v
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@ -623,7 +623,7 @@ assign ex3_req_aborted_d = ex2_req_aborted;
assign ex4_req_aborted_d = ex3_req_aborted_q;
assign ex5_req_aborted_d = ex4_req_aborted_q;

generate begin : ex5ParGen
generate if(1) begin : ex5ParGen
genvar b;
for (b=0; b<=((2**`GPR_WIDTH_ENC)-1)/8; b=b+1) begin : ex5ParGen
assign ex5_fx_ld_data_par[b] = ^(ex5_fx_ld_data[(64-(2**`GPR_WIDTH_ENC))+(b*8):(64-(2**`GPR_WIDTH_ENC))+(b*8)+7]);
@ -829,7 +829,7 @@ assign ex2_s2_abort_d = ex1_s2_abort;
//----------------------------------------------------------------------------------------------------------------------------------------

// Load Hit Data Compare
generate begin : dvcCmpLH
generate if(1) begin : dvcCmpLH
genvar t;
for (t = 0; t <= ((2 ** `GPR_WIDTH_ENC)/8) - 1; t = t + 1) begin : dvcCmpLH
assign ex6_dvc1_cmp_d[t] = ( ex5_fx_ld_data[(64-(2**`GPR_WIDTH_ENC))+t*8:(64-(2**`GPR_WIDTH_ENC))+((t*8)+7)] ==
@ -841,7 +841,7 @@ end
endgenerate

// Thread Select
generate begin : sprTid
generate if(1) begin : sprTid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid
assign spr_dbcr2_dvc1m_tid[tid] = spr_byp_spr_dbcr2_dvc1m[(tid*2):((tid*2)+1)];
@ -906,7 +906,7 @@ assign lq_pc_ram_data = lq_pc_ram_data_q;
//----------------------------------------------------------------------------------------------------------------------------------------
// Reload Data Parity Generation
//----------------------------------------------------------------------------------------------------------------------------------------
generate begin : relParGen
generate if(1) begin : relParGen
genvar b;
for (b = 0; b <= (`STQ_DATA_SIZE- 1)/8; b=b+1) begin : relParGen
assign rel2_data_par[b] = ^(lsq_ctl_rel2_data[(128-`STQ_DATA_SIZE) + b*8:((128-`STQ_DATA_SIZE))+(b*8)+7]);

22
dev/verilog/work/lq_data_ld.v
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@ -319,7 +319,7 @@ assign dcarr_rd_parity_wh = dcarr_rd_data[1136:1151];
// #############################################################################################
// Way A 16 Byte Rotator
// #############################################################################################
generate begin : l1dcrotrWA
generate if(1) begin : l1dcrotrWA
genvar b;
for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWA
if (b == 0) begin : sgrp
@ -394,7 +394,7 @@ endgenerate
// #############################################################################################
// Way B 16 Byte Rotator
// #############################################################################################
generate begin : l1dcrotrWB
generate if(1) begin : l1dcrotrWB
genvar b;
for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWB
if (b == 0) begin : sgrp
@ -469,7 +469,7 @@ endgenerate
// #############################################################################################
// Way C 16 Byte Rotator
// #############################################################################################
generate begin : l1dcrotrWC
generate if(1) begin : l1dcrotrWC
genvar b;
for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWC
if (b == 0) begin : sgrp
@ -544,7 +544,7 @@ endgenerate
// #############################################################################################
// Way D 16 Byte Rotator
// #############################################################################################
generate begin : l1dcrotrWD
generate if(1) begin : l1dcrotrWD
genvar b;
for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWD
if (b == 0) begin : sgrp
@ -619,7 +619,7 @@ endgenerate
// #############################################################################################
// Way E 16 Byte Rotator
// #############################################################################################
generate begin : l1dcrotrWE
generate if(1) begin : l1dcrotrWE
genvar b;
for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWE
if (b == 0) begin : sgrp
@ -694,7 +694,7 @@ endgenerate
// #############################################################################################
// Way F 16 Byte Rotator
// #############################################################################################
generate begin : l1dcrotrWF
generate if(1) begin : l1dcrotrWF
genvar b;
for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWF
if (b == 0) begin : sgrp
@ -769,7 +769,7 @@ endgenerate
// #############################################################################################
// Way G 16 Byte Rotator
// #############################################################################################
generate begin : l1dcrotrWG
generate if(1) begin : l1dcrotrWG
genvar b;
for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWG
if (b == 0) begin : sgrp
@ -844,7 +844,7 @@ endgenerate
// #############################################################################################
// Way H 16 Byte Rotator
// #############################################################################################
generate begin : l1dcrotrWH
generate if(1) begin : l1dcrotrWH
genvar b;
for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWH
if (b == 0) begin : sgrp
@ -919,7 +919,7 @@ endgenerate
// #############################################################################################
// Parity Check
// #############################################################################################
generate begin : parBdet
generate if(1) begin : parBdet
genvar b;
for (b = 0; b <= 15; b = b + 1) begin : parBdet
assign dcarr_perr_byte_wa[b] = dcarr_buf_data_wa[b + 0] ^ dcarr_buf_data_wa[b + 16] ^
@ -994,7 +994,7 @@ assign dcarr_data_perr_way = {dcarr_perr_det_wa, dcarr_perr_det_wb, dcarr_perr_d
// #############################################################################################

// Data Fixup
generate begin : ldData
generate if(1) begin : ldData
genvar bb;
for (bb = 0; bb <= 15; bb = bb + 1) begin : ldData
assign ex4_ld_data_swzl_wa[bb * 8:(bb * 8) + 7] = {ex4_ld_data_rot_wa[bb + 0],
@ -1091,7 +1091,7 @@ assign ex4_ld_data_wg[113:128] = ex4_ld_data_swzl_wg[112:127];
assign ex4_ld_data_wh[113:128] = ex4_ld_data_swzl_wh[112:127];

// Sign Extension
generate begin : algExt
generate if(1) begin : algExt
genvar b;
for (b = 0; b <= 47; b = b + 1) begin : algExt
assign ex4_ld_data_wa[65 + b] = ex4_ld_data_swzl_wa[64 + b] | ex4_ld_alg_bit_wa[b/8];

8
dev/verilog/work/lq_data_st.v
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@ -440,7 +440,7 @@ assign stq3_rot_sel3_d = {rotate_sel3, rotate_sel3};
assign stq3_store_rel_par_d = lsq_dat_stq2_store_data[128:143];

// Swizzle Rotate Data
generate begin : swzlSTData
generate if(1) begin : swzlSTData
genvar t;
for (t = 0; t <= 7; t = t + 1) begin : swzlSTData
assign stq3_store_rel_data_d[t * 16:(t * 16) + 15] = {lsq_dat_stq2_store_data[t + 0],
@ -468,7 +468,7 @@ endgenerate
// #############################################################################################

// Store Data Rotate
generate begin : l1dcrotl
generate if(1) begin : l1dcrotl
genvar b;
for (b = 0; b <= 7; b = b + 1) begin : l1dcrotl
tri_rot16_lu drotl(
@ -574,7 +574,7 @@ assign bittype_mask = (16'h0001 & {16{stq3_opsize_q[4]}}) | (16'h0003 & {16{stq3
(16'h000F & {16{stq3_opsize_q[2]}}) | (16'h00FF & {16{stq3_opsize_q[1]}}) |
(16'hFFFF & {16{stq3_opsize_q[0]}});

generate begin : maskGen
generate if(1) begin : maskGen
genvar b;
for (b = 0; b <= 7; b = b + 1)
begin : maskGen
@ -586,7 +586,7 @@ endgenerate
assign stq3_msk_data = stq3_rot_data & stq3_optype_mask;

// Swizzle Data to a proper format
generate begin : swzlData
generate if(1) begin : swzlData
genvar t;
for (t = 0; t <= 15; t = t + 1)
begin : swzlData

16
dev/verilog/work/lq_dcc.v
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@ -2872,7 +2872,7 @@ assign spr_epcr_duvd_d = xu_lq_spr_epcr_duvd;
assign spr_lpidr_d = mm_lq_lsu_lpidr;

// Threaded Registers
generate begin : tidPid
generate if(1) begin : tidPid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : tidPid
assign spr_pid_d[tid] = mm_lq_pid[14*tid:(14*tid)+13];
@ -3436,7 +3436,7 @@ assign ex3_icswx_ct[1] = (lsq_ctl_ex3_le_ct == 6'b100000) ? ex3_cop_ct[32] :
(lsq_ctl_ex3_le_ct == 6'b111111) ? ex3_cop_ct[63] :
1'b0;

generate begin : regConc
generate if(1) begin : regConc
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : regConc
// Concatenate Appropriate EPSC fields
@ -3493,7 +3493,7 @@ assign stq3_icswx_data_d = stq2_epid_val_q ? stq2_icswx_epid : stq2_icswx_nepid;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

// CR Setter
generate begin : crData
generate if(1) begin : crData
genvar cr;
for (cr=0; cr<`CR_WIDTH; cr=cr+1) begin : crData
if (cr == 2) begin : crSet0
@ -3547,7 +3547,7 @@ assign be3210_en = (ex3_eff_addr_q[62:63] == 2'b00) ? beC840_en[0:15] :
{3'b000, beC840_en[0:12]};

// Byte Enables Generated using the opsize and physical_addr(60 to 63)
generate begin : ben_gen
generate if(1) begin : ben_gen
genvar t;
for (t=0; t<16; t=t+1) begin : ben_gen
assign byte_en[t] = ex3_opsize[0] | be3210_en[t];
@ -3936,7 +3936,7 @@ assign ex3_stq_val_req_d = ex2_stq_val_req & ~fgen_ex2_stg_flush_int;
assign ex4_stq_val_req_d = ex3_stq_val_req_q & ~fgen_ex3_stg_flush_int;

// Wait for Next Completion Indicator Instructions
generate begin : cpNextItag
generate if(1) begin : cpNextItag
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : cpNextItag
assign ex3_wNComp_tid[tid] = ex3_thrd_id_q[tid] & iu_lq_recirc_val_q[tid] & (ex3_itag_q == iu_lq_cp_next_itag_q[tid]);
@ -4113,7 +4113,7 @@ assign dcc_spr_spr_xudbg0_done = dir_arr_rd_ex5_done_q;
assign xudbg1_dir_reg_d = {dir_arr_rd_directory, dir_arr_rd_lru};
assign xudbg1_parity_reg_d = dir_arr_rd_parity;

generate begin : xudbg1Watch
generate if(1) begin : xudbg1Watch
genvar tid;
for (tid=0; tid<4; tid=tid+1) begin : xudbg1Watch
if (tid < `THREADS) begin : tidVal
@ -4677,7 +4677,7 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_recirc_val_re
.dout(iu_lq_recirc_val_q)
);

generate begin : iu_lq_cp_next_itag_tid
generate if(1) begin : iu_lq_cp_next_itag_tid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : iu_lq_cp_next_itag_tid
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_next_itag_reg(
@ -10136,7 +10136,7 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) spr_lpidr_reg(
.dout(spr_lpidr_q)
);

generate begin : spr_pid_reg
generate if(1) begin : spr_pid_reg
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : spr_pid_reg
tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) spr_pid_reg(

31
dev/verilog/work/lq_derat.v
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@ -1857,8 +1857,7 @@ module lq_derat(
assign ex2_ra_entry_d = ra_entry_q;
assign csinv_complete = |(ex2_ttype_q[6:7]);

generate
begin : sprThrd
generate if(1) begin : sprThrd
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : sprThrd
@ -2412,7 +2411,7 @@ module lq_derat(
snoop_addr_q;
assign lq_mm_snoop_ack = snoop_val_q[2];

generate begin : rpnTid
generate if(1) begin : rpnTid
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : rpnTid
if (GPR_WIDTH == 64) begin : gen64_holdreg
@ -2485,7 +2484,7 @@ module lq_derat(
(eptr_q == 5'b11101) ? 5'b11110 :
(eptr_q == 5'b11110) ? 5'b11111 :
5'b00000;
generate begin : epn_mask
generate if(1) begin : epn_mask
genvar i;
for (i = (64 - (2 ** `GPR_WIDTH_ENC)); i <= 51; i = i + 1) begin : epn_mask
if (i < 32) begin : R0
@ -2519,7 +2518,7 @@ module lq_derat(
assign lru_update_event_d[7] = lru_update_event_q[4] & cam_hit;
assign lru_update_event_d[8] = (tlb_rel_data_q[eratpos_wren] & (|(tlb_rel_val_q[0:3])) & tlb_rel_val_q[4]) | (snoop_val_q[0] & snoop_val_q[1]) | (csinv_complete) | (|(ex2_valid_op_q) & ex2_ttype_q[1] & (ex2_ws_q == 2'b00) & (ex2_tlbsel_q == TlbSel_DErat) & (lru_way_encode == ex2_ra_entry_q));
assign lru_update_event_d[9] = lru_update_event_q[8] | (lru_update_event_q[4] & cam_hit);
//?generate begin n(1 to 31);
//?generate if(1) begin n(1 to 31);
//lru_d(<n>) <= '1' when lru_set_vec(<n>)='1' and lru_op_vec(<n>)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0'
// else '0' when lru_reset_vec(<n>)='1' and lru_op_vec(<n>)='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0'
// else lru_q(<n>);
@ -4090,7 +4089,7 @@ module lq_derat(
((|(ex2_pfetch_val_q)) == 1'b1))) ? 2'b11 :
2'b00;
// mmucr1_q: 0-DRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-DPEI, 7:8-DCTID/DTTID, 9-DCCD
generate begin : compTids
generate if(1) begin : compTids
genvar tid;
for (tid = 0; tid <= 3; tid = tid + 1) begin : compTids
if (tid < `THREADS) begin : validTid
@ -4436,7 +4435,7 @@ module lq_derat(
// Look for first IDLE state machine from ERATMISSQ(0) -> ERATMISSQ(`EMQ_ENTRIES-1)
assign eratm_wrt_ptr[0] = eratm_entry_available[0];

generate begin : EMPriWrt
generate if(1) begin : EMPriWrt
genvar emq;
for (emq = 1; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) begin : EMPriWrt
assign eratm_wrt_ptr[emq] = &((~eratm_entry_available[0:emq - 1])) & eratm_entry_available[emq];
@ -4455,7 +4454,7 @@ module lq_derat(
// The ERATMISS Queue epn is valid in ex5, so this covers the back-2-back case
assign ex3_eratm_epn_m = ex3_eratm_chk_val & ex4_eratm_val & (ex4_epn_q == ex3_epn_q) & (~ex3_oldest_itag);

generate begin : ERATMQ
generate if(1) begin : ERATMQ
genvar emq;
for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) begin : ERATMQ

@ -4587,7 +4586,7 @@ module lq_derat(
assign ex3_oldest_itag = (lsq_ctl_oldest_itag == ex3_itag_q) & (|(lsq_ctl_oldest_tid & ex3_valid_q));
assign ex4_oldest_itag_d = ex3_oldest_itag;

generate begin : cpNextItag
generate if(1) begin : cpNextItag
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : cpNextItag
assign ex3_cp_next_tid[tid] = ex3_valid_q[tid] & cp_next_val_q[tid] & (ex3_itag_q == cp_next_itag_q[tid]);
@ -4684,7 +4683,7 @@ module lq_derat(
assign eratm_clrHold = |(eratm_entry_clr_hold);
assign eratm_clrHold_tid = {`THREADS{eratm_clrHold}};

generate begin : holdTid
generate if(1) begin : holdTid
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : holdTid
assign eratm_setHold_tid_ctrl[tid] = {ex4_setHold_tid[tid], eratm_clrHold_tid[tid]};
@ -7222,8 +7221,7 @@ module lq_derat(
.dout(mmucr1_q)
);
/*
generate
begin : rpn_holdreg
generate if(1) begin : rpn_holdreg
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : rpn_holdreg
@ -9726,8 +9724,7 @@ module lq_derat(

endgenerate
/*
generate
begin : eratm_entry_itag
generate if(1) begin : eratm_entry_itag
genvar emq;
for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1)
begin : eratm_entry_itag
@ -9755,8 +9752,7 @@ module lq_derat(
endgenerate
*/
/*
generate
begin : eratm_entry_tid
generate if(1) begin : eratm_entry_tid
genvar emq;
for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1)
begin : eratm_entry_tid
@ -9784,8 +9780,7 @@ module lq_derat(
endgenerate
*/
/*
generate
begin : eratm_entry_epn
generate if(1) begin : eratm_entry_epn
genvar emq;
for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1)
begin : eratm_entry_epn

16
dev/verilog/work/lq_dir_lru.v
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@ -675,7 +675,7 @@ assign stq4_congr_cl_d = stq3_congr_cl_q;
// Reload Pipe Directory Read
// ####################################################
// 1-hot Congruence Class Select
generate begin : stpCClass
generate if(1) begin : stpCClass
genvar cclass;
for (cclass=0; cclass<numCClass; cclass=cclass+1) begin : stpCClass
wire [uprCClassBit:lwrCClassBit] cclassDummy=cclass;
@ -716,7 +716,7 @@ assign rel_m_q_upd_way = rel_clr_vec & {numWays{rel_m_q_upd}};
assign rel_m_q_upd_lock_way = rel_clr_vec & {numWays{(rel_m_q_upd & rel3_lock_en_q)}};

// Reload Matching Reload Queue Entry
generate begin : relqByp
generate if(1) begin : relqByp
genvar lmq;
for (lmq=0; lmq<`LMQ_ENTRIES; lmq=lmq+1) begin : relqByp
assign rel_m_q[lmq] = (stq2_congr_cl_q == reld_q_congr_cl_q[lmq]) & reld_q_val_q[lmq];
@ -939,7 +939,7 @@ assign stq4_lru_upd_d = stq3_lru_upd;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Small Reload Way Enable Queue to Handle Beats with Gaps
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
generate begin : reldQ
generate if(1) begin : reldQ
genvar lmq;
for (lmq=0; lmq<`LMQ_ENTRIES; lmq=lmq+1) begin : reldQ
wire [0:3] lmqDummy = lmq;
@ -1051,7 +1051,7 @@ assign ex4_lru_upd_d = dcc_dir_ex3_lru_upd;
// Execution Pipe Directory Read
// ####################################################
// 1-hot Congruence Class Select
generate begin : ldpCClass
generate if(1) begin : ldpCClass
genvar cclass;
for (cclass=0; cclass<numCClass; cclass=cclass+1) begin : ldpCClass
wire [uprCClassBit:lwrCClassBit] cclassDummy=cclass;
@ -1158,7 +1158,7 @@ assign stq4_dcarr_way_en_d = rel_way_dwen;
assign congr_cl_act_d = ex5_c_acc_q | stq3_val_wen;

// Update LRU due to a Reload or an EX6 Execution operation
generate begin : lruUpd
generate if(1) begin : lruUpd
genvar cclass;
for (cclass=0; cclass<numCClass; cclass=cclass+1) begin : lruUpd
wire [uprCClassBit:lwrCClassBit] cclassDummy=cclass;
@ -1219,7 +1219,7 @@ assign rel3_dir_wr_addr = stq3_congr_cl_q;
// ####################################################

// Congruence Class LRU
generate begin : congr_cl_lru
generate if(1) begin : congr_cl_lru
genvar cclass;
for (cclass=0; cclass<numCClass; cclass=cclass+1) begin : congr_cl_lru
tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_lru_reg(
@ -2024,7 +2024,7 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) rel4_dir_way_upd_reg
.dout(rel4_dir_way_upd_q)
);

generate begin : reld_q_congr_cl
generate if(1) begin : reld_q_congr_cl
genvar lmq0;
for (lmq0=0; lmq0<`LMQ_ENTRIES; lmq0=lmq0+1) begin : reld_q_congr_cl
tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) reld_q_congr_cl_reg(
@ -2049,7 +2049,7 @@ generate begin : reld_q_congr_cl
end
endgenerate

generate begin : reld_q_way
generate if(1) begin : reld_q_way
genvar lmq1;
for (lmq1=0; lmq1<`LMQ_ENTRIES; lmq1=lmq1+1) begin : reld_q_way
tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) reld_q_way_reg(

12
dev/verilog/work/lq_dir_tag_arr.v
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@ -237,7 +237,7 @@ assign wr_data = wdata;
// Array Parity Generation
// ####################################################

generate begin : extra_byte
generate if(1) begin : extra_byte
genvar t;
for (t = 0; t <= 7; t = t + 1) begin : extra_byte
if (t < (tagSize % 8)) begin : R0
@ -250,7 +250,7 @@ generate begin : extra_byte
end
endgenerate

generate begin : par_gen
generate if(1) begin : par_gen
genvar i;
for (i = 0; i <= (tagSize/8) - 1; i = i + 1) begin : par_gen
assign arr_parity[i] = ^(wr_data[8*i+uprTagBit:8*i+uprTagBit+7]);
@ -270,7 +270,7 @@ assign arr_wr_data = {wr_data, arr_parity};
// Tag Array Read
// ####################################################

generate begin : tagRead
generate if(1) begin : tagRead
genvar way;
for (way=0; way<numWays; way=way+1) begin : tagRead
assign p0_rd_way[way] = arr_rd_data0[(way*WAYDATASIZE):(way*WAYDATASIZE) + tagSize - 1];
@ -293,7 +293,7 @@ endgenerate
// Tag Parity Generation
// ####################################################

generate begin : rdExtraByte
generate if(1) begin : rdExtraByte
genvar way;
for (way=0; way<numWays; way=way+1) begin : rdExtraByte
genvar t;
@ -311,7 +311,7 @@ generate begin : rdExtraByte
end
endgenerate

generate begin : rdParGen
generate if(1) begin : rdParGen
genvar way;
for (way=0; way<numWays; way=way+1) begin : rdParGen
genvar i;
@ -386,7 +386,7 @@ endgenerate
// Parity Error Detect
// ####################################################

generate begin : parDet
generate if(1) begin : parDet
genvar way;
for (way=0; way<numWays; way=way+1) begin : parDet
assign p0_par_err_det[way] = p0_parity_gen_1b[way] ^ p0_parity_gen_2b[way] ^ p0_rd_par[way];

62
dev/verilog/work/lq_dir_val.v
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@ -1324,7 +1324,7 @@ assign ex5_way_hit_d = ex4_way_hit;
// Execution Pipe Directory Read
// ####################################################
// 1-hot Congruence Class Select
generate begin : ldpCClass
generate if(1) begin : ldpCClass
genvar cclass;
for (cclass=0; cclass<numCClass; cclass=cclass+1) begin : ldpCClass
wire [uprCClassBit:lwrCClassBit] cclassDummy = cclass;
@ -1404,7 +1404,7 @@ assign congr_cl_ex3_ex6_m = congr_cl_ex3_ex6_cmp_q & p0_wren_cpy_q;
assign congr_cl_ex3_stq4_m = congr_cl_ex3_stq4_cmp_q & rel4_clr_stg_val_q;
assign congr_cl_ex3_stq5_m = congr_cl_ex3_stq5_cmp_q & rel5_clr_stg_val_q;

generate begin : ldpByp
generate if(1) begin : ldpByp
genvar ways;
for (ways=0; ways<numWays; ways=ways+1) begin : ldpByp
// Way Bypass Calculation Should have the following priority
@ -1437,7 +1437,7 @@ endgenerate
// ####################################################
// Execution Pipe Update Directory Logic
// ####################################################
generate begin : ldpCtrl
generate if(1) begin : ldpCtrl
genvar ways;
for (ways=0; ways<numWays; ways=ways+1) begin : ldpCtrl
// Hit Detect
@ -1459,7 +1459,7 @@ generate begin : ldpCtrl

// Set/Clr Watch Bit for Thread on Port0
// Cacheline Watch Bits
begin : P0Watch
if(1) begin : P0Watch
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : P0Watch
assign ex4_dir_way[ways][2 + tid] = (ex4_way_val_q[ways][2 + tid] & ~ex4_clr_watch) | (ex4_way_val_q[ways][0] & ex4_set_watch[tid]);
@ -1687,7 +1687,7 @@ assign ex5_multihit_watch_lost = ex5_cClass_thrd_watch_q & {`THREADS{(ex5_dir_mu

// Parity Error Detect
// ####################################################
generate begin : ldpErrGen
generate if(1) begin : ldpErrGen
genvar ways;
for (ways=0; ways<numWays; ways=ways+1) begin : ldpErrGen
assign ex4_dir_perr_det[ways] = ex4_way_val_q[ways][0] & ex4_tag_perr_way[ways];
@ -1833,7 +1833,7 @@ assign stq4_way_hit_d = stq3_way_hit;
// Reload Pipe Directory Read
// ####################################################
// 1-hot Congruence Class Select
generate begin : stpCClass
generate if(1) begin : stpCClass
genvar cclass;
for (cclass=0; cclass<numCClass; cclass=cclass+1) begin : stpCClass
wire [uprCClassBit:lwrCClassBit] cclassDummy = cclass;
@ -1911,7 +1911,7 @@ assign congr_cl_stq2_stq5_m = congr_cl_stq2_stq5_cmp_q & p1_wren_cpy_q; // D
assign congr_cl_stq2_ex5_m = congr_cl_stq2_ex5_cmp_q & (ex5_binv_val_q | (ex5_lock_set_q & rel2_clr_stg_val_q));
assign congr_cl_stq2_ex6_m = congr_cl_stq2_ex6_cmp_q & p0_wren_q;

generate begin : stpByp
generate if(1) begin : stpByp
genvar ways;
for (ways=0; ways<numWays; ways=ways+1) begin : stpByp

@ -1945,7 +1945,7 @@ endgenerate
// ####################################################
// Reload/Commit Directory Update
// ####################################################
generate begin : stpCtrl
generate if(1) begin : stpCtrl
genvar ways;
for (ways=0; ways<numWays; ways=ways+1) begin : stpCtrl
// Hit Detect
@ -1967,7 +1967,7 @@ generate begin : stpCtrl

// Set/Clr Watch Bit for Thread on Port1
// Cacheline Watch Bits
begin : P1Watch
if(1) begin : P1Watch
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : P1Watch
assign stq3_dir_way[ways][2 + tid] = (stq3_way_val_q[ways][2 + tid] & (~(stq3_clr_watch[tid] | rel_way_clr[ways]))) | (rel3_set_watch[tid] & rel_way_set[ways]);
@ -2095,7 +2095,7 @@ always @(*) begin: stpThrdWatch
end

// Want to still update the STM_WATCHLOST indicator if the DCDIS=1
generate begin : wLVal
generate if(1) begin : wLVal
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : wLVal
assign stq4_watchlost_value[tid] = ~stq4_watch_clr_all[tid] ? stq4_lost_watch[tid] : stq4_l_fld_b1_q;
@ -2158,7 +2158,7 @@ assign stq4_multihit_watch_lost = stq4_cClass_thrd_watch_q & {`THREADS{stq4_dir_

// Parity Error Detect
// ####################################################
generate begin : stpErrGen
generate if(1) begin : stpErrGen
genvar ways;
for (ways=0; ways<numWays; ways=ways+1) begin : stpErrGen
assign stq3_err_det_way[ways] = stq3_way_val_q[ways][0] & stq3_tag_way_perr[ways];
@ -2187,7 +2187,7 @@ assign stq5_dir_err_val_d = stq4_dir_err_val;
// Update Watch Lost State Bits per thread
// ####################################################

generate begin : wLost
generate if(1) begin : wLost
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : wLost
assign stm_upd_watchlost_tid[tid] = {stq4_watchlost_upd[tid], ex5_watchlost_upd[tid]};
@ -2291,7 +2291,7 @@ assign stq7_wren_d = stq6_wren_q;
// Act Pin to all Directory Latches
assign congr_cl_all_act_d = (stq4_watch_clr_all_q & stq4_val_q) | stq4_dci_val_q | spr_xucr0_clfc_q;

generate begin : dirUpdCtrl
generate if(1) begin : dirUpdCtrl
genvar cclass;
for (cclass=0; cclass<numCClass; cclass=cclass+1) begin : dirUpdCtrl
wire [uprCClassBit:lwrCClassBit] cclassDummy = cclass;
@ -2305,7 +2305,7 @@ generate begin : dirUpdCtrl
assign p1_congr_cl_act_d[cclass] = p1_congr_cl_m[cclass] & (stq4_rel4_val_q | rel4_set_dir_val_q | stq4_dir_err_val);
assign congr_cl_act[cclass] = p0_congr_cl_act_q[cclass] | p1_congr_cl_act_q[cclass] | congr_cl_all_act_q;

begin : wayCtrl
if(1) begin : wayCtrl
genvar ways;
for (ways=0; ways<numWays; ways=ways+1) begin : wayCtrl
assign p0_way_data_upd_way[cclass][ways] = p0_congr_cl_act_q[cclass] & ex6_way_upd_q[ways] & p0_wren_q;
@ -2563,7 +2563,7 @@ assign lq_xu_spr_xucr0_cslc_binv = xucr0_cslc_binv_q;
// ####################################################

// Directory State for Way A
generate begin : congr_cl_wA
generate if(1) begin : congr_cl_wA
genvar cclassA;
for (cclassA=0; cclassA<numCClass; cclassA=cclassA+1) begin : congr_cl_wA
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wA_reg(
@ -2589,7 +2589,7 @@ generate begin : congr_cl_wA
endgenerate

// Directory State for Way B
generate begin : congr_cl_wB
generate if(1) begin : congr_cl_wB
genvar cclassB;
for (cclassB=0; cclassB<numCClass; cclassB=cclassB+1) begin : congr_cl_wB
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wB_reg(
@ -2615,7 +2615,7 @@ generate begin : congr_cl_wB
endgenerate

// Directory State for Way C
generate begin : congr_cl_wC
generate if(1) begin : congr_cl_wC
genvar cclassC;
for (cclassC=0; cclassC<numCClass; cclassC=cclassC+1) begin : congr_cl_wC
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wC_reg(
@ -2641,7 +2641,7 @@ generate begin : congr_cl_wC
endgenerate

// Directory State for Way D
generate begin : congr_cl_wD
generate if(1) begin : congr_cl_wD
genvar cclassD;
for (cclassD=0; cclassD<numCClass; cclassD=cclassD+1) begin : congr_cl_wD
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wD_reg(
@ -2667,7 +2667,7 @@ generate begin : congr_cl_wD
endgenerate

// Directory State for Way E
generate begin : congr_cl_wE
generate if(1) begin : congr_cl_wE
genvar cclassE;
for (cclassE=0; cclassE<numCClass; cclassE=cclassE+1) begin : congr_cl_wE
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wE_reg(
@ -2693,7 +2693,7 @@ generate begin : congr_cl_wE
endgenerate

// Directory State for Way F
generate begin : congr_cl_wF
generate if(1) begin : congr_cl_wF
genvar cclassF;
for (cclassF=0; cclassF<numCClass; cclassF=cclassF+1) begin : congr_cl_wF
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wF_reg(
@ -2719,7 +2719,7 @@ generate begin : congr_cl_wF
endgenerate

// Directory State for Way G
generate begin : congr_cl_wG
generate if(1) begin : congr_cl_wG
genvar cclassG;
for (cclassG=0; cclassG<numCClass; cclassG=cclassG+1) begin : congr_cl_wG
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wG_reg(
@ -2745,7 +2745,7 @@ generate begin : congr_cl_wG
endgenerate

// Directory State for Way H
generate begin : congr_cl_wH
generate if(1) begin : congr_cl_wH
genvar cclassH;
for (cclassH=0; cclassH<numCClass; cclassH=cclassH+1) begin : congr_cl_wH
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wH_reg(
@ -2808,7 +2808,7 @@ tri_rlmreg_p #(.WIDTH(numCClass), .INIT(0), .NEEDS_SRESET(1)) p1_congr_cl_act_re
.dout(p1_congr_cl_act_q)
);

generate begin : ex4_way_val
generate if(1) begin : ex4_way_val
genvar ways0;
for (ways0=0; ways0<numWays; ways0=ways0+1) begin : ex4_way_val
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) ex4_way_val_reg(
@ -2833,7 +2833,7 @@ generate begin : ex4_way_val
end
endgenerate

generate begin : ex5_way_val
generate if(1) begin : ex5_way_val
genvar ways1;
for (ways1=0; ways1<numWays; ways1=ways1+1) begin : ex5_way_val
tri_regk #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) ex5_way_val_reg(
@ -2934,7 +2934,7 @@ tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex7_way_upd_reg(
.dout(ex7_way_upd_q)
);

generate begin : ex5_dir_way
generate if(1) begin : ex5_dir_way
genvar ways2;
for (ways2=0; ways2<numWays; ways2=ways2+1) begin : ex5_dir_way
tri_regk #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) ex5_dir_way_reg(
@ -2959,7 +2959,7 @@ generate begin : ex5_dir_way
end
endgenerate

generate begin : ex6_dir_way
generate if(1) begin : ex6_dir_way
genvar ways3;
for (ways3=0; ways3<numWays; ways3=ways3+1) begin : ex6_dir_way
tri_rlmreg_p #(.WIDTH(2 + `THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_dir_way_reg(
@ -2984,7 +2984,7 @@ generate begin : ex6_dir_way
end
endgenerate

generate begin : ex7_dir_way
generate if(1) begin : ex7_dir_way
genvar ways4;
for (ways4=0; ways4<numWays; ways4=ways4+1) begin : ex7_dir_way
tri_regk #(.WIDTH(dirState-2), .INIT(0), .NEEDS_SRESET(1)) ex7_dir_way_reg(
@ -3009,7 +3009,7 @@ generate begin : ex7_dir_way
end
endgenerate

generate begin : stq3_way_val
generate if(1) begin : stq3_way_val
genvar ways5;
for (ways5=0; ways5<numWays; ways5=ways5+1) begin : stq3_way_val
tri_regk #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) stq3_way_val_reg(
@ -3034,7 +3034,7 @@ generate begin : stq3_way_val
end
endgenerate

generate begin : stq4_way_val
generate if(1) begin : stq4_way_val
genvar ways6;
for (ways6=0; ways6<numWays; ways6=ways6+1) begin : stq4_way_val
tri_rlmreg_p #(.WIDTH(dirState-2), .INIT(0), .NEEDS_SRESET(1)) stq4_way_val_reg(
@ -3059,7 +3059,7 @@ generate begin : stq4_way_val
end
endgenerate

generate begin : stq4_dir_way
generate if(1) begin : stq4_dir_way
genvar ways7;
for (ways7=0; ways7<numWays; ways7=ways7+1) begin : stq4_dir_way
tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) stq4_dir_way_reg(
@ -3084,7 +3084,7 @@ generate begin : stq4_dir_way
end
endgenerate

generate begin : stq5_dir_way
generate if(1) begin : stq5_dir_way
genvar ways8;
for (ways8=0; ways8<numWays; ways8=ways8+1) begin : stq5_dir_way
tri_regk #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) stq5_dir_way_reg(

4
dev/verilog/work/lq_fgen.v
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@ -712,7 +712,7 @@ generate
end
endgenerate

generate begin : memAttrQ
generate if(1) begin : memAttrQ
genvar ucodeEntry;
for (ucodeEntry=0; ucodeEntry<UCODEDEPTH; ucodeEntry=ucodeEntry+1) begin : memAttrQ
wire [0:`UCODE_ENTRIES_ENC+`THREADS_POOL_ENC-1] ucodeEntryDummy = ucodeEntry;
@ -2065,7 +2065,7 @@ tri_rlmreg_p #(.WIDTH(UCODEDEPTH), .INIT(0), .NEEDS_SRESET(1)) ucode_cnt_2ucode_
.dout(ucode_cnt_2ucode_q)
);

generate begin : ucode_cnt_memAttr
generate if(1) begin : ucode_cnt_memAttr
genvar ucodeEntry;
for (ucodeEntry=0; ucodeEntry<UCODEDEPTH; ucodeEntry=ucodeEntry+1) begin : ucode_cnt_memAttr
tri_rlmreg_p #(.WIDTH(9), .INIT(1), .NEEDS_SRESET(1)) ucode_cnt_memAttr_reg(

38
dev/verilog/work/lq_imq.v
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@ -380,7 +380,7 @@ module lq_imq(

// Update Logic
assign iuq_entry_wrt_ptr[0] = (~iuq_entry_val_q[0]);
generate begin : IuPriWrt
generate if(1) begin : IuPriWrt
genvar iuq;
for (iuq = 1; iuq <= `IUQ_ENTRIES - 1; iuq = iuq + 1) begin : IuPriWrt
assign iuq_entry_wrt_ptr[iuq] = &(iuq_entry_val_q[0:iuq - 1]) & (~iuq_entry_val_q[iuq]);
@ -388,7 +388,7 @@ module lq_imq(
end
endgenerate

generate begin : InstrQ
generate if(1) begin : InstrQ
genvar iuq;
for (iuq = 0; iuq <= `IUQ_ENTRIES - 1; iuq = iuq + 1) begin : InstrQ
assign entry_iuq_set_val[iuq] = iu_req_val & iuq_entry_wrt_ptr[iuq];
@ -427,7 +427,7 @@ module lq_imq(
// Instruction Fetches contain a sequence number that indicates an order
// They are sent to the L2 in the order recieved

generate begin : IQSel
generate if(1) begin : IQSel
genvar iuq;
for (iuq = 0; iuq <= `IUQ_ENTRIES - 1; iuq = iuq + 1) begin : IQSel
assign iuq_entry_sel[iuq] = (iuq_seq_rd_q == iuq_entry_seq_q[iuq]) & iuq_entry_val_q[iuq];
@ -493,7 +493,7 @@ module lq_imq(
// Update Logic
assign mmq_entry_wrt_ptr[0] = (~mmq_entry_val_q[0]);

generate begin : MmuPriWrt
generate if(1) begin : MmuPriWrt
genvar mmq;
for (mmq = 1; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : MmuPriWrt
assign mmq_entry_wrt_ptr[mmq] = &(mmq_entry_val_q[0:mmq - 1]) & (~mmq_entry_val_q[mmq]);
@ -501,7 +501,7 @@ module lq_imq(
end
endgenerate

generate begin : mmuQ
generate if(1) begin : mmuQ
genvar mmq;
for (mmq = 0; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : mmuQ
assign entry_mmq_set_val[mmq] = mm_req_val & mmq_entry_wrt_ptr[mmq];
@ -549,7 +549,7 @@ module lq_imq(
// MMU Requests contain a sequence number that indicates an order
// They are sent to the L2 in the order recieved

generate begin : MQSel
generate if(1) begin : MQSel
genvar mmq;
for (mmq = 0; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : MQSel
assign mmq_entry_sel[mmq] = (mmq_seq_rd_q == mmq_entry_seq_q[mmq]) & mmq_entry_val_q[mmq];
@ -919,7 +919,7 @@ module lq_imq(
.dout(iuq_entry_val_q)
);

generate begin : iuq_entry_p_addr
generate if(1) begin : iuq_entry_p_addr
genvar iuq;
for (iuq = 0; iuq <= `IUQ_ENTRIES - 1; iuq = iuq + 1) begin : iuq_entry_p_addr

@ -945,7 +945,7 @@ module lq_imq(
end
endgenerate

generate begin : iuq_entry_cTag
generate if(1) begin : iuq_entry_cTag
genvar iuq;
for (iuq = 0; iuq <= `IUQ_ENTRIES - 1; iuq = iuq + 1) begin : iuq_entry_cTag

@ -971,7 +971,7 @@ module lq_imq(
end
endgenerate

generate begin : iuq_entry_wimge
generate if(1) begin : iuq_entry_wimge
genvar iuq;
for (iuq = 0; iuq <= `IUQ_ENTRIES - 1; iuq = iuq + 1) begin : iuq_entry_wimge

@ -997,7 +997,7 @@ module lq_imq(
end
endgenerate

generate begin : iuq_entry_usr_def
generate if(1) begin : iuq_entry_usr_def
genvar iuq;
for (iuq = 0; iuq <= `IUQ_ENTRIES - 1; iuq = iuq + 1) begin : iuq_entry_usr_def

@ -1023,7 +1023,7 @@ module lq_imq(
end
endgenerate

generate begin : iuq_entry_tid
generate if(1) begin : iuq_entry_tid
genvar iuq;
for (iuq = 0; iuq <= `IUQ_ENTRIES - 1; iuq = iuq + 1) begin : iuq_entry_tid

@ -1049,7 +1049,7 @@ module lq_imq(
end
endgenerate

generate begin : iuq_entry_seq
generate if(1) begin : iuq_entry_seq
genvar iuq;
for (iuq = 0; iuq <= `IUQ_ENTRIES - 1; iuq = iuq + 1) begin : iuq_entry_seq

@ -1135,7 +1135,7 @@ module lq_imq(
.dout(mmq_entry_val_q)
);

generate begin : mmq_entry_p_addr
generate if(1) begin : mmq_entry_p_addr
genvar mmq;
for (mmq = 0; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : mmq_entry_p_addr

@ -1161,7 +1161,7 @@ module lq_imq(
end
endgenerate

generate begin : mmq_entry_ttype
generate if(1) begin : mmq_entry_ttype
genvar mmq;
for (mmq = 0; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : mmq_entry_ttype

@ -1187,7 +1187,7 @@ module lq_imq(
end
endgenerate

generate begin : mmq_entry_wimge
generate if(1) begin : mmq_entry_wimge
genvar mmq;
for (mmq = 0; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : mmq_entry_wimge

@ -1213,7 +1213,7 @@ module lq_imq(
end
endgenerate

generate begin : mmq_entry_usr_def
generate if(1) begin : mmq_entry_usr_def
genvar mmq;
for (mmq = 0; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : mmq_entry_usr_def

@ -1239,7 +1239,7 @@ module lq_imq(
end
endgenerate

generate begin : mmq_entry_tid
generate if(1) begin : mmq_entry_tid
genvar mmq;
for (mmq = 0; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : mmq_entry_tid

@ -1265,7 +1265,7 @@ module lq_imq(
end
endgenerate

generate begin : mmq_entry_seq
generate if(1) begin : mmq_entry_seq
genvar mmq;
for (mmq = 0; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : mmq_entry_seq

@ -1291,7 +1291,7 @@ module lq_imq(
end
endgenerate

generate begin : mmq_entry_lpid
generate if(1) begin : mmq_entry_lpid
genvar mmq;
for (mmq = 0; mmq <= `MMQ_ENTRIES - 1; mmq = mmq + 1) begin : mmq_entry_lpid


88
dev/verilog/work/lq_ldq.v
Unescape Escape View File

@ -1834,7 +1834,7 @@ assign ldqe_beat_init = {1'b0, ((~spr_xucr0_cls_q)), 2'b00};
// LDQ Entry WRT Pointer Logic
// Look for first IDLE state machine from LOADMISSQ(0) -> LOADMISSQ(`LMQ_ENTRIES-1)
assign ldqe_wrt_ptr[0] = ldqe_available[0];
generate begin : LdPriWrt
generate if(1) begin : LdPriWrt
genvar ldq;
for (ldq=1; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : LdPriWrt
assign ldqe_wrt_ptr[ldq] = &((~ldqe_available[0:ldq - 1])) & ldqe_available[ldq];
@ -1845,7 +1845,7 @@ endgenerate
// Check for only 1 entry available
// Look for first IDLE state machine from LOADMISSQ(`LMQ_ENTRIES-1) -> LOADMISSQ(0)
assign ldqe_opposite_ptr[`LMQ_ENTRIES - 1] = ldqe_available[`LMQ_ENTRIES - 1];
generate begin : lastMach
generate if(1) begin : lastMach
genvar ldq;
for (ldq = 0; ldq <= `LMQ_ENTRIES-2; ldq=ldq+1) begin : lastMach
assign ldqe_opposite_ptr[ldq] = &((~ldqe_available[ldq + 1:`LMQ_ENTRIES - 1])) & ldqe_available[ldq];
@ -1893,7 +1893,7 @@ assign lq_pc_ldq_quiesce_d = ldq_all_req_home & ctl_lsq_ldp_idle;
assign lq_pc_stq_quiesce_d = stq_ldq_empty;
assign lq_pc_pfetch_quiesce_d = ctl_lsq_pf_empty;

generate begin : loadQ
generate if(1) begin : loadQ
genvar ldq;
for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : loadQ
wire [0:3] ldqDummy;
@ -2170,7 +2170,7 @@ generate begin : loadQ
1'b0;

// Determine if this entry was for the CP_NEXT itag
begin : ldqeItagTid
if(1) begin : ldqeItagTid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : ldqeItagTid
assign ldqe_cpNext_tid[ldq][tid] = ldqe_thrd_id_q[ldq][tid] & (ldqe_itag_q[ldq] == iu_lq_cp_next_itag_q[tid]);
@ -2463,7 +2463,7 @@ end
assign lgqe_available = (~lgqe_valid_q);

assign lgqe_wrt_ptr[0] = lgqe_available[0];
generate begin : LgPriWrt
generate if(1) begin : LgPriWrt
genvar lgq;
for (lgq=1; lgq<`LGQ_ENTRIES; lgq=lgq+1) begin : LgPriWrt
assign lgqe_wrt_ptr[lgq] = &((~lgqe_available[0:lgq - 1])) & lgqe_available[lgq];
@ -2481,7 +2481,7 @@ assign ex4_lgqe_set_all = lgqe_wrt_ptr & {`LGQ_ENTRIES{ex4_ldreq_q}};
assign ex5_lgqe_set_all_d = ex4_lgqe_set_all;
assign ex5_lgqe_set_val_d = ex4_lgqe_set_val;

generate begin : load_gath_Q
generate if(1) begin : load_gath_Q
genvar lgq;
for (lgq=0; lgq<`LGQ_ENTRIES; lgq=lgq+1) begin : load_gath_Q

@ -2512,7 +2512,7 @@ generate begin : load_gath_Q
assign lgqe_ldTag_d[lgq] = ex4_lgqe_set_all[lgq] ? ldq_gath_Tag : lgqe_ldTag_q[lgq];

// create a 1-hot core tag for each gather queue entry
begin : ldq_gath_Tag_1hot_G
if(1) begin : ldq_gath_Tag_1hot_G
genvar ldq;
for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : ldq_gath_Tag_1hot_G
wire [0:3] ldqDummy;
@ -2578,7 +2578,7 @@ generate begin : load_gath_Q
assign lgqe_back_inv_flush_upd[lgq] = |((ldqe_back_inv_q | ldq_rel_l1_dump) & ldq_gath_Tag_1hot[lgq]);

// Determine if request is CP_NEXT itag
begin : lgqeItagTid
if(1) begin : lgqeItagTid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : lgqeItagTid
assign lgqe_cpNext_tid[lgq][tid] = lgqe_thrd_id_q[lgq][tid] & (lgqe_itag_q[lgq] == iu_lq_cp_next_itag_q[tid]);
@ -2741,7 +2741,7 @@ assign ex5_setHold = ex5_ldq_set_hold_q | ex5_ldq_full_set_hold;

// Set Thread Held Indicator
assign ldq_setHold_tid = ldq_hold_tid_q | {`THREADS{ex5_setHold}};
generate begin : holdTid
generate if(1) begin : holdTid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : holdTid
assign ldq_hold_tid[tid] = ctl_lsq_ex5_thrd_id[tid] ? ldq_setHold_tid[tid] : ldq_hold_tid_q[tid];
@ -2941,7 +2941,7 @@ assign fifo_ldq_req0_mkill = |(fifo_ldq_req_tid_q[0] & iu_lq_cp_flush_q);
assign fifo_ldq_req0_avail = (fifo_ldq_req_val_q[0] & ~fifo_ldq_req0_mkill) & ~fifo_ldq_req_pfetch_q[0];

// FIFO Control
generate begin : fifoCtrl
generate if(1) begin : fifoCtrl
genvar fifo;
for (fifo=0; fifo<`LMQ_ENTRIES; fifo=fifo+1) begin : fifoCtrl
// Fifo Entry Was Zapped
@ -2978,7 +2978,7 @@ assign fifo_ldq_req_val_d[`LMQ_ENTRIES-1] = (fifo_ldq_req_cntrl[`LMQ_ENTRIES-
1'b1;

// Rest of the entries of FIFO
generate begin : ldqFifo
generate if(1) begin : ldqFifo
genvar fifo;
for (fifo=0; fifo<=`LMQ_ENTRIES-2; fifo=fifo+1) begin : ldqFifo
assign fifo_ldq_req_tid_d[fifo] = (fifo_ldq_req_cntrl[fifo] == 2'b00) ? fifo_ldq_req_tid_q[fifo] :
@ -3111,7 +3111,7 @@ assign ldq_err_ecc_det_d = l2_rel2_resp_val_q & l2_lsq_resp_ecc_err;
assign ldq_err_ue_det_d = l2_rel2_resp_val_q & l2_lsq_resp_ecc_err_ue;

// 1-hot of quadword updated
generate begin : relDat
generate if(1) begin : relDat
genvar beat;
for (beat=0; beat<8; beat=beat+1) begin : relDat
wire [0:2] beatDummy;
@ -3528,7 +3528,7 @@ assign ldq_odq_upd_eccue = ldq_rel3_odq_eccue;
// followed by a Round Robin Scheme within each Group

// Expand LDQ to max supported
generate begin : cplExp
generate if(1) begin : cplExp
genvar grp;
for (grp=0; grp<=(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4; grp=grp+1) begin : cplExp
genvar b;
@ -3549,7 +3549,7 @@ endgenerate

// Entry Select within Group
// Round Robin Scheme within each 4 entries in a Group
generate begin : cplGrpEntry
generate if(1) begin : cplGrpEntry
genvar grp;
for (grp = 0; grp <= (`LMQ_ENTRIES + `LGQ_ENTRIES - 1)/4; grp = grp + 1) begin : cplGrpEntry
assign cpl_grpEntry_val[grp] = ldqe_remove[grp * 4:(grp * 4) + 3];
@ -3645,7 +3645,7 @@ endgenerate

// Group Select Between all Groups
// Round Robin Scheme within Groups
generate begin : cplGrp
generate if(1) begin : cplGrp
genvar grp;
for (grp=0; grp<=3; grp=grp+1) begin : cplGrp
if (grp <= (`LMQ_ENTRIES+`LGQ_ENTRIES- 1)/4) begin : grpExst
@ -3735,7 +3735,7 @@ always @(*) begin: cplGrpLqMux
end

// Completion Report has been sent
generate begin : credSent
generate if(1) begin : credSent
genvar grp;
for (grp = 0; grp <= (`LMQ_ENTRIES + `LGQ_ENTRIES - 1)/4; grp = grp + 1) begin : credSent
genvar ldq;
@ -4222,7 +4222,7 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_flush_reg(
.dout(iu_lq_cp_flush_q)
);

generate begin : iu_lq_cp_next_itag_tid
generate if(1) begin : iu_lq_cp_next_itag_tid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : iu_lq_cp_next_itag_tid
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_next_itag_reg(
@ -5226,7 +5226,7 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_pf
.dout(fifo_ldq_req_pfetch_q)
);

generate begin : fifo_ldq_req_tid
generate if(1) begin : fifo_ldq_req_tid
genvar ldq;
for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : fifo_ldq_req_tid
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_tid_reg(
@ -5251,7 +5251,7 @@ generate begin : fifo_ldq_req_tid
end
endgenerate

generate begin : fifo_ldq_req
generate if(1) begin : fifo_ldq_req
genvar ldq0;
for (ldq0=0; ldq0<`LMQ_ENTRIES; ldq0=ldq0+1) begin : fifo_ldq_req
tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_reg(
@ -5376,7 +5376,7 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_reset_cpl_
.dout(ldqe_reset_cpl_rpt_q)
);

generate begin : ldqe_iTag
generate if(1) begin : ldqe_iTag
genvar ldq1;
for (ldq1=0; ldq1<`LMQ_ENTRIES; ldq1=ldq1+1) begin : ldqe_iTag
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ldqe_iTag_reg(
@ -5401,7 +5401,7 @@ generate begin : ldqe_iTag
end
endgenerate

generate begin : ldqe_thrd_id
generate if(1) begin : ldqe_thrd_id
genvar ldq2;
for (ldq2=0; ldq2<`LMQ_ENTRIES; ldq2=ldq2+1) begin : ldqe_thrd_id
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldqe_thrd_id_reg(
@ -5426,7 +5426,7 @@ generate begin : ldqe_thrd_id
end
endgenerate

generate begin : ldqe_wimge
generate if(1) begin : ldqe_wimge
genvar ldq3;
for (ldq3=0; ldq3<`LMQ_ENTRIES; ldq3=ldq3+1) begin : ldqe_wimge
tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ldqe_wimge_reg(
@ -5510,7 +5510,7 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_pfetch_reg
.dout(ldqe_pfetch_q)
);

generate begin : ldqe_op_size
generate if(1) begin : ldqe_op_size
genvar ldq4;
for (ldq4=0; ldq4<`LMQ_ENTRIES; ldq4=ldq4+1) begin : ldqe_op_size
tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldqe_op_size_reg(
@ -5535,7 +5535,7 @@ generate begin : ldqe_op_size
end
endgenerate

generate begin : ldqe_tgpr
generate if(1) begin : ldqe_tgpr
genvar ldq5;
for (ldq5=0; ldq5<`LMQ_ENTRIES; ldq5=ldq5+1) begin : ldqe_tgpr
tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ldqe_tgpr_reg(
@ -5560,7 +5560,7 @@ generate begin : ldqe_tgpr
end
endgenerate

generate begin : ldqe_usr_def
generate if(1) begin : ldqe_usr_def
genvar ldq6;
for (ldq6=0; ldq6<`LMQ_ENTRIES; ldq6=ldq6+1) begin : ldqe_usr_def
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_usr_def_reg(
@ -5585,7 +5585,7 @@ generate begin : ldqe_usr_def
end
endgenerate

generate begin : ldqe_class_id
generate if(1) begin : ldqe_class_id
genvar ldq7;
for (ldq7=0; ldq7<`LMQ_ENTRIES; ldq7=ldq7+1) begin : ldqe_class_id
tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldqe_class_id_reg(
@ -5610,7 +5610,7 @@ generate begin : ldqe_class_id
end
endgenerate

generate begin : ldqe_perf_events
generate if(1) begin : ldqe_perf_events
genvar ldq7;
for (ldq7=0; ldq7<`LMQ_ENTRIES; ldq7=ldq7+1) begin : ldqe_perf_events
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_perf_events_reg(
@ -5635,7 +5635,7 @@ generate begin : ldqe_perf_events
end
endgenerate

generate begin : ldqe_dvc
generate if(1) begin : ldqe_dvc
genvar ldq8;
for (ldq8=0; ldq8<`LMQ_ENTRIES; ldq8=ldq8+1) begin : ldqe_dvc
tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldqe_dvc_reg(
@ -5660,7 +5660,7 @@ generate begin : ldqe_dvc
end
endgenerate

generate begin : ldqe_ttype
generate if(1) begin : ldqe_ttype
genvar ldq9;
for (ldq9=0; ldq9<`LMQ_ENTRIES; ldq9=ldq9+1) begin : ldqe_ttype
tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ldqe_ttype_reg(
@ -5685,7 +5685,7 @@ generate begin : ldqe_ttype
end
endgenerate

generate begin : ldqe_dacrw
generate if(1) begin : ldqe_dacrw
genvar ldq10;
for (ldq10=0; ldq10<`LMQ_ENTRIES; ldq10=ldq10+1) begin : ldqe_dacrw
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_dacrw_reg(
@ -5710,7 +5710,7 @@ generate begin : ldqe_dacrw
end
endgenerate

generate begin : ldqe_p_addr
generate if(1) begin : ldqe_p_addr
genvar ldq11;
for (ldq11=0; ldq11<`LMQ_ENTRIES; ldq11=ldq11+1) begin : ldqe_p_addr
tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ldqe_p_addr_reg(
@ -5835,7 +5835,7 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_back_inv_n
.dout(ldqe_back_inv_np1Flush_q)
);

generate begin : ldqe_beat_cntr
generate if(1) begin : ldqe_beat_cntr
genvar ldq12;
for (ldq12=0; ldq12<`LMQ_ENTRIES; ldq12=ldq12+1) begin : ldqe_beat_cntr
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_beat_cntr_reg(
@ -6000,7 +6000,7 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_algebraic_
.dout(ldqe_algebraic_q)
);

generate begin : ldqe_state
generate if(1) begin : ldqe_state
genvar ldq13;
for (ldq13=0; ldq13<`LMQ_ENTRIES; ldq13=ldq13+1) begin : ldqe_state
tri_rlmreg_p #(.WIDTH(7), .INIT(64), .NEEDS_SRESET(1)) ldqe_state_reg(
@ -6025,7 +6025,7 @@ generate begin : ldqe_state
end
endgenerate

generate begin : ldqe_sentRel_cntr
generate if(1) begin : ldqe_sentRel_cntr
genvar ldq;
for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : ldqe_sentRel_cntr
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_sentRel_cntr_reg(
@ -6109,7 +6109,7 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_valid_reg(
.dout(lgqe_valid_q)
);

generate begin : lgqe_iTag
generate if(1) begin : lgqe_iTag
genvar lgq;
for (lgq=0; lgq<`LGQ_ENTRIES; lgq=lgq+1) begin : lgqe_iTag
tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lgqe_iTag_reg(
@ -6134,7 +6134,7 @@ generate begin : lgqe_iTag
end
endgenerate

generate begin : lgqe_ldTag
generate if(1) begin : lgqe_ldTag
genvar lgq0;
for (lgq0=0; lgq0<`LGQ_ENTRIES; lgq0=lgq0+1) begin : lgqe_ldTag
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lgqe_ldTag_reg(
@ -6159,7 +6159,7 @@ generate begin : lgqe_ldTag
end
endgenerate

generate begin : lgqe_thrd_id
generate if(1) begin : lgqe_thrd_id
genvar lgq1;
for (lgq1=0; lgq1<`LGQ_ENTRIES; lgq1=lgq1+1) begin : lgqe_thrd_id
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lgqe_thrd_id_reg(
@ -6204,7 +6204,7 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_byte_swap_
.dout(lgqe_byte_swap_q)
);

generate begin : lgqe_op_size
generate if(1) begin : lgqe_op_size
genvar lgq2;
for (lgq2=0; lgq2<`LGQ_ENTRIES; lgq2=lgq2+1) begin : lgqe_op_size
tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) lgqe_op_size_reg(
@ -6229,7 +6229,7 @@ generate begin : lgqe_op_size
end
endgenerate

generate begin : lgqe_tgpr
generate if(1) begin : lgqe_tgpr
genvar lgq3;
for (lgq3=0; lgq3<`LGQ_ENTRIES; lgq3=lgq3+1) begin : lgqe_tgpr
tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) lgqe_tgpr_reg(
@ -6334,7 +6334,7 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_back_inv_n
.dout(lgqe_back_inv_np1Flush_q)
);

generate begin : lgqe_dacrw
generate if(1) begin : lgqe_dacrw
genvar lgq4;
for (lgq4=0; lgq4<`LGQ_ENTRIES; lgq4=lgq4+1) begin : lgqe_dacrw
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lgqe_dacrw_reg(
@ -6359,7 +6359,7 @@ generate begin : lgqe_dacrw
end
endgenerate

generate begin : lgqe_dvc
generate if(1) begin : lgqe_dvc
genvar lgq5;
for (lgq5=0; lgq5<`LGQ_ENTRIES; lgq5=lgq5+1) begin : lgqe_dvc
tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) lgqe_dvc_reg(
@ -6384,7 +6384,7 @@ generate begin : lgqe_dvc
end
endgenerate

generate begin : lgqe_p_addr
generate if(1) begin : lgqe_p_addr
genvar lgq6;
for (lgq6=0; lgq6<`LGQ_ENTRIES; lgq6=lgq6+1) begin : lgqe_p_addr
tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lgqe_p_addr_reg(
@ -6449,7 +6449,7 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_axu_reg(
.dout(lgqe_axu_q)
);

generate begin : lgqe_perf_events
generate if(1) begin : lgqe_perf_events
genvar lgq6;
for (lgq6=0; lgq6<`LGQ_ENTRIES; lgq6=lgq6+1) begin : lgqe_perf_events
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lgqe_perf_events_reg(
@ -8062,7 +8062,7 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_qHit_held_
.dout(ldqe_qHit_held_q)
);

generate begin : cpl_grpEntry_last_sel
generate if(1) begin : cpl_grpEntry_last_sel
genvar grp0;
for (grp0=0; grp0<=(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4; grp0=grp0+1) begin : cpl_grpEntry_last_sel
tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) cpl_grpEntry_last_sel_reg(

22
dev/verilog/work/lq_ldq_relq.v
Unescape Escape View File

@ -366,14 +366,14 @@ assign ldq_rel0_arb_val_d = |(ldqe_relBeats_val & ~ldqe_rel_eccdet);
assign ldq_rel1_rdat_sel_d = ldq_rel0_rdat_sel;
assign ldq_rel2_rdat_sel_d = ldq_rel1_rdat_sel_q;

generate begin : relQ
generate if(1) begin : relQ
genvar ldq;
for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : relQ

// Reload Data Beat Home
assign ldqe_rel_datSet[ldq] = ldq_rel1_beat_upd_q & {8{ldq_rel1_dbeat_val[ldq]}};

begin : relDatRetQ
if(1) begin : relDatRetQ
genvar beat;
for (beat=0; beat<8; beat=beat+1) begin : relDatRetQ
assign ldqe_rel_datClr[ldq][beat] = (ldq_rel2_beat_upd_q[beat] & ldq_rel2_entrySent[ldq] & ~ldq_rel2_blk_req) | ldqe_rel_eccdet[ldq];
@ -407,7 +407,7 @@ generate begin : relQ
// Select Beat from Available beats in Reload Arbiters
assign ldqe_relBeats_nxt[ldq][0] = ldqe_relBeats_avail[ldq][0];

begin : relSel genvar beat;
if(1) begin : relSel genvar beat;
for (beat=1; beat<8; beat=beat+1) begin : relSel
assign ldqe_relBeats_nxt[ldq][beat] = &(~ldqe_relBeats_avail[ldq][0:beat-1]) & ldqe_relBeats_avail[ldq][beat];
end
@ -444,7 +444,7 @@ endgenerate
// followed by a Round Robin Scheme within each Group

// Expand LDQ to max supported
generate begin : relExp
generate if(1) begin : relExp
genvar grp;
genvar b;
for (grp=0; grp<=(`LMQ_ENTRIES-1)/4; grp=grp+1) begin : relExp
@ -462,7 +462,7 @@ endgenerate

// Entry Select within Group
// Round Robin Scheme within each 4 entries in a Group
generate begin : relGrpEntry
generate if(1) begin : relGrpEntry
genvar grp;
for (grp=0; grp<=(`LMQ_ENTRIES-1)/4; grp=grp+1) begin : relGrpEntry
assign rel_grpEntry_val[grp] = {ldq_rel_arb_entry[4*grp+0], ldq_rel_arb_entry[4*grp+1], ldq_rel_arb_entry[4*grp+2], ldq_rel_arb_entry[4*grp+3]};
@ -514,7 +514,7 @@ endgenerate

// Group Select Between all Groups
// Round Robin Scheme within Groups
generate begin : relGrp
generate if(1) begin : relGrp
genvar grp;
for (grp=0; grp<=3; grp=grp+1) begin : relGrp
if (grp <= (`LMQ_ENTRIES - 1)/4) begin : grpExst
@ -548,7 +548,7 @@ assign rel_group_sel[3] = (rel_group_last_sel_q[0] & ~(|rel_group_val[1:2]) & re
(rel_group_last_sel_q[3] & ~(|rel_group_val[0:2]) & rel_group_val[3]);

// Reload Queue Entry Sent
generate begin : relSent
generate if(1) begin : relSent
genvar grp;
for (grp=0; grp<=(`LMQ_ENTRIES-1)/4; grp=grp+1) begin : relSent
genvar ldq;
@ -598,7 +598,7 @@ end
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Reload Data Array
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
generate begin : relq
generate if(1) begin : relq
genvar bb;
if (`RELQ_INCLUDE == 1) begin
tri_64x144_1r1w rdat(
@ -775,7 +775,7 @@ assign ldq_arb_rel2_rd_data = rel2_rd_data;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// REGISTERS
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
generate begin : ldqe_rel_datRet
generate if(1) begin : ldqe_rel_datRet
genvar ldq;
for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : ldqe_rel_datRet
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_datRet_reg(
@ -838,7 +838,7 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_beat_upd_reg(
.dout(ldq_rel2_beat_upd_q)
);

generate begin : ldqe_relAttempts
generate if(1) begin : ldqe_relAttempts
genvar ldq;
for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : ldqe_relAttempts
tri_rlmreg_p #(.WIDTH(3), .INIT(7), .NEEDS_SRESET(1)) ldqe_relAttempts_reg(
@ -958,7 +958,7 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_cTag_reg(
.dout(ldq_rel0_arb_cTag_q)
);

generate begin : rel_grpEntry_last_sel
generate if(1) begin : rel_grpEntry_last_sel
genvar grp;
for (grp=0; grp<=(`LMQ_ENTRIES-1)/4; grp=grp+1) begin : rel_grpEntry_last_sel
tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) rel_grpEntry_last_sel_reg(

12
dev/verilog/work/lq_ldq_rot.v
Unescape Escape View File

@ -199,7 +199,7 @@ assign tiup = 1'b1;
// #############################################################################################

// Thread Unpack
generate begin : sprTid
generate if(1) begin : sprTid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid
assign ctl_lsq_spr_dbcr2_dvc1be_int[tid] = ctl_lsq_spr_dbcr2_dvc1be[8*tid:8*(tid+1)-1];
@ -211,7 +211,7 @@ generate begin : sprTid
endgenerate

// Swizzle Rotate Data
generate begin : swzlRelData
generate if(1) begin : swzlRelData
genvar t;
for (t=0; t<8; t=t+1) begin : swzlRelData
assign rel1_data_swzl[t*16:(t*16)+15] = {ldq_rel1_data[t+0], ldq_rel1_data[t+8], ldq_rel1_data[t+16], ldq_rel1_data[t+24],
@ -223,7 +223,7 @@ generate begin : swzlRelData
endgenerate

// Reload Data Rotate
generate begin : rrotl
generate if(1) begin : rrotl
genvar b;
for (b=0; b<8; b=b+1) begin : rrotl
tri_rot16_lu drotl(
@ -302,7 +302,7 @@ assign rel1_bittype_mask = (16'h0001 & {16{rel1_1hot_opsize[4]}}) | (16'h0003 &
(16'h000F & {16{rel1_1hot_opsize[2]}}) | (16'h00FF & {16{rel1_1hot_opsize[1]}}) |
(16'hFFFF & {16{rel1_1hot_opsize[0]}});

generate begin : maskGen
generate if(1) begin : maskGen
genvar b;
for (b=0; b <8; b=b+1) begin : maskGen
assign rel1_optype_mask[b*16:(b*16)+15] = rel1_bittype_mask;
@ -321,7 +321,7 @@ assign lw_algebraic_msk = {{32{rel1_alg_bit}}, 16'h0000};
assign rel1_algebraic_msk = (lh_algebraic_msk & {48{lh_algebraic}}) | (lw_algebraic_msk & {48{lw_algebraic}});

// Swizzle Data to a proper format
generate begin : swzlData
generate if(1) begin : swzlData
genvar t;
for (t=0; t<16; t=t+1) begin : swzlData
assign rel1_swzl_data[t*8:(t*8)+7] = {rel1_msk_data[t], rel1_msk_data[t+16], rel1_msk_data[t+32], rel1_msk_data[t+48],
@ -341,7 +341,7 @@ assign rel2_dvc1_val_d = ldq_rel1_gpr_val & ldq_rel1_dvc1_en;
assign rel2_dvc2_val_d = ldq_rel1_gpr_val & ldq_rel1_dvc2_en;

// Reload Data Compare
generate begin : dvcCmpRl
generate if(1) begin : dvcCmpRl
genvar t;
for (t = 0; t <= ((2 ** `GPR_WIDTH_ENC)/8) - 1; t = t + 1) begin : dvcCmpRl
assign rel2_dvc1_cmp[t] = (rel2_rot_data_q[(128 - (2 ** `GPR_WIDTH_ENC)) + t * 8:(128 - (2 ** `GPR_WIDTH_ENC)) + ((t * 8) + 7)] ==

45
dev/verilog/work/lq_odq.v
Unescape Escape View File

@ -772,8 +772,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
assign tidn = 1'b0;

// This is used to convert the wide vector port inputs into an internal 2 dimesional array format
generate
begin : ports
generate if(1) begin : ports
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : convert
@ -876,8 +875,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
assign instr1_vld = |(ex1_i1_vld_q & (~(cp_flush_q | cp_flush2_q | cp_flush3_q | cp_flush4_q | cp_flush5_q)));


generate
begin : fcf
generate if(1) begin : fcf
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : flushCredFree
@ -967,8 +965,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)



generate
begin : gen_a
generate if(1) begin : gen_a
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : gen_a
@ -1169,8 +1166,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
// with these 2 itags, we can determine the AGE of a load with respect to the store queue

// Determine Closest Youngest Store
generate
begin : ady
generate if(1) begin : ady
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : ageDetectYoung
@ -1212,8 +1208,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
endgenerate

// Determine Closest Oldest Store
generate
begin : ado
generate if(1) begin : ado
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : ageDetectOld
@ -1268,8 +1263,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//
// Determine if we have a load colliding with an incomming store that is older than it, these need to be flushed
//
generate
begin : flush_a
generate if(1) begin : flush_a
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : flush_a
@ -1316,8 +1310,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
assign lq_iu_credit_free_d = (remove_tid & {`THREADS{compress_val}}) | flush_credit_free;
assign lq_iu_credit_free = lq_iu_credit_free_q;

generate
begin : compVect
generate if(1) begin : compVect
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : compVect
@ -1341,8 +1334,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//flush_vector <= flush_vector_pre(1 to `LDSTQ_ENTRIES-1) & '0' when (compress_val = '1') else
assign flush_vector = flush_vector_pre;

generate
begin : cmp_loop
generate if(1) begin : cmp_loop
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : cmp_loop
@ -1465,8 +1457,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//
assign collision_vector_new = (compress_val_q == 1'b0) ? collision_vector_q :
{collision_vector_q[1:`LDSTQ_ENTRIES - 1], 1'b0};
generate
begin : gen_ops
generate if(1) begin : gen_ops
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : gen_ops
@ -1477,8 +1468,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
endgenerate

//collision_check_mask(0) <= '0';
generate
begin : col_det_g
generate if(1) begin : col_det_g
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : col_det_g
@ -1495,8 +1485,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
forw_collisions_ahead[0] = tidn;
end

generate
begin : col_det_f
generate if(1) begin : col_det_f
genvar entry;
for (entry = 1; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : col_det_f
@ -1587,8 +1576,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
addrq_entry_bytemask_next[`LDSTQ_ENTRIES] = {16{tidn}};
end

generate
begin : gen_b
generate if(1) begin : gen_b
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : gen_b
@ -1650,8 +1638,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
end
endgenerate

generate
begin : cmp2_loop
generate if(1) begin : cmp2_loop
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : cmp2_loop
@ -1789,8 +1776,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

generate
begin : urld_gen
generate if(1) begin : urld_gen
genvar entry;
for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : urld_gen
@ -1860,8 +1846,7 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
// For now I am choosing option 3 at it will be the best timing and still gets most of the benefit from removing the flushed entries
// from the middle. I will check ldq_odq_vld and only allow a flushed entry removal from the middle if this value is 0.
//
generate
begin : rld_gen
generate if(1) begin : rld_gen
genvar entry;
for (entry = 1; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1)
begin : rld_gen

5
dev/verilog/work/lq_perv.v
Unescape Escape View File

@ -354,8 +354,7 @@ assign unused = (|perf_event_mux_ctrl) | clkoff_dc_b_int[1] | d_mode_dc_int[1] |
// Debug Bus Control Logic
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

generate
begin : dbgData
generate if(1) begin : dbgData
genvar bus;
for (bus=0; bus<32; bus=bus+1) begin : dbgData
assign lq_dbg_data_mux1[bus] = lq_debug_bus0;
@ -475,7 +474,7 @@ assign perf_event_en_d = ( spr_msr_pr_q & {`THREADS{pc_lq_event_
// Muxing
assign perf_event_mux_ctrl = {ctl_perv_spr_lesr1, ctl_perv_spr_lesr2};

generate begin : TidPerf
generate if(1) begin : TidPerf
genvar tid;
for (tid=0;tid<`THREADS;tid=tid+1) begin : TidPerf
// Generate Events Per Thread

24
dev/verilog/work/lq_pfetch.v
Unescape Escape View File

@ -587,8 +587,7 @@ module lq_pfetch(
// SPR for prefetch depth
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : sprThrd
@ -938,8 +937,7 @@ module lq_pfetch(
assign pf_iar_i0_wen[0] = new_itag_i0_val & (pf_iar_tbl_val_q[0] == 1'b0);
assign pf_iar_i0_wen[1] = new_itag_i0_val & (pf_iar_tbl_val_q[0:1] == 2'b10);

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 2; i <= `LDSTQ_ENTRIES - 1; i = i + 1)
begin : pf_iar_i0_wen_gen
@ -953,8 +951,7 @@ module lq_pfetch(
assign pf_iar_i1_wen[0] = new_itag_i1_val & (pf_iar_val_for_i1[0] == 1'b0);
assign pf_iar_i1_wen[1] = new_itag_i1_val & (pf_iar_val_for_i1[0:1] == 2'b10);

generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar i;
for (i = 2; i <= `LDSTQ_ENTRIES - 1; i = i + 1)
begin : pf_iar_i1_wen_gen
@ -1025,8 +1022,7 @@ module lq_pfetch(
.dout(odq_report_tid_q)
);

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar i;
for (i = 0; i <= `LDSTQ_ENTRIES - 1; i = i + 1)
begin : done_itag_match_gen
@ -1037,8 +1033,7 @@ module lq_pfetch(
end
endgenerate

generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar i;
for (i = 0; i <= `LDSTQ_ENTRIES - 1; i = i + 1)
begin : pf_iar_table
@ -1145,8 +1140,7 @@ module lq_pfetch(
// lookup iar from itag-iar table
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

generate
begin : xhdl5
generate if(1) begin : xhdl5
genvar i;
for (i = 0; i <= `LDSTQ_ENTRIES - 1; i = i + 1)
begin : new_itag_match_gen
@ -2446,8 +2440,7 @@ module lq_pfetch(
(pf2_hits_q[0:1] == 2'b10) ? 1'b1 :
(~old_rpt_lru);

generate
begin : xhdl6
generate if(1) begin : xhdl6
genvar i;
for (i = 0; i <= 31; i = i + 1)
begin : rpt_lru_gen
@ -2502,8 +2495,7 @@ module lq_pfetch(

assign pf1_new_data_ea = pf1_data_ea_q + ({ {59-21-1-(64-(2**`GPR_WIDTH_ENC))+1{pf1_rpt_stride_q[0]}}, pf1_rpt_stride_q });

generate
begin : xhdl7
generate if(1) begin : xhdl7
genvar i;
for (i = 0; i <= `PFETCH_Q_SIZE - 1; i = i + 1)
begin : pfq_gen

2
dev/verilog/work/lq_spr.v
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@ -374,7 +374,7 @@ lq_spr_cspr #(.hvmode(hvmode), .a2mode(a2mode)) lq_spr_cspr(
.gnd(gnd)
);

generate begin : thread
generate if(1) begin : thread
genvar t;
for (t=0; t<`THREADS; t=t+1) begin : thread
lq_spr_tspr #(.hvmode(hvmode), .a2mode(a2mode)) lq_spr_tspr(

12
dev/verilog/work/lq_spr_cspr.v
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@ -446,7 +446,7 @@ assign ex3_dac4_cmpr_sel = (ex3_dac34m_q[0] == 1'b0) ? ex3_dac4_cmpr :
ex3_dac3_cmpr;

// Determine if DAC is enabled for this thread
generate begin : sprTidOut
generate if(1) begin : sprTidOut
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTidOut
assign dbcr0_dac1_int[tid*2:(tid*2)+1] = dbcr0_dac1_q[tid];
@ -516,7 +516,7 @@ lq_spr_dacen lq_spr_dac4en(
.dacw_en(ex3_dac4w_en)
);

generate begin : lq_spr_dvc_cmp
generate if(1) begin : lq_spr_dvc_cmp
genvar t;
for (t = 0; t <= `THREADS - 1; t = t + 1) begin : lq_spr_dvc_cmp
assign dbcr2_dvc1m_on_d[t] = |(tspr_cspr_dbcr2_dvc1m_int[t]) & |(tspr_cspr_dbcr2_dvc1be_int[t][8 - `GPR_WIDTH/8:7]);
@ -1252,7 +1252,7 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_val_latch(
.din(ex3_val),
.dout(ex4_val_q)
);
generate begin : dbcr0_dac1
generate if(1) begin : dbcr0_dac1
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac1

@ -1277,7 +1277,7 @@ generate begin : dbcr0_dac1
end
end
endgenerate
generate begin : dbcr0_dac2
generate if(1) begin : dbcr0_dac2
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac2

@ -1302,7 +1302,7 @@ generate begin : dbcr0_dac2
end
end
endgenerate
generate begin : dbcr0_dac3
generate if(1) begin : dbcr0_dac3
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac3

@ -1327,7 +1327,7 @@ generate begin : dbcr0_dac3
end
end
endgenerate
generate begin : dbcr0_dac4
generate if(1) begin : dbcr0_dac4
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac4


4
dev/verilog/work/lq_spr_dacen.v
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@ -75,7 +75,7 @@ wire [0:`THREADS-1] dac_st_en;
wire [0:`THREADS-1] dac_us_en;
wire [0:`THREADS-1] dac_er_en;

generate begin : sprTid
generate if(1) begin : sprTid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid
assign spr_dbcr0_dac_tid[tid] = spr_dbcr0_dac[tid*2:tid*2+1];
@ -85,7 +85,7 @@ generate begin : sprTid
end
endgenerate

generate begin : dacen_gen
generate if(1) begin : dacen_gen
genvar t;
for (t = 0; t <= `THREADS - 1; t = t + 1) begin : dacen_gen
assign dac_ld_en[t] = spr_dbcr0_dac_tid[t][0] & load;

169
dev/verilog/work/lq_stq.v
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@ -1486,8 +1486,7 @@ module lq_stq(
//!! Bugspray Include: lq_stq

// This is used to convert the wide vector port inputs into an internal 2 dimesional array format
generate
begin : ports
generate if(1) begin : ports
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : convert
@ -1569,8 +1568,7 @@ module lq_stq(

// I0 starts at the beginning of the TAG queue and works its way to the end, it looks for the first available
assign stq_wrt_i0_ptr[0] = stq_tag_available[0];
generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar stq;
for (stq = 1; stq <= `STQ_ENTRIES - 1; stq = stq + 1)
begin : stqI0Wrt
@ -1581,8 +1579,7 @@ module lq_stq(

// I1 starts at the end of the TAG queue and works its way to the beginning, it looks for the first available entry
assign stq_wrt_i1_ptr[`STQ_ENTRIES - 1] = stq_tag_available[`STQ_ENTRIES - 1];
generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar stq;
for (stq = 0; stq <= `STQ_ENTRIES - 2; stq = stq + 1)
begin : stqI1Wrt
@ -1612,8 +1609,7 @@ module lq_stq(
stq3_cmmt_tag = cmmtTag;
end

generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar stq;
for (stq = 0; stq <= `STQ_ENTRIES - 1; stq = stq + 1)
begin : stqTagAlloc
@ -1757,8 +1753,7 @@ module lq_stq(

assign cpl_ready = (~(|(cp_flush_q & cpl_ready_tid_final))) & (~(|(any_ack_val))) & |(stqe_need_ready & stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1] & (stqe_dreq_val_q[0:`STQ_ENTRIES - 1] | stqe_dvc_int_det | ((~stqe_need_ext_ack_q[0:`STQ_ENTRIES - 1]))));

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : skip_ready_gen
@ -1802,8 +1797,7 @@ module lq_stq(
// (probably overkill on the latches here, but I'll leave it)
assign hwsync_ack = an_ac_sync_ack; // and or_reduce(stqe_is_sync_q(0 to `STQ_ENTRIES-1) and stqe_l_zero and stqe_need_ready_ptr_q(0 to `STQ_ENTRIES-1));

generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar t;
for (t = 0; t <= `THREADS - 1; t = t + 1)
begin : sync_thrd_gen
@ -1841,7 +1835,7 @@ module lq_stq(

assign sync_ack[0] = sync_ack_all[0];
generate // this logic only works for 1 or 2 `THREADS
begin : xhdl5
if(1) begin : xhdl5
genvar t;
for (t = 1; t <= `THREADS - 1; t = t + 1)
begin : sync_ack_thrd_gen
@ -1860,7 +1854,7 @@ module lq_stq(

assign cr_ack[0] = cr_ack_q[0] & (~cr_block[0]) & (~(|(sync_ack_all)));
generate // this logic only works for 1 or 2 `THREADS
begin : xhdl6
if(1) begin : xhdl6
genvar t;
for (t = 1; t <= `THREADS - 1; t = t + 1)
begin : cr_ack_thrd_gen
@ -1889,7 +1883,7 @@ module lq_stq(
assign any_ack_val[0] = any_ack_hold_q[0] & (~ctl_lsq_stq_cpl_blk);

generate // this logic only works for 1 or 2 `THREADS
begin : xhdl7
if(1) begin : xhdl7
genvar t;
for (t = 1; t <= `THREADS - 1; t = t + 1)
begin : any_ack_val_thrd_gen
@ -2017,8 +2011,7 @@ module lq_stq(

assign stqe0_icswxdot_val = stqe_is_icswxr_q[0] & (stqe_ttype_q[0] == 6'b100111);

generate
begin : xhdl8
generate if(1) begin : xhdl8
genvar t;
for (t = 0; t <= `THREADS - 1; t = t + 1)
begin : ext_ack_queue_gen
@ -2367,8 +2360,7 @@ module lq_stq(
set_stqe_odq_resolved[0:`STQ_ENTRIES - 1] = odq_resolved_ptr & {`STQ_ENTRIES{odq_stq_resolved}};
end

generate
begin : xhdl9
generate if(1) begin : xhdl9
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stq_addr_entry_gen
@ -2644,8 +2636,7 @@ module lq_stq(
// 1 0 Stores are older from Oldest_Itag as upper bound, including Oldest_Itag
// 1 1 Stores are older from Oldest_Itag as upper bound, including Oldest_Itag
// Need to validate the oldest entries
generate
begin : xhdl10
generate if(1) begin : xhdl10
genvar stq;
for (stq = 0; stq <= `STQ_ENTRIES - 1; stq = stq + 1)
begin : ageExpand
@ -2701,7 +2692,7 @@ module lq_stq(
assign ex4_req_opsize_1hot[4] = ex4_req_opsize_q == 3'b001; // 1B
assign ex4_req_opsize1 = ~ex4_req_opsize_q[0] & ex4_req_opsize_q[2];

generate begin : xhdl12
generate if(1) begin : xhdl12
genvar i;
genvar b;

@ -2898,7 +2889,7 @@ module lq_stq(
assign ex3_ex4_byte_en_hit = |(ctl_lsq_ex3_byte_en & ex4_req_byte_en_q);

// compare the forwardable entries to each other to determine the forwarding priority mask
generate begin : fwd_pri_gen_l1
generate if(1) begin : fwd_pri_gen_l1
genvar i;
for (i = 0; i <= `STQ_FWD_ENTRIES - 1; i = i + 1) begin : fwd_pri_gen_l1
always @(*) begin: fwd_pri_gen_l2
@ -3135,8 +3126,7 @@ module lq_stq(
assign ex3_axu_val = |(ex3_axu_val_q);
assign ex4_axu_val_d = ex3_axu_val_q & (~cp_flush_q);

generate
begin : xhdl14
generate if(1) begin : xhdl14
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stq_data_entry_gen
@ -4114,8 +4104,7 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_ack_rcvd_l
.din(stqe_ack_rcvd_d),
.dout(stqe_ack_rcvd_q[0:`STQ_ENTRIES - 1])
);
generate
begin : xhdl15
generate if(1) begin : xhdl15
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_lmqhit_latch_gen
@ -4141,8 +4130,7 @@ generate
end
end
endgenerate
generate
begin : xhdl16
generate if(1) begin : xhdl16
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_need_ext_ack_latch_gen
@ -4169,8 +4157,7 @@ generate
end
endgenerate

generate
begin : stqe_blk_loads_latch_gen
generate if(1) begin : stqe_blk_loads_latch_gen
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) begin : stqe_blk_loads_latch_gen

@ -4196,8 +4183,7 @@ generate
end
endgenerate

generate
begin : xhdl57
generate if(1) begin : xhdl57
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_all_thrd_chk_latch_gen
@ -4224,8 +4210,7 @@ generate
end
endgenerate

generate
begin : xhdl17
generate if(1) begin : xhdl17
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_itag_latch_gen
@ -4252,8 +4237,7 @@ generate
end
end
endgenerate
generate
begin : xhdl18
generate if(1) begin : xhdl18
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_addr_latch_gen
@ -4279,8 +4263,7 @@ generate
end
end
endgenerate
generate
begin : xhdl19
generate if(1) begin : xhdl19
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_rotcmp_latch_gen
@ -4306,8 +4289,7 @@ generate
end
end
endgenerate
generate
begin : xhdl20
generate if(1) begin : xhdl20
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_cline_chk_latch_gen
@ -4333,8 +4315,7 @@ generate
end
end
endgenerate
generate
begin : xhdl21
generate if(1) begin : xhdl21
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_ttype_latch_gen
@ -4360,8 +4341,7 @@ generate
end
end
endgenerate
generate
begin : xhdl22
generate if(1) begin : xhdl22
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_byte_en_latch_gen
@ -4387,8 +4367,7 @@ generate
end
end
endgenerate
generate
begin : xhdl23
generate if(1) begin : xhdl23
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_wimge_latch_gen
@ -4414,8 +4393,7 @@ generate
end
end
endgenerate
generate
begin : xhdl24
generate if(1) begin : xhdl24
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_byte_swap_latch_gen
@ -4441,8 +4419,7 @@ generate
end
end
endgenerate
generate
begin : xhdl25
generate if(1) begin : xhdl25
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_opsize_latch_gen
@ -4468,8 +4445,7 @@ generate
end
end
endgenerate
generate
begin : xhdl26
generate if(1) begin : xhdl26
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_axu_val_latch_gen
@ -4495,8 +4471,7 @@ generate
end
end
endgenerate
generate
begin : xhdl27
generate if(1) begin : xhdl27
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_epid_val_latch_gen
@ -4522,8 +4497,7 @@ generate
end
end
endgenerate
generate
begin : xhdl28
generate if(1) begin : xhdl28
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_usr_def_latch_gen
@ -4549,8 +4523,7 @@ generate
end
end
endgenerate
generate
begin : xhdl29
generate if(1) begin : xhdl29
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_is_store_latch_gen
@ -4576,8 +4549,7 @@ generate
end
end
endgenerate
generate
begin : xhdl30
generate if(1) begin : xhdl30
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_is_sync_latch_gen
@ -4603,8 +4575,7 @@ generate
end
end
endgenerate
generate
begin : xhdl31
generate if(1) begin : xhdl31
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_is_resv_latch_gen
@ -4630,8 +4601,7 @@ generate
end
end
endgenerate
generate
begin : xhdl32
generate if(1) begin : xhdl32
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_is_icswxr_latch_gen
@ -4657,8 +4627,7 @@ generate
end
end
endgenerate
generate
begin : xhdl33
generate if(1) begin : xhdl33
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_is_icbi_latch_gen
@ -4684,8 +4653,7 @@ generate
end
end
endgenerate
generate
begin : xhdl34
generate if(1) begin : xhdl34
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_is_inval_op_latch_gen
@ -4711,8 +4679,7 @@ generate
end
end
endgenerate
generate
begin : xhdl35
generate if(1) begin : xhdl35
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_dreq_val_latch_gen
@ -4738,8 +4705,7 @@ generate
end
end
endgenerate
generate
begin : xhdl36
generate if(1) begin : xhdl36
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_has_data_latch_gen
@ -4765,8 +4731,7 @@ generate
end
end
endgenerate
generate
begin : xhdl37
generate if(1) begin : xhdl37
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_send_l2_latch_gen
@ -4792,8 +4757,7 @@ generate
end
end
endgenerate
generate
begin : xhdl38
generate if(1) begin : xhdl38
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_lock_clr_latch_gen
@ -4819,8 +4783,7 @@ generate
end
end
endgenerate
generate
begin : xhdl39
generate if(1) begin : xhdl39
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_watch_clr_latch_gen
@ -4846,8 +4809,7 @@ generate
end
end
endgenerate
generate
begin : xhdl40
generate if(1) begin : xhdl40
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_l_fld_latch_gen
@ -4873,8 +4835,7 @@ generate
end
end
endgenerate
generate
begin : xhdl41
generate if(1) begin : xhdl41
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_thrd_id_latch_gen
@ -4900,8 +4861,7 @@ generate
end
end
endgenerate
generate
begin : xhdl42
generate if(1) begin : xhdl42
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_tgpr_latch_gen
@ -4927,8 +4887,7 @@ generate
end
end
endgenerate
generate
begin : xhdl43
generate if(1) begin : xhdl43
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_dvc_en_latch_gen
@ -4954,8 +4913,7 @@ generate
end
end
endgenerate
generate
begin : xhdl44
generate if(1) begin : xhdl44
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_dacrw_latch_gen
@ -4981,8 +4939,7 @@ generate
end
end
endgenerate
generate
begin : xhdl45
generate if(1) begin : xhdl45
genvar i;
for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1)
begin : stqe_dvcr_cmpr_latch_gen
@ -5008,8 +4965,7 @@ generate
end
end
endgenerate
generate
begin : xhdl47
generate if(1) begin : xhdl47
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_qHit_held_latch_gen
@ -5035,8 +4991,7 @@ generate
end
end
endgenerate
generate
begin : xhdl48
generate if(1) begin : xhdl48
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_held_early_clr_latch_gen
@ -5062,8 +5017,7 @@ generate
end
end
endgenerate
generate
begin : xhdl49
generate if(1) begin : xhdl49
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stqe_data1_latch_gen
@ -5185,8 +5139,7 @@ generate
.dout(cp_next_val_q)
);

generate
begin : xhdl50
generate if(1) begin : xhdl50
genvar i;
for (i = 0; i <= `THREADS-1; i = i + 1)
begin : cp_next_itag_latch_gen
@ -5230,8 +5183,7 @@ generate
.din(iu_lq_i0_completed),
.dout(cp_i0_completed_q)
);
generate
begin : xhdl51
generate if(1) begin : xhdl51
genvar i;
for (i = 0; i <= `THREADS-1; i = i + 1)
begin : cp_i0_completed_itag_latch_gen
@ -5275,8 +5227,7 @@ generate
.din(iu_lq_i1_completed),
.dout(cp_i1_completed_q)
);
generate
begin : xhdl52
generate if(1) begin : xhdl52
genvar i;
for (i = 0; i <= `THREADS-1; i = i + 1)
begin : cp_i1_completed_itag_latch_gen
@ -6176,8 +6127,7 @@ generate
);


generate
begin : xhdl53
generate if(1) begin : xhdl53
genvar i;
for (i = 0; i <= `THREADS-1; i = i + 1)
begin : ext_ack_queue_itag_latch_gen
@ -6203,8 +6153,7 @@ generate
end
end
endgenerate
generate
begin : xhdl54
generate if(1) begin : xhdl54
genvar i;
for (i = 0; i <= `THREADS-1; i = i + 1)
begin : ext_ack_queue_cr_wa_latch_gen
@ -6230,8 +6179,7 @@ generate
end
end
endgenerate
generate
begin : xhdl55
generate if(1) begin : xhdl55
genvar i;
for (i = 0; i <= `THREADS-1; i = i + 1)
begin : ext_ack_queue_dacrw_det_latch_gen
@ -7700,8 +7648,7 @@ generate
.din(stq_tag_val_d),
.dout(stq_tag_val_q)
);
generate
begin : xhdl56
generate if(1) begin : xhdl56
genvar i;
for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1)
begin : stq_tag_ptr_latch_gen

9
dev/verilog/work/mmq.v
Unescape Escape View File

@ -1267,8 +1267,7 @@ module mmq(


// input port threadwise widening `THREADS(n) -> `MM_THREADS(m)
generate
begin : xhdl0
generate if(1) begin : xhdl0
// genvar tid;
for (tid = 0; tid <= `MM_THREADS-1; tid = tid + 1)
begin : mmThreads
@ -1320,8 +1319,7 @@ module mmq(
end
endgenerate

generate
begin : xhdl1
generate if(1) begin : xhdl1
// genvar tid;
for (tid = 0; tid <= `THDID_WIDTH - 1; tid = tid + 1)
begin : mmDbgThreads
@ -1339,8 +1337,7 @@ module mmq(
end
endgenerate

generate
begin : xhdl2
generate if(1) begin : xhdl2
// genvar tid;
for (tid = 0; tid <= `THDID_WIDTH - 1; tid = tid + 1)
begin : mmperfThreads

3
dev/verilog/work/mmq_dbg.v
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@ -798,8 +798,7 @@ module mmq_dbg(
assign dbg_group4[58] = xu_mm_lmq_stq_empty;
assign dbg_group4[59] = iu_mm_lmq_empty;

generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar tid;
for (tid = 0; tid <= 3; tid = tid + 1)
begin : Grp4Threads

10
dev/verilog/work/mmq_spr.v
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@ -1125,8 +1125,7 @@ module mmq_spr(
assign spr_etid_int_onehot[2] = (spr_etid_int_q == 2'b10);
assign spr_etid_int_onehot[3] = (spr_etid_int_q == 2'b11);

generate
begin : etid_generate
generate if(1) begin : etid_generate
genvar tid;
for (tid = 0; tid <= 3; tid = tid + 1)
begin : mmqsprflush
@ -1148,8 +1147,7 @@ module mmq_spr(
endgenerate

`ifdef WAIT_UPDATES
generate
begin : mmq_spr_tid_generate
generate if(1) begin : mmq_spr_tid_generate
genvar tid;
for (tid = 0; tid <= `MM_THREADS-1; tid = tid + 1)
begin : mmThreads
@ -1173,8 +1171,8 @@ assign xu_mm_derat_mmucr1_we_d = xu_mm_derat_mmucr1_we;
assign cp_flush_p1_d = cp_flush_q;
assign cp_flush_p1 = cp_flush_p1_q;

//masthdNExist : if `THDID_WIDTH > (`MM_THREADS) generate begin
// masthdunused : for tid in (`MM_THREADS) to (`THDID_WIDTH-1) generate begin
//masthdNExist : if `THDID_WIDTH > (`MM_THREADS) generate if(1) begin
// masthdunused : for tid in (`MM_THREADS) to (`THDID_WIDTH-1) generate if(1) begin
// unused_dc_thdid(tid) <= lrat_mas_thdid(tid) or tlb_lper_we_upd(tid) or tlb_delayed_act(tid+29);
// end generate masthdunused;
//end generate masthdNExist;

2
dev/verilog/work/mmq_tlb_ctl.v
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@ -3408,7 +3408,7 @@ module mmq_tlb_ctl(
generate
if (`THDID_WIDTH > `MM_THREADS)
begin : tlbctlthdNExist
begin : xhdl0
if(1) begin : xhdl0
genvar tid;
for (tid = `MM_THREADS; tid <= (`THDID_WIDTH - 1); tid = tid + 1)
begin : tlbctlthdunused

3
dev/verilog/work/mmq_tlb_lrat.v
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@ -1856,8 +1856,7 @@ module mmq_tlb_lrat(
`endif
assign unused_dc[13] = ex6_illeg_instr[0];

generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar tid;
for (tid = 0; tid <= `THDID_WIDTH - 1; tid = tid + 1)
begin : lratunused

12
dev/verilog/work/rv_barf.v
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@ -150,8 +150,7 @@ module rv_barf(
// Write aoi
//-------------------------------------------------------------------------------------------------------

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar n;
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_dat_gen
@ -173,8 +172,7 @@ module rv_barf(
// Read Mux
//-------------------------------------------------------------------------------------------------------

generate
begin : xhdl1r
generate if(1) begin : xhdl1r
genvar n, b;
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : rgene
@ -192,8 +190,7 @@ module rv_barf(
end
endgenerate

generate
begin : xhdl1o
generate if(1) begin : xhdl1o
genvar b;
for (b = 0; b <= (q_dat_width_g - 1); b = b + 1)
begin : rgeneo
@ -208,8 +205,7 @@ module rv_barf(
//-------------------------------------------------------------------------------------------------------
// storage elements
//-------------------------------------------------------------------------------------------------------
generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar n;
for (n = 0; n <= q_num_entries_g - 1; n = n + 1)
begin : q_x_q_gen

3
dev/verilog/work/rv_cmpitag.v
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@ -92,8 +92,7 @@ module rv_cmpitag(
// Total Logic: XOR + 6 levels
//-------------------------------------------------------------------------------------------------------

generate
begin : xhdl0
generate if(1) begin : xhdl0
genvar n;
for (n = 0; n <= 5; n = n + 1)
begin : q_valid_gen

6
dev/verilog/work/rv_dep_scard.v
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@ -201,8 +201,7 @@ module rv_dep_scard(
// Set the target if t_v is valid and clear the valid if any of the target busses match
//------------------------------------------------------------------------------------------------------------

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i <= num_entries_g - 1; i = i + 1)
begin : g0
@ -242,8 +241,7 @@ module rv_dep_scard(
//------------------------------------------------------------------------------------------------------------
// Mux out the itag
//------------------------------------------------------------------------------------------------------------
generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar i;
for (i = 0; i <= num_entries_g - 1; i = i + 1)
begin : g1

3
dev/verilog/work/rv_primux.v
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@ -215,8 +215,7 @@ module rv_primux(
//-------------------------------------------------------------------------------------------------------
// Instruction Muxing
//-------------------------------------------------------------------------------------------------------
generate
begin : xhdl
generate if(1) begin : xhdl
for (n = 0; n <= (q_dat_width_g - 1); n = n + 1)
begin : gendat


117
dev/verilog/work/rv_rf_byp.v
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@ -776,8 +776,7 @@ module rv_rf_byp(
assign fxu1_s2_d = {(rv_byp_fx1_vld & (~(cp_flush_q))), rv_byp_fx1_s2_t};
assign fxu1_s3_d = {(rv_byp_fx1_vld & (~(cp_flush_q))), rv_byp_fx1_s3_t};

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 1; i <= 4; i = i + 1)
begin : fxu0_pipe_t_gen
@ -802,8 +801,7 @@ module rv_rf_byp(
(({((fxu0_t3_q[7][0:`THREADS - 1] | fx0_byp_rdy_nxt[7]) & (~(cp_flush_q))), fxu0_t3_q[7][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex7_mult_recirc}})) ;


generate
begin : xhdla
generate if(1) begin : xhdla
genvar i;
for (i = 6; i <= 12; i = i + 1)
begin : fxu0_pipe_t_gen
@ -814,8 +812,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar i;
for (i = 1; i <= 8; i = i + 1)
begin : lq_pipe_t_gen
@ -825,8 +822,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl4
generate if(1) begin : xhdl4
genvar i;
for (i = 1; i <= 7; i = i + 1)
begin : fxu1_pipe_t_gen
@ -839,8 +835,7 @@ module rv_rf_byp(

assign rel_vld_d[0] = (lq_rv_itag2_vld & (~(cp_flush_q)));
assign rel_itag_d[0] = lq_rv_itag2;
generate
begin : xhdl5
generate if(1) begin : xhdl5
genvar i;
for (i = 1; i <= 3; i = i + 1)
begin : rel_pipe_t_gen
@ -853,8 +848,7 @@ module rv_rf_byp(
//----------------------------------------------------------------------------------------------------------------------------------------
// FXU0 Compares
//----------------------------------------------------------------------------------------------------------------------------------------
generate
begin : xhdl6
generate if(1) begin : xhdl6
genvar i;
for (i = 1; i <= 11; i = i + 1)
begin : comp_fxu0_fxu0
@ -874,8 +868,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhd7
generate if(1) begin : xhd7
genvar i;
for (i = 4; i <= 8; i = i + 1)
begin : comp_fxu0_lq
@ -895,8 +888,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl8
generate if(1) begin : xhdl8
genvar i;
for (i = 1; i <= 6 ; i = i + 1)
begin : comp_fxu0_fxu1
@ -916,8 +908,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl9
generate if(1) begin : xhdl9
genvar i;
for (i = 2; i <= 3; i = i + 1)
begin : comp_fxu0_rel
@ -963,8 +954,7 @@ module rv_rf_byp(
//----------------------------------------------------------------------------------------------------------------------------------------
// LQ Compares
//----------------------------------------------------------------------------------------------------------------------------------------
generate
begin : xhdl10
generate if(1) begin : xhdl10
genvar i;
for (i = 2; i <= 12; i = i + 1)
begin : comp_lq_fxu0
@ -980,8 +970,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl11
generate if(1) begin : xhdl11
genvar i;
for (i = 4; i <= 8; i = i + 1)
begin : comp_lq_lq
@ -997,8 +986,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl12
generate if(1) begin : xhdl12
genvar i;
for (i = 2; i <= 7; i = i + 1)
begin : comp_lq_fxu1
@ -1014,8 +1002,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl13
generate if(1) begin : xhdl13
genvar i;
for (i = 2; i <= 3 ; i = i + 1)
begin : comp_lq_rel
@ -1058,8 +1045,7 @@ module rv_rf_byp(
//----------------------------------------------------------------------------------------------------------------------------------------
// FXU1 Compares
//----------------------------------------------------------------------------------------------------------------------------------------
generate
begin : xhdl14
generate if(1) begin : xhdl14
genvar i;
for (i = 1; i <= 11; i = i + 1)
begin : comp_fxu1_fxu0
@ -1079,8 +1065,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl15
generate if(1) begin : xhdl15
genvar i;
for (i = 4; i <= 8; i = i + 1)
begin : comp_fxu1_lq
@ -1100,8 +1085,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl16
generate if(1) begin : xhdl16
genvar i;
for (i = 1; i <= 6; i = i + 1)
begin : comp_fxu1_fxu1
@ -1121,8 +1105,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl17
generate if(1) begin : xhdl17
genvar i;
for (i = 2; i <= 3 ; i = i + 1)
begin : comp_fxu1_rel
@ -1222,8 +1205,7 @@ module rv_rf_byp(
(fx0_itag_q[6] & {`ITAG_SIZE_ENC{( fx0_ex6_mult_recirc)}}) |
(fx0_itag_q[7] & {`ITAG_SIZE_ENC{( fx0_ex7_mult_recirc)}}) ;

generate
begin : xhdl18i
generate if(1) begin : xhdl18i
genvar i;
for (i = 6; i <= 12; i = i + 1)
begin : fxu0_itag_d_gen
@ -1406,8 +1388,7 @@ module rv_rf_byp(

assign fx1_itag_d[0] = rv_byp_fx1_itag;
assign fx1_vld_d[0] = rv_byp_fx1_vld & (~cp_flush_q);
generate
begin : xhdl19v
generate if(1) begin : xhdl19v
genvar i;
for (i = 1; i <= 6; i = i + 1)
begin : fxu1_vld_d_gen
@ -1415,8 +1396,7 @@ module rv_rf_byp(
end
end
endgenerate
generate
begin : xhdl19
generate if(1) begin : xhdl19
genvar i;
for (i = 1; i <= 7; i = i + 1)
begin : fxu1_itag_d_gen
@ -1537,8 +1517,7 @@ module rv_rf_byp(


assign lq_itag_d[0] = rv_byp_lq_itag;
generate
begin : xhdl20
generate if(1) begin : xhdl20
genvar i;
for (i = 1; i <= 8; i = i + 1)
begin : lq_itag_d_gen
@ -1572,8 +1551,7 @@ module rv_rf_byp(
//-------------------------------------------------------------------
// Latches
//-------------------------------------------------------------------
generate
begin : xhdl21
generate if(1) begin : xhdl21
genvar i;
for (i = 0; i <= 12; i = i + 1)
begin : fxu0_t1_gen
@ -1601,8 +1579,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl22
generate if(1) begin : xhdl22
genvar i;
for (i = 0; i <= 12; i = i + 1)
begin : fxu0_t2_gen
@ -1630,8 +1607,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin
generate if(1) begin
genvar i;
for (i = 0; i <= 12; i = i + 1)
begin : fxu0_t3_gen
@ -1719,8 +1695,7 @@ module rv_rf_byp(
.dout(fxu0_s3_q)
);

generate
begin : xhdl24
generate if(1) begin : xhdl24
genvar i;
for (i = 0; i <= 8; i = i + 1)
begin : lq_t1_gen
@ -1749,8 +1724,7 @@ module rv_rf_byp(
endgenerate


generate
begin : xhdl26
generate if(1) begin : xhdl26
genvar i;
for (i = 0; i <= 8; i = i + 1)
begin : lq_t3_gen
@ -1818,8 +1792,7 @@ module rv_rf_byp(
.dout(lq_s2_q)
);

generate
begin : xhdl27
generate if(1) begin : xhdl27
genvar i;
for (i = 0; i <= 7; i = i + 1)
begin : fxu1_t1_gen
@ -1847,8 +1820,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl28
generate if(1) begin : xhdl28
genvar i;
for (i = 0; i <= 7; i = i + 1)
begin : fxu1_t2_gen
@ -1876,8 +1848,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl29
generate if(1) begin : xhdl29
genvar i;
for (i = 0; i <= 7; i = i + 1)
begin : fxu1_t3_gen
@ -1965,8 +1936,7 @@ module rv_rf_byp(
.dout(fxu1_s3_q)
);

generate
begin : xhdl77
generate if(1) begin : xhdl77
genvar i;
for (i = 0; i <= 3 ; i = i + 1)
begin : rel_gen
@ -2036,8 +2006,7 @@ module rv_rf_byp(
.dout(cp_flush_q)
);

generate
begin : xhdl78b
generate if(1) begin : xhdl78b
genvar i;
for (i = 1; i <= 7; i = i + 1)
begin : fxu0_itagv_gen
@ -2065,8 +2034,7 @@ module rv_rf_byp(
end
end
endgenerate
generate
begin : xhdl78v
generate if(1) begin : xhdl78v
genvar i;
for (i = 0; i <= 11; i = i + 1)
begin : fxu0_itagv_gen
@ -2094,8 +2062,7 @@ module rv_rf_byp(
end
end
endgenerate
generate
begin : xhdl78i
generate if(1) begin : xhdl78i
genvar i;
for (i = 0; i <= 12; i = i + 1)
begin : fxu0_itag_gen
@ -2783,8 +2750,7 @@ module rv_rf_byp(
.dout(fx0_ex7_recircd_q)
);

generate
begin : xab0
generate if(1) begin : xab0
genvar i;
for (i = 3; i <= 4; i = i + 1)
begin : fx0xab
@ -2814,8 +2780,7 @@ module rv_rf_byp(
endgenerate


generate
begin : xhdl70v
generate if(1) begin : xhdl70v
genvar i;
for (i = 0; i <= 6; i = i + 1)
begin : fxu1_vld_gen
@ -2844,8 +2809,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl70
generate if(1) begin : xhdl70
genvar i;
for (i = 0; i <= 7; i = i + 1)

@ -3306,8 +3270,7 @@ module rv_rf_byp(
.dout(fx1_ext_rel_itag_abort_q)
);

generate
begin : xab1
generate if(1) begin : xab1
genvar i;
for (i = 3; i <= 4; i = i + 1)
begin : fx1xab
@ -3459,8 +3422,7 @@ module rv_rf_byp(
.dout(fx1_ex0_s3_itag_q)
);

generate
begin : xhdl80
generate if(1) begin : xhdl80
genvar i;
for (i = 0; i <= 7; i = i + 1)
begin : lq_vld_gen
@ -3488,8 +3450,7 @@ module rv_rf_byp(
end
endgenerate

generate
begin : xhdl81
generate if(1) begin : xhdl81
genvar i;
for (i = 0; i <= `LQ_LOAD_PIPE_END; i = i + 1)
begin : lq_itag_gen

192
dev/verilog/work/rv_station.v
Unescape Escape View File

@ -719,8 +719,7 @@ module rv_station(
assign w_act = (rv0_w0_addr | rv0_w1_addr) & {q_num_entries_g+1{(rv0_instr_i0_rte | rv0_instr_i1_rte)}};


generate
begin : xhdlbbar
generate if(1) begin : xhdlbbar
for (n = 0; n <= (q_num_entries_g ); n = n + 1)
begin : genaddr
wire [0:q_barf_enc_g-1] id=n;
@ -782,8 +781,7 @@ module rv_station(
endgenerate
assign rv0_w0_addr[0] = barf_w0_or_tree[0] & ~barf_w0_or_tree[1];
assign rv0_w1_addr[0] = barf_w1_or_tree[0];
generate
begin : xhdlbbar2
generate if(1) begin : xhdlbbar2
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : genaddr2

@ -816,8 +814,7 @@ module rv_station(
//-------------------------------------------------------------------------------------------------------
assign q_ev_d[0] = (q_entry_load_i1[0]) | (q_entry_load_i0[0]) | (1'b0 & q_entry_shift[0]) | (q_ev_nxt[0] & q_entry_hold[0]);

generate
begin : xhdl1
generate if(1) begin : xhdl1
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_ev_gen
assign q_ev_d[n] = (q_entry_load_i1[n]) | (q_entry_load_i0[n]) | (q_ev_nxt[n - 1] & q_entry_shift[n]) | (q_ev_nxt[n] & q_entry_hold[n]);
@ -825,8 +822,7 @@ module rv_station(
end
endgenerate

generate
begin : xhdl2
generate if(1) begin : xhdl2
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_ev_nxt_gen
assign q_ev_clr[n] = q_credit_take[n] | &(flush);
@ -844,8 +840,7 @@ module rv_station(
(rv0_instr_i0_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) |
(q_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}});

generate
begin : xhdl7
generate if(1) begin : xhdl7
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_itag_gen
assign q_itag_d[n] = (rv0_instr_i1_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[n]}}) |
@ -864,8 +859,7 @@ module rv_station(
assign q_tid_d[0] = ({`THREADS{q_entry_load_i1[0]}} & rv0_instr_i1_tid ) |
({`THREADS{q_entry_load_i0[0]}} & rv0_instr_i0_tid ) |
({`THREADS{q_entry_hold[0]}} & q_tid_q[0]);
generate
begin : xhdl10
generate if(1) begin : xhdl10
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_tid_gen
assign q_tid_d[n] = ({`THREADS{q_entry_load_i1[n]}} & rv0_instr_i1_tid ) |
@ -881,8 +875,7 @@ module rv_station(
//-------------------------------------------------------------------------------------------------------
assign q_flushed_d[0] = (rv0_instr_i1_flushed & q_entry_load_i1[0]) | (rv0_instr_i0_flushed & q_entry_load_i0[0]) | (q_flushed_nxt[0] & q_entry_hold[0]);

generate
begin : xhdl11
generate if(1) begin : xhdl11
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_flushed_gen
assign q_flushed_d[n] = (rv0_instr_i1_flushed & q_entry_load_i1[n]) |
@ -893,8 +886,7 @@ module rv_station(
end
endgenerate

generate
begin : xhdl12
generate if(1) begin : xhdl12
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_flushed_nxt_gen
assign q_flushed_nxt[n] = q_ev_q[n] & |(q_tid_q[n] & ({`THREADS{q_flushed_q[n]}} | flush));
@ -910,8 +902,7 @@ module rv_station(
(rv0_w1_addr_enc & {q_barf_enc_g{q_entry_load_i1[0]}}) |
(q_barf_addr_q[0] & {q_barf_enc_g{q_entry_hold[0]}});

generate
begin : xhdl11b
generate if(1) begin : xhdl11b
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_barf_addr_gen
assign q_barf_addr_d[n] = (rv0_w0_addr_enc & {q_barf_enc_g{q_entry_load_i0[n]}}) |
@ -929,8 +920,7 @@ module rv_station(
assign q_ilat_d[0] = ({q_ilat_width_g{q_entry_load_i1[0]}} & rv0_instr_i1_ilat ) |
({q_ilat_width_g{q_entry_load_i0[0]}} & rv0_instr_i0_ilat ) |
({q_ilat_width_g{q_entry_hold[0]}} & q_ilat_q[0]);
generate
begin : xhdl13
generate if(1) begin : xhdl13
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_ilat_gen
assign q_ilat_d[n] = ({q_ilat_width_g{q_entry_load_i1[n]}} & rv0_instr_i1_ilat ) |
@ -957,8 +947,7 @@ module rv_station(
(rv0_instr_i0_s3_v & q_entry_load_i0[0]) |
(q_s3_v_q[0] & q_entry_hold[0]);

generate
begin : xhdl16
generate if(1) begin : xhdl16
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_sv_gen
assign q_s1_v_d[n] = (rv0_instr_i1_s1_v & q_entry_load_i1[n]) |
@ -995,8 +984,7 @@ module rv_station(
(rv0_instr_i0_s3_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) |
(q_s3_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}});

generate
begin : xhdl17
generate if(1) begin : xhdl17
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_sitag_gen

@ -1034,8 +1022,7 @@ module rv_station(
(q_s3_rdy_nxt[0] & q_entry_hold[0] );


generate
begin : xhdl20
generate if(1) begin : xhdl20
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_srdy_gen
assign q_s1_rdy_d[n] = (rv0_instr_i1_s1_rdy & q_entry_load_i1[n]) |
@ -1054,8 +1041,7 @@ module rv_station(
end
endgenerate

generate
begin : xhdl21
generate if(1) begin : xhdl21
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_srdy_nxt_gen
assign q_s1_rdy_setf[n] = (q_other_ilat0_match_s1[n] | q_ilat0_match_s1[n]);
@ -1090,8 +1076,7 @@ module rv_station(
(q_i0_s_rdy & q_entry_load_i0[0]) |
(q_entry_hold[0] & q_rdy_nxt[0]);

generate
begin : xhdl22
generate if(1) begin : xhdl22
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_rdy_gen
assign q_rdy_d[n] = (q_i1_s_rdy & q_entry_load_i1[n]) |
@ -1102,8 +1087,7 @@ module rv_station(
end
endgenerate

generate
begin : xhdl23
generate if(1) begin : xhdl23
for (n = 0; n <= (q_num_entries_g - 2); n = n + 1)
begin : q_rdy_nxt_gen
assign q_rdy_set[n] = ( (~q_e_miss_nxt[n])) &
@ -1134,8 +1118,7 @@ module rv_station(

assign q_issued_d[4] = q_issued_nxt[4] & q_entry_hold[4];

generate
begin : xhdl24
generate if(1) begin : xhdl24
for (n = 5; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_issued_gen

@ -1146,8 +1129,7 @@ module rv_station(
endgenerate

// If its not ready, its not issued nxt
generate
begin : xhdl25
generate if(1) begin : xhdl25
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_issued_nxt_gen
assign q_issued_set[n] = q_entry_select[n];
@ -1170,8 +1152,7 @@ module rv_station(
({q_dat_width_g{1'b0}} & {q_dat_width_g{q_entry_shift[0]}}) |
(q_dat_q[0] & {q_dat_width_g{q_entry_hold[0]}}); //feedback

generate
begin : xhdl28
generate if(1) begin : xhdl28
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_dat_gen
assign q_dat_d[n] = (rv0_instr_i1_dat & {q_dat_width_g{q_entry_load_i1[n]}}) |
@ -1185,8 +1166,7 @@ module rv_station(
//-------------------------------------------------------------------------------------------------------
// generation of q_entry_rdy logic. These are used after prioritization as mux selects to remove entries
//-------------------------------------------------------------------------------------------------------
generate
begin : xhdl29
generate if(1) begin : xhdl29
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_entry_rdy_gen
assign q_entry_rdy[n] = q_rdy_q[n] ;
@ -1204,8 +1184,7 @@ module rv_station(
//-------------------------------------------------------------------------------------------------------
// generation of ilat0 compare for zero bypass cases. Do it early for timing
//-------------------------------------------------------------------------------------------------------
generate
begin : xhdl30
generate if(1) begin : xhdl30
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_entry_ilat0_gen
assign q_entry_ilat0[n] = q_tid_q[n] & {`THREADS{(q_ilat_q[n] == 4'b0000) }};
@ -1213,8 +1192,7 @@ module rv_station(
end
endgenerate

generate
begin : xhdl31
generate if(1) begin : xhdl31
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_entry_ilat1_gen
assign q_entry_ilat1[n] = q_tid_q[n] & {`THREADS{(q_ilat_q[n] == 4'b0001) }};
@ -1236,8 +1214,7 @@ module rv_station(

assign q_entry_select = ~(q_hold_all_q | q_hold_brick) ? q_entry_rdy_pri : {q_num_entries_g-4{1'b0}};

generate
begin : dat_extnd
generate if(1) begin : dat_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : dat_extnda
assign q_dat_ary[n*q_dat_width_g:(n+1)*q_dat_width_g-1] = q_dat_q[n];
@ -1255,8 +1232,7 @@ module rv_station(
assign rv1_instr_dat = q_instr_dat;


generate
begin : tid_extnd
generate if(1) begin : tid_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : tid_extnda
assign q_tid_ary[n*`THREADS:(n+1)*`THREADS-1] = q_tid_q[n];
@ -1276,8 +1252,7 @@ module rv_station(
assign q_instr_is_brick = |(q_entry_select & q_is_brick_q[4:q_num_entries_g-1]);
assign rv1_instr_is_brick = |(q_entry_rdy_pri & q_is_brick_q[4:q_num_entries_g-1]);

generate
begin : brick_extnd
generate if(1) begin : brick_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : brick_extnda
assign q_brick_ary[n*3:(n+1)*3-1] = q_brick_q[n];
@ -1298,8 +1273,7 @@ module rv_station(
assign rv1_other_ilat0_itag_out = ~q_instr_itag_l1a_b;

//-------------------------------------------------------------------------------------------------------
generate
begin : ilat0_extnd
generate if(1) begin : ilat0_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : ilat0_extnda
assign q_ilat0_ary[n*`THREADS:(n+1)*`THREADS-1] = q_entry_ilat0[n];
@ -1323,8 +1297,7 @@ module rv_station(
assign rv1_instr_ilat0_vld = q_instr_ilat0_vld;

//-------------------------------------------------------------------------------------------------------
generate
begin : ilat1_extnd
generate if(1) begin : ilat1_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : ilat1_extnda
assign q_ilat1_ary[n*`THREADS:(n+1)*`THREADS-1] = q_entry_ilat1[n];
@ -1343,8 +1316,7 @@ module rv_station(
assign rv1_instr_ilat1_vld = q_instr_ilat1_vld;

//-------------------------------------------------------------------------------------------------------
generate
begin : itag_extnd
generate if(1) begin : itag_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : itag_extnda
assign q_itag_ary[n*`ITAG_SIZE_ENC:(n+1)*`ITAG_SIZE_ENC-1] = q_itag_q[n];
@ -1368,8 +1340,7 @@ module rv_station(


//-------------------------------------------------------------------------------------------------------
generate
begin : s1_itag_extnd
generate if(1) begin : s1_itag_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : s1_itag_extnda
assign q_s1_itag_ary[n*`ITAG_SIZE_ENC:(n+1)*`ITAG_SIZE_ENC-1] = q_s1_itag_q[n];
@ -1386,8 +1357,7 @@ module rv_station(
assign rv1_instr_s1_itag = q_instr_s1_itag;

//-------------------------------------------------------------------------------------------------------
generate
begin : s2_itag_extnd
generate if(1) begin : s2_itag_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : s2_itag_extnda
assign q_s2_itag_ary[n*`ITAG_SIZE_ENC:(n+1)*`ITAG_SIZE_ENC-1] = q_s2_itag_q[n];
@ -1405,8 +1375,7 @@ module rv_station(
assign rv1_instr_s2_itag = q_instr_s2_itag;

//-------------------------------------------------------------------------------------------------------
generate
begin : s3_itag_extnd
generate if(1) begin : s3_itag_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : s3_itag_extnda
assign q_s3_itag_ary[n*`ITAG_SIZE_ENC:(n+1)*`ITAG_SIZE_ENC-1] = q_s3_itag_q[n];
@ -1424,8 +1393,7 @@ module rv_station(
assign rv1_instr_s3_itag = q_instr_s3_itag;

//-------------------------------------------------------------------------------------------------------
generate
begin : ilat_extnd
generate if(1) begin : ilat_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : ilat_extnda
assign q_ilat_ary[n*q_ilat_width_g:(n+1)*q_ilat_width_g-1] = q_ilat_q[n];
@ -1442,8 +1410,7 @@ module rv_station(
);

//-------------------------------------------------------------------------------------------------------
generate
begin : ba_extnd
generate if(1) begin : ba_extnd
for (n = 4; n <= (q_num_entries_g - 1); n = n + 1)
begin : ba_extnda
assign q_barf_addr_ary[n*q_barf_enc_g:(n+1)*q_barf_enc_g-1] = q_barf_addr_q[n];
@ -1451,8 +1418,7 @@ module rv_station(
end
end
endgenerate
generate
begin : ba_extndc
generate if(1) begin : ba_extndc
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : ba_extndac
assign q_barf_clr_addr_ary[n*q_barf_enc_g:(n+1)*q_barf_enc_g-1] = q_barf_addr_q[n];
@ -1513,7 +1479,7 @@ module rv_station(
assign q_cord_d[0] = (q_entry_load_i1[0] & rv0_instr_i1_cord ) |
(q_entry_load_i0[0] & rv0_instr_i0_cord ) |
(q_entry_hold[0] & q_cord_nxt[0]);
begin : xhdl5
if(1) begin : xhdl5
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_cord_gen
assign q_cord_d[n] = (q_entry_load_i1[n] & rv0_instr_i1_cord ) |
@ -1523,7 +1489,7 @@ module rv_station(

end
end
begin : xhdl6
if(1) begin : xhdl6
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_cord_nxt_gen
assign q_cord_set[n] = q_lq_itag_match[n] & lq_rv_itag1_cord_q;
@ -1558,7 +1524,7 @@ module rv_station(
if (q_cord_g == 0)
begin : q_cord0_g_gen
assign q_cord_match = 1'b0;
begin : xhdl6b
if(1) begin : xhdl6b
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_cord0_nxt_gen
assign q_cord_d[n]=1'b0;
@ -1581,7 +1547,7 @@ module rv_station(
assign q_ord_d[0] = (q_entry_load_i1[0] & rv0_instr_i1_ord ) |
(q_entry_load_i0[0] & rv0_instr_i0_ord ) |
(q_entry_hold[0] & q_ord_nxt[0]);
begin : xhdl3
if(1) begin : xhdl3
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_ord_gen
assign q_ord_d[n] = (q_entry_load_i1[n] & rv0_instr_i1_ord ) |
@ -1592,7 +1558,7 @@ module rv_station(
end
end

begin : xhdl4
if(1) begin : xhdl4
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_ord_nxt_gen
assign q_ord_nxt[n] = q_ord_q[n];
@ -1625,7 +1591,7 @@ module rv_station(
if (q_ord_g == 0)
begin : q_ord0_g_gen
//generate
begin : xhdl3b
if(1) begin : xhdl3b
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_ord0_gen

@ -1658,7 +1624,7 @@ module rv_station(
assign q_spec_d[0] = (q_entry_load_i1[0] & rv0_instr_i1_spec ) |
(q_entry_load_i0[0] & rv0_instr_i0_spec ) |
(q_entry_hold[0] & q_spec_nxt[0]);
begin : xhdl14
if(1) begin : xhdl14
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_spec_gen
assign q_spec_d[n] = (q_entry_load_i1[n] & rv0_instr_i1_spec ) |
@ -1667,7 +1633,7 @@ module rv_station(
(q_entry_hold[n] & q_spec_nxt[n] );
end
end
begin : xhdl15
if(1) begin : xhdl15
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_spec_nxt_gen
assign q_spec_clr[n] = q_lq_itag_match[n] & (~q_e_miss_nxt[n]) & (~lq_rv_itag1_restart_q);
@ -1702,7 +1668,7 @@ module rv_station(
//-------------------------------------------------------------------------------------------------------

assign q_e_miss_d[0] = q_e_miss_nxt[0] & q_entry_hold[0];
begin : xhdl26
if(1) begin : xhdl26
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_e_miss_gen

@ -1710,7 +1676,7 @@ module rv_station(
(q_e_miss_nxt[n] & q_entry_hold[n]);
end
end
begin : xhdl27
if(1) begin : xhdl27
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_e_miss_nxt_gen
assign q_e_miss_set[n] = q_lq_itag_match[n] & lq_rv_itag1_hold_q;
@ -1890,7 +1856,7 @@ module rv_station(
assign q_is_brick_d[0] = (q_entry_load_i1[0] & rv0_instr_i1_is_brick ) |
(q_entry_load_i0[0] & rv0_instr_i0_is_brick ) |
(q_entry_hold[0] & q_is_brick_q[0]);
begin : xhdl8
if(1) begin : xhdl8
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_is_brick_gen
assign q_is_brick_d[n] = (q_entry_load_i1[n] & rv0_instr_i1_is_brick ) |
@ -1903,7 +1869,7 @@ module rv_station(
assign q_brick_d[0] = ({3{q_entry_load_i1[0]}} & rv0_instr_i1_brick ) |
({3{q_entry_load_i0[0]}} & rv0_instr_i0_brick ) |
({3{q_entry_hold[0]}} & q_brick_q[0]);
begin : xhdl9
if(1) begin : xhdl9
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_brick_gen
assign q_brick_d[n] = ({3{q_entry_load_i1[n]}} & rv0_instr_i1_brick ) |
@ -1954,7 +1920,7 @@ module rv_station(
.dout(q_hold_brick_cnt_q)
);

begin : xhdl9b
if(1) begin : xhdl9b
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_bricklat_gen
tri_rlmlatch_p #(.INIT(0))
@ -2016,7 +1982,7 @@ module rv_station(
assign brick_unused = q_hold_brick | |q_hold_brick_cnt_d | |q_hold_brick_cnt_q | q_hold_brick_d | q_hold_brick_q | q_instr_is_brick |
rv0_instr_i0_is_brick | |rv0_instr_i0_brick | rv0_instr_i1_is_brick | |rv0_instr_i1_brick | |q_instr_brick;

begin : xhdl9b
if(1) begin : xhdl9b
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_brick_gen0

@ -2043,8 +2009,7 @@ module rv_station(
//-------------------------------------------------------------------------------------------------------
assign q_ev_b = (~q_ev_q);

generate
begin : xhdl32
generate if(1) begin : xhdl32
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_or_gen
assign q_entry_or_tree[n] = |(q_ev_b[n:q_num_entries_g - 1]);
@ -2052,8 +2017,7 @@ module rv_station(
end
endgenerate

generate
begin : xhdl33
generate if(1) begin : xhdl33
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_and_gen
assign q_entry_and_tree[n] = &(q_ev_b[0:n]);
@ -2061,8 +2025,7 @@ module rv_station(
end
endgenerate

generate
begin : xhdl34
generate if(1) begin : xhdl34
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_entry_shift_gen
assign q_entry_shift[n] = q_entry_or_tree[n] & (~(q_entry_load[n] | q_entry_load2[n]));
@ -2075,8 +2038,7 @@ module rv_station(
(rv0_load1 & q_entry_or_tree[0] & q_entry_and_tree[0] & (~q_entry_or_tree[1]));


generate
begin : xhdl35
generate if(1) begin : xhdl35
for (n = 1; n <= (q_num_entries_g - 2); n = n + 1)
begin : q_load_gen
// special case
@ -2091,8 +2053,7 @@ module rv_station(
assign q_entry_load[q_num_entries_g - 1] = (rv0_load1 & (~q_entry_or_tree[q_num_entries_g - 1]) & q_entry_and_tree[q_num_entries_g - 1] & (~1'b0)) |
(rv0_load1 & q_entry_or_tree[q_num_entries_g - 1] & (~1'b0) & q_entry_and_tree[q_num_entries_g - 2]);

generate
begin : xhdl36
generate if(1) begin : xhdl36
for (n = 0; n <= (q_num_entries_g - 2); n = n + 1)
begin : q_entry_load2_gen
assign q_entry_load2[n] = rv0_load2 & q_entry_load[n + 1];
@ -2101,8 +2062,7 @@ module rv_station(
endgenerate
assign q_entry_load2[q_num_entries_g - 1] = 1'b0;

generate
begin : xhdl37
generate if(1) begin : xhdl37
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_hold_gen
assign q_entry_hold[n] = (~(q_entry_load[n] | q_entry_load2[n] | q_entry_shift[n]));
@ -2123,8 +2083,7 @@ module rv_station(
|(lq_rv_itag1_rst_vld_q | lq_rv_clr_hold_q); //itag1 clrhold
assign q_cord_act[0] = (rv0_instr_i0_rte | rv0_instr_i1_rte) | |(lq_rv_itag1_rst_vld_q);

generate
begin : xhdl38
generate if(1) begin : xhdl38
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_act_gen
assign q_dat_act[n] = ((rv0_instr_i0_rte | rv0_instr_i1_rte) | q_ev_q[n - 1]);
@ -2143,8 +2102,7 @@ module rv_station(

assign q_credit_d[0] = (q_credit_nxt[0] & q_entry_hold[0]) & ~(&(flush));

generate
begin : xhdl39
generate if(1) begin : xhdl39
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_credit_gen
assign q_credit_d[n] =
@ -2154,8 +2112,7 @@ module rv_station(
end
endgenerate

generate
begin : xhdl40
generate if(1) begin : xhdl40
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_credit_nxt_gen

@ -2184,8 +2141,7 @@ module rv_station(
.pri(q_credit_take)
);

generate
begin : tid_extndf
generate if(1) begin : tid_extndf
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : tid_extndaf
assign q_tid_full_ary[n*`THREADS:(n+1)*`THREADS-1] = q_tid_q[n];
@ -2201,8 +2157,7 @@ module rv_station(
.dout(ex1_credit_free_d)
);

generate
begin : xhdl41
generate if(1) begin : xhdl41
for (t = 0; t <= (`THREADS - 1); t = t + 1)
begin : ex1_credit_gen
assign ex1_credit_free[t] = ex1_credit_free_q[t] & ~(&(flush2));
@ -2214,13 +2169,12 @@ module rv_station(
// RVS Empty
//-------------------------------------------------------------------------------------------------------

generate
begin : xhdl43
generate if(1) begin : xhdl43
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_entry_tvld_gen
assign q_entry_tvld[n] = {`THREADS{q_ev_q[n]}} & q_tid_q[n];

begin : xhdl42
if(1) begin : xhdl42
for (t = 0; t <= (`THREADS - 1); t = t + 1)
begin : q_tvld_rev_gen
assign q_entry_tvld_rev[t][n] = q_entry_tvld[n][t];
@ -2230,8 +2184,7 @@ module rv_station(
end
endgenerate

generate
begin : xhdl44
generate if(1) begin : xhdl44
for (t = 0; t <= (`THREADS - 1); t = t + 1)
begin : rvs_empty_gen
assign rvs_empty_d[t] = (~(|(q_entry_tvld_rev[t]) |
@ -2256,8 +2209,7 @@ module rv_station(

// Is the entry being shifted? We only shift down, ignore last shift

generate
begin : xiaenc
generate if(1) begin : xiaenc
// Encode the issued entry address to save latches
if(q_num_entries_g==12)
begin : ia12
@ -2368,8 +2320,7 @@ module rv_station(
assign xx_rv_itag_ary[5*(`ITAG_SIZE_ENC):5*(`ITAG_SIZE_ENC)+(`ITAG_SIZE_ENC)-1] = xx_rv_rel_itag_q[5] ;
assign xx_rv_itag_ary[6*(`ITAG_SIZE_ENC):6*(`ITAG_SIZE_ENC)+(`ITAG_SIZE_ENC)-1] = xx_rv_rel_itag_q[6] ;

generate
begin : xhdl45
generate if(1) begin : xhdl45
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_itag_match_gen
// Zero Bubble from my FX release
@ -2565,8 +2516,7 @@ module rv_station(
.dout(ex0_barf_addr_q)
);

generate
begin : x5ia4
generate if(1) begin : x5ia4
for (n = 0; n <= 4 ; n = n + 1)
begin : isa_gen

@ -2694,8 +2644,7 @@ module rv_station(



generate
begin : xhdl555
generate if(1) begin : xhdl555
for (n = 0; n <= q_num_entries_g ; n = n + 1)
begin : q_bev_gen

@ -2722,8 +2671,7 @@ module rv_station(
end // block: xhdl555
endgenerate

generate
begin : xhdl5xx
generate if(1) begin : xhdl5xx
for (n = 0; n < q_itag_busses_g ; n = n + 1)
begin : xx_gen

@ -2789,8 +2737,7 @@ module rv_station(
.dout(xx_rv_abort_q)
);

generate
begin : xhdl999
generate if(1) begin : xhdl999
for (n = 0; n <= q_num_entries_g - 1; n = n + 1)
begin : q_x_q_gen

@ -3113,8 +3060,7 @@ module rv_station(


// Issueable
generate
begin : xhdl999i
generate if(1) begin : xhdl999i
for (n = 0; n <= q_num_entries_g - 1; n = n + 1)
begin : q_x_q_gen


2
dev/verilog/work/xu.v
Unescape Escape View File

@ -860,7 +860,7 @@ module xu(
assign lq_xu_gpr_ex6_wa_d = lq_xu_gpr_ex5_wa[AXU_TARGET_ENC - (`GPR_POOL_ENC + `THREADS_POOL_ENC):AXU_TARGET_ENC - 1];
assign lq_xu_gpr_ex6_wd_d = lq_xu_ex5_rt[128 - `GPR_WIDTH:127];

generate begin : parGen
generate if(1) begin : parGen
genvar b;
for (b=0;b<=`GPR_WIDTH/8-1;b=b+1)
begin : parGen

2
dev/verilog/work/xu0.v
Unescape Escape View File

@ -572,7 +572,7 @@ module xu0
.y(cnt_byp_ex2_rt)
);

generate begin : bperm
generate if(1) begin : bperm
genvar i;
for (i=0;i<=7;i=i+1) begin : bprm_bit
xu0_bprm bperm_bit(

16
dev/verilog/work/xu0_br.v
Unescape Escape View File

@ -771,8 +771,7 @@ assign ex1_vld_d = (rv_br_ex0_fusion | |(ex1_vld_q) ? ex0_vld & (~iu_br_flush_q)
assign ex2_abs = (ex3_is_b_d == 1'b1) ? ex2_li :
ex2_bd;

generate
begin : xhdl1
generate if(1) begin : xhdl1
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : thread_ifar
@ -798,8 +797,7 @@ assign ex1_vld_d = (rv_br_ex0_fusion | |(ex1_vld_q) ? ex0_vld & (~iu_br_flush_q)

assign ex2_nia_pre = ex2_ifar + 1;

generate
begin : xhdl2
generate if(1) begin : xhdl2
genvar i;
for (i = (62 - `EFF_IFAR_ARCH); i <= 61; i = i + 1)
begin : ex3NIAMask
@ -820,8 +818,7 @@ assign ex3_nia_d = ex2_nia;

assign ex3_bta_pre = (ex3_is_bclr_q == 1'b1 ? ex3_lr[62 - `EFF_IFAR_ARCH:61] : 0 ) | (ex3_is_bcctr_q == 1'b1 ? ex3_ctr[62 - `EFF_IFAR_ARCH:61] : 0 ) | (ex3_is_bctar_q == 1'b1 ? ex3_lr[62 - `EFF_IFAR_ARCH:61] : 0 ) | (ex3_is_b_q == 1'b1 | ex3_is_bc_q == 1'b1 ? ex3_bta_q[62 - `EFF_IFAR_ARCH:61] : 0 );

generate
begin : xhdl3
generate if(1) begin : xhdl3
genvar i;
for (i = (62 - `EFF_IFAR_ARCH); i <= 61; i = i + 1)
begin : ex3BTAMask
@ -846,7 +843,7 @@ assign ex3_nia = ex3_nia_q;
//-----------------------------------------------

generate
begin : xhdl4
if(1) begin : xhdl4
genvar i;
for (i = 0; i <= (`THREADS - 1); i = i + 1)
begin : br_thread
@ -987,7 +984,7 @@ assign br_iu_perf_events = ex4_perf_event_q;
//5: mispredicted branch target (within current address range)
//6: mispredicted branch target (outside current address range)

generate begin : perf_event
generate if(1) begin : perf_event
genvar t,e;
for (e=0;e<=3;e=e+1) begin : thread
for (t=0;t<=`THREADS-1;t=t+1) begin : thread
@ -1047,8 +1044,7 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_br_flush_latch(
.dout(iu_br_flush_q)
);

generate
begin : xhdl5
generate if(1) begin : xhdl5
genvar i;
for (i = 0; i <= `THREADS - 1; i = i + 1)
begin : thread_regs

36
dev/verilog/work/xu0_byp.v
Unescape Escape View File

@ -1068,7 +1068,7 @@ module xu0_byp(
//------------------------------------------------------------------------------------------
// Parity Gen
//------------------------------------------------------------------------------------------
generate begin : parity_gen
generate if(1) begin : parity_gen
genvar i;
for (i = 8-`GPR_WIDTH/8; i <= 7; i = i + 1)
begin : parity_loop
@ -1241,7 +1241,7 @@ module xu0_byp(
.din(rv_xu0_ex0_s3_v),
.dout(ex1_s3_v_q)
);
generate begin : ex1_gpr_s1_xu0_sel_gen
generate if(1) begin : ex1_gpr_s1_xu0_sel_gen
genvar i;
for (i=2;i<=8;i=i+1) begin : ex1_gpr_s1_xu0_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu0_sel_latch(
@ -1261,7 +1261,7 @@ generate begin : ex1_gpr_s1_xu0_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s2_xu0_sel_gen
generate if(1) begin : ex1_gpr_s2_xu0_sel_gen
genvar i;
for (i=2;i<=8;i=i+1) begin : ex1_gpr_s2_xu0_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu0_sel_latch(
@ -1281,7 +1281,7 @@ generate begin : ex1_gpr_s2_xu0_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s1_xu1_sel_gen
generate if(1) begin : ex1_gpr_s1_xu1_sel_gen
genvar i;
for (i=2;i<=5;i=i+1) begin : ex1_gpr_s1_xu1_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu1_sel_latch(
@ -1301,7 +1301,7 @@ generate begin : ex1_gpr_s1_xu1_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s2_xu1_sel_gen
generate if(1) begin : ex1_gpr_s2_xu1_sel_gen
genvar i;
for (i=2;i<=5;i=i+1) begin : ex1_gpr_s2_xu1_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu1_sel_latch(
@ -1321,7 +1321,7 @@ generate begin : ex1_gpr_s2_xu1_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s1_lq_sel_gen
generate if(1) begin : ex1_gpr_s1_lq_sel_gen
genvar i;
for (i=5;i<=8;i=i+1) begin : ex1_gpr_s1_lq_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_lq_sel_latch(
@ -1341,7 +1341,7 @@ generate begin : ex1_gpr_s1_lq_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s2_lq_sel_gen
generate if(1) begin : ex1_gpr_s2_lq_sel_gen
genvar i;
for (i=5;i<=8;i=i+1) begin : ex1_gpr_s2_lq_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_lq_sel_latch(
@ -1375,7 +1375,7 @@ endgenerate
.din({8{dec_byp_ex0_rs2_sel_imm}}),
.dout(ex1_gpr_s2_imm_sel_q)
);
generate begin : ex1_spr_s1_xu0_sel_gen
generate if(1) begin : ex1_spr_s1_xu0_sel_gen
genvar i;
for (i=3;i<=6;i=i+1) begin : ex1_spr_s1_xu0_sel_entry
tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_xu0_sel_latch(
@ -1395,7 +1395,7 @@ generate begin : ex1_spr_s1_xu0_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s1_xu1_sel_gen
generate if(1) begin : ex1_spr_s1_xu1_sel_gen
genvar i;
for (i=3;i<=3;i=i+1) begin : ex1_spr_s1_xu1_sel_entry
tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_xu1_sel_latch(
@ -1415,7 +1415,7 @@ generate begin : ex1_spr_s1_xu1_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s1_lq_sel_gen
generate if(1) begin : ex1_spr_s1_lq_sel_gen
genvar i;
for (i=5;i<=6;i=i+1) begin : ex1_spr_s1_lq_sel_entry
tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_lq_sel_latch(
@ -1435,7 +1435,7 @@ generate begin : ex1_spr_s1_lq_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s2_xu0_sel_gen
generate if(1) begin : ex1_spr_s2_xu0_sel_gen
genvar i;
for (i=3;i<=6;i=i+1) begin : ex1_spr_s2_xu0_sel_entry
tri_rlmreg_p #(.WIDTH(6), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_xu0_sel_latch(
@ -1455,7 +1455,7 @@ generate begin : ex1_spr_s2_xu0_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s2_xu1_sel_gen
generate if(1) begin : ex1_spr_s2_xu1_sel_gen
genvar i;
for (i=3;i<=3;i=i+1) begin : ex1_spr_s2_xu1_sel_entry
tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_xu1_sel_latch(
@ -1475,7 +1475,7 @@ generate begin : ex1_spr_s2_xu1_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s2_lq_sel_gen
generate if(1) begin : ex1_spr_s2_lq_sel_gen
genvar i;
for (i=5;i<=6;i=i+1) begin : ex1_spr_s2_lq_sel_entry
tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_lq_sel_latch(
@ -1495,7 +1495,7 @@ generate begin : ex1_spr_s2_lq_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s3_xu0_sel_gen
generate if(1) begin : ex1_spr_s3_xu0_sel_gen
genvar i;
for (i=3;i<=8;i=i+1) begin : ex1_spr_s3_xu0_sel_entry
tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu0_sel_latch(
@ -1515,7 +1515,7 @@ generate begin : ex1_spr_s3_xu0_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s3_xu1_sel_gen
generate if(1) begin : ex1_spr_s3_xu1_sel_gen
genvar i;
for (i=3;i<=5;i=i+1) begin : ex1_spr_s3_xu1_sel_entry
tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu1_sel_latch(
@ -1535,7 +1535,7 @@ generate begin : ex1_spr_s3_xu1_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s3_lq_sel_gen
generate if(1) begin : ex1_spr_s3_lq_sel_gen
genvar i;
for (i=5;i<=6;i=i+1) begin : ex1_spr_s3_lq_sel_entry
tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_lq_sel_latch(
@ -1555,7 +1555,7 @@ generate begin : ex1_spr_s3_lq_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s1_rel_sel_gen
generate if(1) begin : ex1_gpr_s1_rel_sel_gen
genvar i;
for (i=3;i<=4;i=i+1) begin : ex1_gpr_s1_rel_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_rel_sel_latch(
@ -1575,7 +1575,7 @@ generate begin : ex1_gpr_s1_rel_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s2_rel_sel_gen
generate if(1) begin : ex1_gpr_s2_rel_sel_gen
genvar i;
for (i=3;i<=4;i=i+1) begin : ex1_gpr_s2_rel_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_rel_sel_latch(

4
dev/verilog/work/xu0_dec.v
Unescape Escape View File

@ -1689,7 +1689,7 @@ module xu0_dec(

assign ex3_tid = (ex3_val_q | (ex2_ord_tid_q & {`THREADS{ex3_ord_complete_q}}));

generate begin : perf_event
generate if(1) begin : perf_event
genvar t,e;
for (e=0;e<=3;e=e+1) begin : thread
for (t=0;t<=`THREADS-1;t=t+1) begin : thread
@ -4487,7 +4487,7 @@ module xu0_dec(
.din(ord_flush_1_q),
.dout(ord_flush_2_q)
);
generate begin : spr_mmucr0_tlbsel_gen
generate if(1) begin : spr_mmucr0_tlbsel_gen
genvar i;
for (i=0;i<`THREADS;i=i+1) begin : spr_mmucr0_tlbsel_entry
tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_mmucr0_tlbsel_latch(

28
dev/verilog/work/xu1_byp.v
Unescape Escape View File

@ -526,7 +526,7 @@ module xu1_byp(
//------------------------------------------------------------------------------------------
// Parity Gen
//------------------------------------------------------------------------------------------
generate begin : ex3ParGen
generate if(1) begin : ex3ParGen
genvar i;
for (i=8-`GPR_WIDTH/8;i<=7;i=i+1) begin : ex3ParGen
assign ex3_parity[i] = ^(alu_byp_ex3_rt[8*i:8*i+7]);
@ -539,7 +539,7 @@ module xu1_byp(
//------------------------------------------------------------------------------------------
`ifdef THREADS1

generate begin : dvc_1t
generate if(1) begin : dvc_1t
genvar b;
for (b=(64-`GPR_WIDTH)/8;b<=7;b=b+1) begin : dvc_byte
assign ex2_stq_dvc1_t0_cmpr[b] = (spr_dvc1_t0[8*b:8*b+7] == ex2_rs1_q[8*b:8*b+7]);
@ -554,7 +554,7 @@ module xu1_byp(


`ifndef THREADS1
generate begin : dvc_2t
generate if(1) begin : dvc_2t

genvar b;
for (b=(64-`GPR_WIDTH)/8;b<=7;b=b+1) begin : dvc_byte
@ -746,7 +746,7 @@ generate begin : dvc_2t
.din(ex0_s3_v_q),
.dout(ex1_s3_v_q)
);
generate begin : ex1_gpr_s1_xu0_sel_gen
generate if(1) begin : ex1_gpr_s1_xu0_sel_gen
genvar i;
for (i=2;i<=8;i=i+1) begin : ex1_gpr_s1_xu0_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu0_sel_latch(
@ -766,7 +766,7 @@ generate begin : ex1_gpr_s1_xu0_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s2_xu0_sel_gen
generate if(1) begin : ex1_gpr_s2_xu0_sel_gen
genvar i;
for (i=2;i<=8;i=i+1) begin : ex1_gpr_s2_xu0_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu0_sel_latch(
@ -786,7 +786,7 @@ generate begin : ex1_gpr_s2_xu0_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s1_xu1_sel_gen
generate if(1) begin : ex1_gpr_s1_xu1_sel_gen
genvar i;
for (i=2;i<=5;i=i+1) begin : ex1_gpr_s1_xu1_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu1_sel_latch(
@ -806,7 +806,7 @@ generate begin : ex1_gpr_s1_xu1_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s2_xu1_sel_gen
generate if(1) begin : ex1_gpr_s2_xu1_sel_gen
genvar i;
for (i=2;i<=5;i=i+1) begin : ex1_gpr_s2_xu1_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu1_sel_latch(
@ -826,7 +826,7 @@ generate begin : ex1_gpr_s2_xu1_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s1_lq_sel_gen
generate if(1) begin : ex1_gpr_s1_lq_sel_gen
genvar i;
for (i=5;i<=8;i=i+1) begin : ex1_gpr_s1_lq_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_lq_sel_latch(
@ -846,7 +846,7 @@ generate begin : ex1_gpr_s1_lq_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s2_lq_sel_gen
generate if(1) begin : ex1_gpr_s2_lq_sel_gen
genvar i;
for (i=5;i<=8;i=i+1) begin : ex1_gpr_s2_lq_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_lq_sel_latch(
@ -880,7 +880,7 @@ endgenerate
.din({8{dec_byp_ex0_rs2_sel_imm}}),
.dout(ex1_gpr_s2_imm_sel_q)
);
generate begin : ex1_spr_s3_xu0_sel_gen
generate if(1) begin : ex1_spr_s3_xu0_sel_gen
genvar i;
for (i=3;i<=8;i=i+1) begin : ex1_spr_s3_xu0_sel_entry
tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu0_sel_latch(
@ -900,7 +900,7 @@ generate begin : ex1_spr_s3_xu0_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s3_xu1_sel_gen
generate if(1) begin : ex1_spr_s3_xu1_sel_gen
genvar i;
for (i=3;i<=5;i=i+1) begin : ex1_spr_s3_xu1_sel_entry
tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu1_sel_latch(
@ -920,7 +920,7 @@ generate begin : ex1_spr_s3_xu1_sel_gen
end
end
endgenerate
generate begin : ex1_spr_s3_lq_sel_gen
generate if(1) begin : ex1_spr_s3_lq_sel_gen
genvar i;
for (i=5;i<=6;i=i+1) begin : ex1_spr_s3_lq_sel_entry
tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_lq_sel_latch(
@ -940,7 +940,7 @@ generate begin : ex1_spr_s3_lq_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s1_rel_sel_gen
generate if(1) begin : ex1_gpr_s1_rel_sel_gen
genvar i;
for (i=3;i<=4;i=i+1) begin : ex1_gpr_s1_rel_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_rel_sel_latch(
@ -960,7 +960,7 @@ generate begin : ex1_gpr_s1_rel_sel_gen
end
end
endgenerate
generate begin : ex1_gpr_s2_rel_sel_gen
generate if(1) begin : ex1_gpr_s2_rel_sel_gen
genvar i;
for (i=3;i<=4;i=i+1) begin : ex1_gpr_s2_rel_sel_entry
tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_rel_sel_latch(

9
dev/verilog/work/xu_spr.v
Unescape Escape View File

@ -904,8 +904,7 @@ module xu_spr
.gnd(gnd)
);

generate
begin : threads
generate if(1) begin : threads
genvar t;
for (t = 0; t <= `THREADS - 1; t = t + 1)
begin : thread
@ -1265,8 +1264,7 @@ module xu_spr
.din(reset_wd_request_d),
.dout(reset_wd_request_q)
);
generate
begin : int_rest_ifar_latch_gen
generate if(1) begin : int_rest_ifar_latch_gen
genvar r;
for (r = 0; r <= `THREADS-1; r = r + 1)
begin : thread
@ -1753,8 +1751,7 @@ module xu_spr
tri_plat #(.WIDTH(1)) perv_2to1_reg_13 (.din(fce_2 ),.q(fce_1 ),.vd(vdd),.gd(gnd),.clk(clk),
.rst(rst),.flush(pc_xu_ccflush_dc));

generate
begin : perv_1to0_reg_gen
generate if(1) begin : perv_1to0_reg_gen
genvar t;
for (t = 0; t <= `THREADS; t = t + 1)
begin : thread

9
dev/verilog/work/xu_spr_cspr.v
Unescape Escape View File

@ -1060,8 +1060,7 @@ assign power_savings_en = ^spr_ccr0_pme & // Power Management Enabled

// WAIT[WC](0) = Resume on Imp. Specific
// WAIT[WC](1) = Resume on no reservation
generate
begin : pm_wake_up_gen
generate if(1) begin : pm_wake_up_gen
genvar t;
for (t=0;t<=`THREADS-1;t=t+1)
begin : thread
@ -1181,8 +1180,7 @@ assign perf_event_en_d = ( tspr_msr_pr & {`THREADS{pc_xu_event_c

wire [0:16*`THREADS-1] perf_events;
wire [0:0] core_event;
generate
begin : perf_count
generate if(1) begin : perf_count
genvar t;
for (t = 0; t <= `THREADS - 1; t = t + 1)
begin : thread
@ -1381,8 +1379,7 @@ wire [0:0] core_event;

assign cspr_tspr_dbell_pirtag = lq_xu_dbell_pirtag_q;

generate
begin : dbell
generate if(1) begin : dbell
genvar t;
for (t=0;t<=`THREADS-1;t=t+1)
begin : thread

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