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build_smt2 | 11 months ago | |
build_st | 11 months ago | |
build_sweetpea | 11 months ago | |
A2L2.py | 10 months ago | |
A2O.py | 10 months ago | |
Makefile.node | 10 months ago | |
Makefile.smt2 | 11 months ago | |
Makefile.st | 10 months ago | |
Makefile.sweetpea | 11 months ago | |
Makefile.verilator | 11 months ago | |
OPEnv.py | 10 months ago | |
boot.lst | 11 months ago | |
cocotb_icarus.v | 11 months ago | |
cocotb_icarus_node.v | 10 months ago | |
makegtkw | 11 months ago | |
pyvcd.gtkw | 11 months ago | |
readme.md | 10 months ago | |
results.xml | 11 months ago | |
sim.png | 11 months ago | |
sim.txt | 10 months ago | |
tb.py | 10 months ago | |
tb_node.py | 10 months ago | |
verilog | 11 months ago | |
wtf.gtkw | 10 months ago |
readme.md
Cocotb Sim Experiments
Core-only version with partial implementation of Python A2L2 interface
- testbench provides memory using A2 core-L2 interface
make -f Makefile.st build |& grep -v Anac
Core+wrapper version with partial implementation of A2Node
- testbench provides memory using simple RAM interface
make -f Makefile.node build |& grep -v Anac
Core+wrapper version with implementation of A2Node (Wishbone system bus)
- testbench provides Wishbone interface
- can be easily dropped into Litex, etc. for Verilator and FPGA
- can add L2 mem
- can add multiple core intefaces (SMP)
- can add multicore+heterogeneous cores (mixed A2L2, WB-1, WB-2)