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a2o
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The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
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a2o/dev/sim/coco
openpowerwtf a3c25ddd99
runs test3 		10 months ago
..
build_smt2 add dev 11 months ago
build_st init 11 months ago
build_sweetpea add dev 11 months ago
A2L2.py testing a2onode 10 months ago
A2O.py hang detect 10 months ago
Makefile.node tie pervasive sigs in rtl 10 months ago
Makefile.smt2 init 11 months ago
Makefile.st random tst, bios 10 months ago
Makefile.sweetpea add dev 11 months ago
Makefile.verilator add dev 11 months ago
OPEnv.py fix short stores 10 months ago
boot.lst add dev 11 months ago
cocotb_icarus.v add dev 11 months ago
cocotb_icarus_node.v tie pervasive sigs in rtl 10 months ago
makegtkw add dev 11 months ago
pyvcd.gtkw add dev 11 months ago
readme.md runs test3 10 months ago
results.xml init 11 months ago
sim.png add dev 11 months ago
sim.txt runs test3 10 months ago
tb.py testing a2onode 10 months ago
tb_node.py runs test3 10 months ago
verilog add dev 11 months ago
wtf.gtkw random tst, bios 10 months ago

readme.md

Cocotb Sim Experiments

Core-only version with partial implementation of Python A2L2 interface

  • testbench provides memory using A2 core-L2 interface
make -f Makefile.st build |& grep -v Anac

Core+wrapper version with partial implementation of A2Node

  • testbench provides memory using simple RAM interface
make -f Makefile.node build |& grep -v Anac

Core+wrapper version with implementation of A2Node (Wishbone system bus)

  • testbench provides Wishbone interface
  • can be easily dropped into Litex, etc. for Verilator and FPGA
  • can add L2 mem
  • can add multiple core intefaces (SMP)
  • can add multicore+heterogeneous cores (mixed A2L2, WB-1, WB-2)