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a2o/dev/sim/coco
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openpowerwtf a3c25ddd99 runs test3 2 years ago
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A2L2.py testing a2onode 2 years ago
A2O.py hang detect 2 years ago
Makefile.node tie pervasive sigs in rtl 2 years ago
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OPEnv.py fix short stores 2 years ago
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cocotb_icarus.v add dev 2 years ago
cocotb_icarus_node.v tie pervasive sigs in rtl 2 years ago
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wtf.gtkw random tst, bios 2 years ago

readme.md

Cocotb Sim Experiments

Core-only version with partial implementation of Python A2L2 interface

  • testbench provides memory using A2 core-L2 interface
make -f Makefile.st build |& grep -v Anac

Core+wrapper version with partial implementation of A2Node

  • testbench provides memory using simple RAM interface
make -f Makefile.node build |& grep -v Anac

Core+wrapper version with implementation of A2Node (Wishbone system bus)

  • testbench provides Wishbone interface
  • can be easily dropped into Litex, etc. for Verilator and FPGA
  • can add L2 mem
  • can add multiple core intefaces (SMP)
  • can add multicore+heterogeneous cores (mixed A2L2, WB-1, WB-2)