The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue
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openpowerwtf d262ec40a4 fix set_ and xucr0 init 10 months ago
..
arcitst.h test3 - cpl hang in results save 11 months ago
arcitst.lst random tst, bios 10 months ago
arcitst.o random tst, bios 10 months ago
arcitst.s random tst, bios 10 months ago
bin test3 - cpl hang in results save 11 months ago
bios.c fix set_ and xucr0 init 10 months ago
bios.h fix set_ and xucr0 init 10 months ago
bios.o fix set_ and xucr0 init 10 months ago
boot.s random tst, bios 10 months ago
build random tst, bios 10 months ago
build_litex_base random tst, bios 10 months ago
console.c random tst, bios 10 months ago
cpl_hang.png test3 - cpl hang in results save 11 months ago
crt0.lst random tst, bios 10 months ago
crt0.o random tst, bios 10 months ago
defines.s test3 - cpl hang in results save 11 months ago
fx_alucmpbr.tst test3 - cpl hang in results save 11 months ago
liblitex.h random tst, bios 10 months ago
linker.ld random tst, bios 10 months ago
litex random tst, bios 10 months ago
readme.md random tst, bios 10 months ago
regions.ld random tst, bios 10 months ago
rom fix set_ and xucr0 init 10 months ago
rom.bin fix set_ and xucr0 init 10 months ago
rom.d fix set_ and xucr0 init 10 months ago
rom.init fix set_ and xucr0 init 10 months ago
rom.s fix set_ and xucr0 init 10 months ago
test3 test3 - cpl hang in results save 11 months ago

readme.md

test3 - kernel+bios+arci

  • gen, convert, and link random tst (fx_alucmpbr.tst), and try to run
build

# create mem file for coco sim
cp rom.init test3

methodology

  1. produce tst.s (stub code and tst definition) and link with kernel/bios
  2. tst init is done in tst.s
  3. jmp2tst
  4. tst ends (bla through kernel, sc, etc.)
  5. tst cleanup is done in tst.s
  6. tst checking, etc. is done in bios

debug

  • hanging during results save; itags not executed in cpl queue

  • itags 07-0B are dispatched but not marked 'executed' in cplq; they were sent to stq

  • not documented completely in spec (CPCR2, CPCR3, CPCR4, CPCR5); 2/3 are for hi-pri and 4/5 for med(?)

    assign spr_t0_cpcr2_fx0_cnt = cpcr2_l2[0][35:39];
    assign spr_t0_cpcr2_fx1_cnt = cpcr2_l2[0][43:47];
    assign spr_t0_cpcr2_lq_cnt = cpcr2_l2[0][51:55];
    assign spr_t0_cpcr2_sq_cnt = cpcr2_l2[0][59:63];
    assign spr_t0_cpcr3_fu0_cnt = cpcr3_l2[0][43:47];
    assign spr_t0_cpcr3_fu1_cnt = cpcr3_l2[0][51:55];
    assign spr_t0_cpcr3_cp_cnt = cpcr3_l2[0][57:63];
    assign spr_t0_cpcr4_fx0_cnt = cpcr4_l2[0][35:39];
    assign spr_t0_cpcr4_fx1_cnt = cpcr4_l2[0][43:47];
    assign spr_t0_cpcr4_lq_cnt = cpcr4_l2[0][51:55];
    assign spr_t0_cpcr4_sq_cnt = cpcr4_l2[0][59:63];
    assign spr_t0_cpcr5_fu0_cnt = cpcr5_l2[0][43:47];
    assign spr_t0_cpcr5_fu1_cnt = cpcr5_l2[0][51:55];
    assign spr_t0_cpcr5_cp_cnt = cpcr5_l2[0][57:63];
    
  • verilog violation in iuq_dispatch! unused thread 1 strand bits skipping force to 0, and used later as x's for credit checks which didn't stop dispatch

//wtf (THREADS1 is def'd)
// iverilog sez: ../../verilog/work/iuq_dispatch.v:2322: warning: @* found no sensitivities so it will never trigger.
// seems to be correct behavior - block won't be entered without a value change
// make it initial, or a generate?
`ifdef THREADS1
   //always @(*)
   initial

printf from litex

add putchar function to store to memory buffer

/home/wtf/projects/litex/litex/soc/software/libbase/vsnprintf.c

plus at least these:

from /home/wtf/projects/litex/litex/soc/software/include/base/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <ctype.h>
#include <math.h>
#include <stddef.h>

from /home/wtf/projects/litex/litex/soc/software/include/fdlibm
#include <fdlibm.h>