micropython only requires 512kB of BRAM

Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/7/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent 1aadee281d
commit 1fa0b332ca

@ -26,7 +26,7 @@ begin
wishbone_out => wishbone_out, registers => registers, terminate_out => terminate); wishbone_out => wishbone_out, registers => registers, terminate_out => terminate);


simple_ram_0: entity work.simple_ram_behavioural simple_ram_0: entity work.simple_ram_behavioural
generic map ( filename => "simple_ram_behavioural.bin", size => 1048576) generic map ( filename => "simple_ram_behavioural.bin", size => 524288)
port map (clk => clk, rst => rst, wishbone_in => wishbone_out, wishbone_out => wishbone_in); port map (clk => clk, rst => rst, wishbone_in => wishbone_out, wishbone_out => wishbone_in);


clk_process: process clk_process: process

@ -13,7 +13,7 @@ use work.wishbone_types.all;
-- 0xc0002000: UART0 (for host communication) -- 0xc0002000: UART0 (for host communication)
entity toplevel is entity toplevel is
generic ( generic (
MEMORY_SIZE : positive := 1048576; MEMORY_SIZE : positive := 524288;
RAM_INIT_FILE : string := "firmware.hex"); RAM_INIT_FILE : string := "firmware.hex");
port( port(
clk : in std_logic; clk : in std_logic;

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