Merge pull request #7 from riktw/fusesoc_arty_a7

Fusesoc arty a7

fpga/arty_a7-35.xdc

@@ -0,0 +1,7 @@
+set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }];
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk }];
+
+set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { reset_n }]; #mapped to SW0
+
+set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }]; 
+set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];

microwatt.core

@@ -49,6 +49,12 @@ filesets:
       - fpga/nexys-video.xdc : {file_type : xdc}
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
       
+  arty_a7-35:
+    files:
+      - fpga/arty_a7-35.xdc : {file_type : xdc}
+      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+  
+
 targets:
   nexys_a7:
     default_tool: vivado
@@ -66,6 +72,14 @@ targets:
       vivado: {part : xc7a200tsbg484-1}
     toplevel : toplevel
     
+  arty_a7-35:
+    default_tool: vivado
+    filesets: [core, arty_a7-35, soc]
+    parameters : [memory_size, ram_init_file]
+    tools:
+      vivado: {part : xc7a35ticsg324-1L}
+    toplevel : toplevel
+
   synth:
     filesets: [core]
     tools: