Merge pull request #7 from riktw/fusesoc_arty_a7

Fusesoc arty a7
pull/10/head
Anton Blanchard 5 years ago committed by GitHub
commit 3819768d2a
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@ -0,0 +1,7 @@
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk }];

set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { reset_n }]; #mapped to SW0

set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];

@ -48,6 +48,12 @@ filesets:
files: files:
- fpga/nexys-video.xdc : {file_type : xdc} - fpga/nexys-video.xdc : {file_type : xdc}
- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
arty_a7-35:
files:
- fpga/arty_a7-35.xdc : {file_type : xdc}
- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}


targets: targets:
nexys_a7: nexys_a7:
@ -65,6 +71,14 @@ targets:
tools: tools:
vivado: {part : xc7a200tsbg484-1} vivado: {part : xc7a200tsbg484-1}
toplevel : toplevel toplevel : toplevel
arty_a7-35:
default_tool: vivado
filesets: [core, arty_a7-35, soc]
parameters : [memory_size, ram_init_file]
tools:
vivado: {part : xc7a35ticsg324-1L}
toplevel : toplevel


synth: synth:
filesets: [core] filesets: [core]

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