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Merge pull request #409 from CodeConstruct/dev/soc-reset

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Make syscon SOC reset work
pull/417/head
Michael Neuling 2 years ago committed by GitHub
parent 7d928200b8 56f1c41e9c
commit da5d3ded3c
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GPG Key ID: 4AEE18F83AFDEB23
29 changed files with 99455 additions and 97916 deletions
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5
core_dram_tb.vhdl
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@ -32,7 +32,6 @@ architecture behave of core_dram_tb is
signal wb_ext_io_out : wb_io_slave_out; signal wb_ext_io_out : wb_io_slave_out;
signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_csr : std_ulogic;
signal wb_ext_is_dram_init : std_ulogic; signal wb_ext_is_dram_init : std_ulogic;
signal core_alt_reset : std_ulogic;


-- SPI -- SPI
signal spi_sck : std_ulogic; signal spi_sck : std_ulogic;
@ -84,8 +83,7 @@ begin
spi_flash_cs_n => spi_cs_n, spi_flash_cs_n => spi_cs_n,
spi_flash_sdat_o => spi_sdat_o, spi_flash_sdat_o => spi_sdat_o,
spi_flash_sdat_oe => spi_sdat_oe, spi_flash_sdat_oe => spi_sdat_oe,
spi_flash_sdat_i => spi_sdat_i, spi_flash_sdat_i => spi_sdat_i
alt_reset => core_alt_reset
); );


flash: entity work.s25fl128s flash: entity work.s25fl128s
@ -135,7 +133,6 @@ begin
rst => rst, rst => rst,
system_clk => system_clk, system_clk => system_clk,
system_reset => soc_rst, system_reset => soc_rst,
core_alt_reset => core_alt_reset,


wb_in => wb_dram_in, wb_in => wb_dram_in,
wb_out => wb_dram_out, wb_out => wb_dram_out,

1
dram_tb.vhdl
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@ -58,7 +58,6 @@ begin
rst => rst, rst => rst,
system_clk => clk, system_clk => clk,
system_reset => soc_rst, system_reset => soc_rst,
core_alt_reset => open,
pll_locked => open, pll_locked => open,


wb_in => wb_in, wb_in => wb_in,

8
fpga/top-acorn-cle-215.vhdl
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@ -84,9 +84,6 @@ architecture behaviour of toplevel is
signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_csr : std_ulogic;
signal wb_ext_is_dram_init : std_ulogic; signal wb_ext_is_dram_init : std_ulogic;


-- Control/status
signal core_alt_reset : std_ulogic;

-- SPI flash -- SPI flash
signal spi_sck : std_ulogic; signal spi_sck : std_ulogic;
signal spi_cs_n : std_ulogic; signal spi_cs_n : std_ulogic;
@ -162,8 +159,7 @@ begin
wb_ext_io_in => wb_ext_io_in, wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out, wb_ext_io_out => wb_ext_io_out,
wb_ext_is_dram_csr => wb_ext_is_dram_csr, wb_ext_is_dram_csr => wb_ext_is_dram_csr,
wb_ext_is_dram_init => wb_ext_is_dram_init, wb_ext_is_dram_init => wb_ext_is_dram_init
alt_reset => core_alt_reset
); );


-- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2
@ -231,7 +227,6 @@ begin
led1 <= pll_rst; led1 <= pll_rst;
led2 <= not system_clk_locked; led2 <= not system_clk_locked;
led3 <= '0'; led3 <= '0';
core_alt_reset <= '0';


-- Vivado barfs on those differential signals if left -- Vivado barfs on those differential signals if left
-- unconnected. So instanciate a diff. buffer and feed -- unconnected. So instanciate a diff. buffer and feed
@ -289,7 +284,6 @@ begin
rst => pll_rst, rst => pll_rst,
system_clk => system_clk, system_clk => system_clk,
system_reset => soc_rst, system_reset => soc_rst,
core_alt_reset => core_alt_reset,
pll_locked => system_clk_locked, pll_locked => system_clk_locked,


wb_in => wb_dram_in, wb_in => wb_dram_in,

10
fpga/top-antmicro-artix-dc-scm.vhdl
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@ -121,9 +121,6 @@ architecture behaviour of toplevel is
-- for conversion from non-pipelined wishbone to pipelined -- for conversion from non-pipelined wishbone to pipelined
signal wb_sddma_stb_sent : std_ulogic; signal wb_sddma_stb_sent : std_ulogic;


-- Control/status
signal core_alt_reset : std_ulogic;

-- Status LED -- Status LED
signal led0_b_pwm : std_ulogic; signal led0_b_pwm : std_ulogic;
signal led0_r_pwm : std_ulogic; signal led0_r_pwm : std_ulogic;
@ -240,9 +237,7 @@ begin


-- DMA wishbone -- DMA wishbone
wishbone_dma_in => wb_sddma_in, wishbone_dma_in => wb_sddma_in,
wishbone_dma_out => wb_sddma_out, wishbone_dma_out => wb_sddma_out

alt_reset => core_alt_reset
); );




@ -303,8 +298,6 @@ begin
pll_locked_out => system_clk_locked pll_locked_out => system_clk_locked
); );


core_alt_reset <= '0';

d11_led <= '0'; d11_led <= '0';
d12_led <= soc_rst; d12_led <= soc_rst;
d13_led <= system_clk; d13_led <= system_clk;
@ -376,7 +369,6 @@ begin
rst => pll_rst, rst => pll_rst,
system_clk => system_clk, system_clk => system_clk,
system_reset => dram_sys_rst, system_reset => dram_sys_rst,
core_alt_reset => core_alt_reset,
pll_locked => system_clk_locked, pll_locked => system_clk_locked,


wb_in => wb_dram_in, wb_in => wb_dram_in,

32
fpga/top-arty.vhdl
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@ -104,6 +104,8 @@ architecture behaviour of toplevel is
-- Reset signals: -- Reset signals:
signal soc_rst : std_ulogic; signal soc_rst : std_ulogic;
signal pll_rst : std_ulogic; signal pll_rst : std_ulogic;
signal sw_rst : std_ulogic;
signal periph_rst : std_ulogic;


-- Internal clock signals: -- Internal clock signals:
signal system_clk : std_ulogic; signal system_clk : std_ulogic;
@ -139,9 +141,6 @@ architecture behaviour of toplevel is
-- for conversion from non-pipelined wishbone to pipelined -- for conversion from non-pipelined wishbone to pipelined
signal wb_sddma_stb_sent : std_ulogic; signal wb_sddma_stb_sent : std_ulogic;


-- Control/status
signal core_alt_reset : std_ulogic;

-- Status LED -- Status LED
signal led0_b_pwm : std_ulogic; signal led0_b_pwm : std_ulogic;
signal led0_r_pwm : std_ulogic; signal led0_r_pwm : std_ulogic;
@ -219,6 +218,7 @@ begin
-- System signals -- System signals
system_clk => system_clk, system_clk => system_clk,
rst => soc_rst, rst => soc_rst,
sw_soc_reset => sw_rst,


-- UART signals -- UART signals
uart0_txd => uart_main_tx, uart0_txd => uart_main_tx,
@ -258,9 +258,7 @@ begin


-- DMA wishbone -- DMA wishbone
wishbone_dma_in => wb_sddma_in, wishbone_dma_in => wb_sddma_in,
wishbone_dma_out => wb_sddma_out, wishbone_dma_out => wb_sddma_out

alt_reset => core_alt_reset
); );


--uart_pmod_rts_n <= '0'; --uart_pmod_rts_n <= '0';
@ -304,6 +302,7 @@ begin


nodram: if not USE_LITEDRAM generate nodram: if not USE_LITEDRAM generate
signal ddram_clk_dummy : std_ulogic; signal ddram_clk_dummy : std_ulogic;
signal gen_rst : std_ulogic;
begin begin
reset_controller: entity work.soc_reset reset_controller: entity work.soc_reset
generic map( generic map(
@ -315,9 +314,11 @@ begin
pll_locked_in => system_clk_locked and eth_clk_locked, pll_locked_in => system_clk_locked and eth_clk_locked,
ext_rst_in => ext_rst_n, ext_rst_in => ext_rst_n,
pll_rst_out => pll_rst, pll_rst_out => pll_rst,
rst_out => soc_rst rst_out => gen_rst
); );


soc_rst <= gen_rst;

clkgen: entity work.clock_generator clkgen: entity work.clock_generator
generic map( generic map(
CLK_INPUT_HZ => 100000000, CLK_INPUT_HZ => 100000000,
@ -333,7 +334,6 @@ begin
led0_b_pwm <= '1'; led0_b_pwm <= '1';
led0_r_pwm <= '1'; led0_r_pwm <= '1';
led0_g_pwm <= '0'; led0_g_pwm <= '0';
core_alt_reset <= '0';


-- Vivado barfs on those differential signals if left -- Vivado barfs on those differential signals if left
-- unconnected. So instanciate a diff. buffer and feed -- unconnected. So instanciate a diff. buffer and feed
@ -351,8 +351,7 @@ begin
has_dram: if USE_LITEDRAM generate has_dram: if USE_LITEDRAM generate
signal dram_init_done : std_ulogic; signal dram_init_done : std_ulogic;
signal dram_init_error : std_ulogic; signal dram_init_error : std_ulogic;
signal dram_sys_rst : std_ulogic; signal gen_rst : std_ulogic;
signal rst_gen_rst : std_ulogic;
begin begin


-- Eventually dig out the frequency from the generator -- Eventually dig out the frequency from the generator
@ -371,7 +370,7 @@ begin
pll_locked_in => eth_clk_locked, pll_locked_in => eth_clk_locked,
ext_rst_in => ext_rst_n, ext_rst_in => ext_rst_n,
pll_rst_out => pll_rst, pll_rst_out => pll_rst,
rst_out => rst_gen_rst rst_out => open
); );


-- Generate SoC reset -- Generate SoC reset
@ -380,7 +379,7 @@ begin
if ext_rst_n = '0' then if ext_rst_n = '0' then
soc_rst <= '1'; soc_rst <= '1';
elsif rising_edge(system_clk) then elsif rising_edge(system_clk) then
soc_rst <= dram_sys_rst or not eth_clk_locked or not system_clk_locked; soc_rst <= gen_rst or not eth_clk_locked or not system_clk_locked;
end if; end if;
end process; end process;


@ -401,8 +400,7 @@ begin
clk_in => ext_clk, clk_in => ext_clk,
rst => pll_rst, rst => pll_rst,
system_clk => system_clk, system_clk => system_clk,
system_reset => dram_sys_rst, system_reset => gen_rst,
core_alt_reset => core_alt_reset,
pll_locked => system_clk_locked, pll_locked => system_clk_locked,


wb_in => wb_dram_in, wb_in => wb_dram_in,
@ -438,6 +436,8 @@ begin


end generate; end generate;


periph_rst <= soc_rst or sw_rst;

has_liteeth : if USE_LITEETH generate has_liteeth : if USE_LITEETH generate


component liteeth_core port ( component liteeth_core port (
@ -527,7 +527,7 @@ begin
liteeth : liteeth_core liteeth : liteeth_core
port map( port map(
sys_clock => system_clk, sys_clock => system_clk,
sys_reset => soc_rst, sys_reset => periph_rst,
mii_eth_clocks_tx => eth_clocks_tx, mii_eth_clocks_tx => eth_clocks_tx,
mii_eth_clocks_rx => eth_clocks_rx, mii_eth_clocks_rx => eth_clocks_rx,
mii_eth_rst_n => eth_rst_n, mii_eth_rst_n => eth_rst_n,
@ -615,7 +615,7 @@ begin
litesdcard : litesdcard_core litesdcard : litesdcard_core
port map ( port map (
clk => system_clk, clk => system_clk,
rst => soc_rst, rst => periph_rst,
wb_ctrl_adr => wb_sdcard_adr, wb_ctrl_adr => wb_sdcard_adr,
wb_ctrl_dat_w => wb_ext_io_in.dat, wb_ctrl_dat_w => wb_ext_io_in.dat,
wb_ctrl_dat_r => wb_sdcard_out.dat, wb_ctrl_dat_r => wb_sdcard_out.dat,

8
fpga/top-genesys2.vhdl
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@ -87,9 +87,6 @@ architecture behaviour of toplevel is
signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_csr : std_ulogic;
signal wb_ext_is_dram_init : std_ulogic; signal wb_ext_is_dram_init : std_ulogic;


-- Control/status
signal core_alt_reset : std_ulogic;

-- SPI flash -- SPI flash
signal spi_sck : std_ulogic; signal spi_sck : std_ulogic;
signal spi_cs_n : std_ulogic; signal spi_cs_n : std_ulogic;
@ -165,8 +162,7 @@ begin
wb_ext_io_in => wb_ext_io_in, wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out, wb_ext_io_out => wb_ext_io_out,
wb_ext_is_dram_csr => wb_ext_is_dram_csr, wb_ext_is_dram_csr => wb_ext_is_dram_csr,
wb_ext_is_dram_init => wb_ext_is_dram_init, wb_ext_is_dram_init => wb_ext_is_dram_init
alt_reset => core_alt_reset
); );


-- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2
@ -234,7 +230,6 @@ begin
led1 <= pll_rst; led1 <= pll_rst;
led2 <= not system_clk_locked; led2 <= not system_clk_locked;
led3 <= '0'; led3 <= '0';
core_alt_reset <= '0';


-- Vivado barfs on those differential signals if left -- Vivado barfs on those differential signals if left
-- unconnected. So instanciate a diff. buffer and feed -- unconnected. So instanciate a diff. buffer and feed
@ -292,7 +287,6 @@ begin
rst => pll_rst, rst => pll_rst,
system_clk => system_clk, system_clk => system_clk,
system_reset => soc_rst, system_reset => soc_rst,
core_alt_reset => core_alt_reset,
pll_locked => system_clk_locked, pll_locked => system_clk_locked,


wb_in => wb_dram_in, wb_in => wb_dram_in,

9
fpga/top-nexys-video.vhdl
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@ -128,9 +128,6 @@ architecture behaviour of toplevel is
-- for conversion from non-pipelined wishbone to pipelined -- for conversion from non-pipelined wishbone to pipelined
signal wb_sddma_stb_sent : std_ulogic; signal wb_sddma_stb_sent : std_ulogic;


-- Control/status
signal core_alt_reset : std_ulogic;

-- SPI flash -- SPI flash
signal spi_sck : std_ulogic; signal spi_sck : std_ulogic;
signal spi_cs_n : std_ulogic; signal spi_cs_n : std_ulogic;
@ -220,9 +217,7 @@ begin


-- DMA wishbone -- DMA wishbone
wishbone_dma_in => wb_sddma_in, wishbone_dma_in => wb_sddma_in,
wishbone_dma_out => wb_sddma_out, wishbone_dma_out => wb_sddma_out

alt_reset => core_alt_reset
); );


-- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2
@ -282,7 +277,6 @@ begin
led0 <= '1'; led0 <= '1';
led1 <= not soc_rst; led1 <= not soc_rst;
led2 <= '0'; led2 <= '0';
core_alt_reset <= '0';


-- Vivado barfs on those differential signals if left -- Vivado barfs on those differential signals if left
-- unconnected. So instanciate a diff. buffer and feed -- unconnected. So instanciate a diff. buffer and feed
@ -350,7 +344,6 @@ begin
rst => pll_rst, rst => pll_rst,
system_clk => system_clk, system_clk => system_clk,
system_reset => dram_sys_rst, system_reset => dram_sys_rst,
core_alt_reset => core_alt_reset,
pll_locked => system_clk_locked, pll_locked => system_clk_locked,


wb_in => wb_dram_in, wb_in => wb_dram_in,

9
fpga/top-orangecrab0.2.vhdl
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@ -110,9 +110,6 @@ architecture behaviour of toplevel is
-- for conversion from non-pipelined wishbone to pipelined -- for conversion from non-pipelined wishbone to pipelined
signal wb_sddma_stb_sent : std_ulogic; signal wb_sddma_stb_sent : std_ulogic;


-- Control/status
signal core_alt_reset : std_ulogic;

-- Status LED -- Status LED
signal led0_b_pwm : std_ulogic; signal led0_b_pwm : std_ulogic;
signal led0_r_pwm : std_ulogic; signal led0_r_pwm : std_ulogic;
@ -231,9 +228,7 @@ begin


-- DMA wishbone -- DMA wishbone
wishbone_dma_in => wb_sddma_in, wishbone_dma_in => wb_sddma_in,
wishbone_dma_out => wb_sddma_out, wishbone_dma_out => wb_sddma_out

alt_reset => core_alt_reset
); );


-- SPI Flash -- SPI Flash
@ -284,7 +279,6 @@ begin
led0_b_pwm <= '1'; led0_b_pwm <= '1';
led0_r_pwm <= '1'; led0_r_pwm <= '1';
led0_g_pwm <= '0'; led0_g_pwm <= '0';
core_alt_reset <= '0';


end generate; end generate;


@ -341,7 +335,6 @@ begin
rst => pll_rst, rst => pll_rst,
system_clk => system_clk, system_clk => system_clk,
system_reset => dram_sys_rst, system_reset => dram_sys_rst,
core_alt_reset => core_alt_reset,
pll_locked => system_clk_locked, pll_locked => system_clk_locked,


wb_in => wb_dram_in, wb_in => wb_dram_in,

10
fpga/top-wukong-v2.vhdl
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@ -128,9 +128,6 @@ architecture behaviour of toplevel is
-- for conversion from non-pipelined wishbone to pipelined -- for conversion from non-pipelined wishbone to pipelined
signal wb_sddma_stb_sent : std_ulogic; signal wb_sddma_stb_sent : std_ulogic;


-- Control/status
signal core_alt_reset : std_ulogic;

-- SPI flash -- SPI flash
signal spi_sck : std_ulogic; signal spi_sck : std_ulogic;
signal spi_cs_n : std_ulogic; signal spi_cs_n : std_ulogic;
@ -225,9 +222,7 @@ begin


-- DMA wishbone -- DMA wishbone
wishbone_dma_in => wb_sddma_in, wishbone_dma_in => wb_sddma_in,
wishbone_dma_out => wb_sddma_out, wishbone_dma_out => wb_sddma_out

alt_reset => core_alt_reset
); );


-- SPI Flash -- SPI Flash
@ -282,8 +277,6 @@ begin
pll_locked_out => system_clk_locked pll_locked_out => system_clk_locked
); );


core_alt_reset <= '0';

-- Vivado barfs on those differential signals if left -- Vivado barfs on those differential signals if left
-- unconnected. So instanciate a diff. buffer and feed -- unconnected. So instanciate a diff. buffer and feed
-- it a constant '0'. -- it a constant '0'.
@ -351,7 +344,6 @@ begin
rst => pll_rst, rst => pll_rst,
system_clk => system_clk, system_clk => system_clk,
system_reset => dram_sys_rst, system_reset => dram_sys_rst,
core_alt_reset => core_alt_reset,
pll_locked => system_clk_locked, pll_locked => system_clk_locked,


wb_in => wb_dram_in, wb_in => wb_dram_in,

1
include/microwatt_soc.h
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@ -52,6 +52,7 @@
#define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0) #define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0)
#define SYS_REG_CTRL_CORE_RESET (1ull << 1) #define SYS_REG_CTRL_CORE_RESET (1ull << 1)
#define SYS_REG_CTRL_SOC_RESET (1ull << 2) #define SYS_REG_CTRL_SOC_RESET (1ull << 2)
#define SYS_REG_CTRL_ALT_RESET (1ull << 3)
#define SYS_REG_DRAMINITINFO 0x30 #define SYS_REG_DRAMINITINFO 0x30
#define SYS_REG_SPI_INFO 0x38 #define SYS_REG_SPI_INFO 0x38
#define SYS_REG_SPI_INFO_FLASH_OFF_MASK 0xffffffff #define SYS_REG_SPI_INFO_FLASH_OFF_MASK 0xffffffff

4
litedram/extras/litedram-wrapper-l2.vhdl
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@ -44,7 +44,6 @@ entity litedram_wrapper is
rst : in std_ulogic; rst : in std_ulogic;
system_clk : out std_ulogic; system_clk : out std_ulogic;
system_reset : out std_ulogic; system_reset : out std_ulogic;
core_alt_reset : out std_ulogic;
pll_locked : out std_ulogic; pll_locked : out std_ulogic;


-- Wishbone ports: -- Wishbone ports:
@ -420,9 +419,6 @@ begin
assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS) assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
report "geometry bits don't add up" severity FAILURE; report "geometry bits don't add up" severity FAILURE;


-- alternate core reset address set when DRAM is not initialized.
core_alt_reset <= not init_done;

-- Init code BRAM memory slave -- Init code BRAM memory slave
init_ram_0: entity work.dram_init_mem init_ram_0: entity work.dram_init_mem
generic map( generic map(

11
litedram/gen-src/sdram_init/bin2hex.py
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@ -7,11 +7,8 @@ import struct
with open(sys.argv[1], "rb") as f: with open(sys.argv[1], "rb") as f:
while True: while True:
word = f.read(8) word = f.read(8)
if len(word) == 8: if len(word) == 0:
print("%016x" % struct.unpack('Q', word));
elif len(word) == 4:
print("00000000%08x" % struct.unpack('I', word));
elif len(word) == 0:
exit(0); exit(0);
else: if len(word) != 8:
raise Exception("Bad length") word = word + bytes(8 - len(word))
print("%016x" % struct.unpack('Q', word));

6
litedram/gen-src/sdram_init/main.c
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@ -285,10 +285,14 @@ uint64_t main(void)
try_flash = true; try_flash = true;
} }
printf("\n"); printf("\n");
if (ftr & SYS_REG_INFO_HAS_DRAM) { if (ftr & SYS_REG_INFO_HAS_DRAM && !ddrctrl_init_done_read()) {
printf("LiteDRAM built from LiteX %s\n", LITEX_GIT_SHA1); printf("LiteDRAM built from LiteX %s\n", LITEX_GIT_SHA1);
sdram_init(); sdram_init();
} }

val = readq(SYSCON_BASE + SYS_REG_CTRL);
writeq(val & ~SYS_REG_CTRL_ALT_RESET, SYSCON_BASE + SYS_REG_CTRL);

if (ftr & SYS_REG_INFO_HAS_BRAM) { if (ftr & SYS_REG_INFO_HAS_BRAM) {
printf("Booting from BRAM...\n"); printf("Booting from BRAM...\n");
return 0; return 0;

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48
soc.vhdl
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@ -51,6 +51,16 @@ use work.wishbone_types.all;
-- 3 : SD card -- 3 : SD card
-- 4 : GPIO -- 4 : GPIO


-- Resets:
-- The soc can be reset externally by its parent top- entity (via rst port),
-- or can be reset by software via syscon. In the software reset case
-- the reset signal will also be exposed via sw_soc_reset port - toplevels
-- can use that to reset other peripherals if required.
--
-- When using DRAM the alt_reset signal will be high after soc reset, to
-- run sdram init routines. After startup software will switch alt_reset to
-- low, so a core reset will use the non-alt reset address.

entity soc is entity soc is
generic ( generic (
MEMORY_SIZE : natural; MEMORY_SIZE : natural;
@ -129,13 +139,16 @@ entity soc is
gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0); gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0);
gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0'); gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');


-- DRAM controller signals -- SOC reset trigger from syscon
alt_reset : in std_ulogic := '0' sw_soc_reset : out std_ulogic
); );
end entity soc; end entity soc;


architecture behaviour of soc is architecture behaviour of soc is


-- internal reset
signal soc_reset : std_ulogic;

-- Wishbone master signals: -- Wishbone master signals:
signal wishbone_dcore_in : wishbone_slave_out; signal wishbone_dcore_in : wishbone_slave_out;
signal wishbone_dcore_out : wishbone_master_out; signal wishbone_dcore_out : wishbone_master_out;
@ -166,6 +179,7 @@ architecture behaviour of soc is
-- Syscon signals -- Syscon signals
signal dram_at_0 : std_ulogic; signal dram_at_0 : std_ulogic;
signal do_core_reset : std_ulogic; signal do_core_reset : std_ulogic;
signal alt_reset : std_ulogic;
signal wb_syscon_in : wb_io_master_out; signal wb_syscon_in : wb_io_master_out;
signal wb_syscon_out : wb_io_slave_out; signal wb_syscon_out : wb_io_slave_out;


@ -312,18 +326,21 @@ architecture behaviour of soc is


begin begin


-- either external reset, or from syscon
soc_reset <= rst or sw_soc_reset;

resets: process(system_clk) resets: process(system_clk)
begin begin
if rising_edge(system_clk) then if rising_edge(system_clk) then
rst_core <= rst or do_core_reset; rst_core <= soc_reset or do_core_reset;
rst_uart <= rst; rst_uart <= soc_reset;
rst_spi <= rst; rst_spi <= soc_reset;
rst_xics <= rst; rst_xics <= soc_reset;
rst_gpio <= rst; rst_gpio <= soc_reset;
rst_bram <= rst; rst_bram <= soc_reset;
rst_dtm <= rst; rst_dtm <= soc_reset;
rst_wbar <= rst; rst_wbar <= soc_reset;
rst_wbdb <= rst; rst_wbdb <= soc_reset;
alt_reset_d <= alt_reset; alt_reset_d <= alt_reset;
end if; end if;
end process; end process;
@ -482,7 +499,7 @@ begin
if rising_edge(system_clk) then if rising_edge(system_clk) then
do_cyc := '0'; do_cyc := '0';
end_cyc := '0'; end_cyc := '0';
if (rst) then if (soc_reset) then
state := IDLE; state := IDLE;
wb_io_out.ack <= '0'; wb_io_out.ack <= '0';
wb_io_out.stall <= '0'; wb_io_out.stall <= '0';
@ -774,12 +791,13 @@ begin
) )
port map( port map(
clk => system_clk, clk => system_clk,
rst => rst, rst => soc_reset,
wishbone_in => wb_syscon_in, wishbone_in => wb_syscon_in,
wishbone_out => wb_syscon_out, wishbone_out => wb_syscon_out,
dram_at_0 => dram_at_0, dram_at_0 => dram_at_0,
core_reset => do_core_reset, core_reset => do_core_reset,
soc_reset => open -- XXX TODO soc_reset => sw_soc_reset,
alt_reset => alt_reset
); );


-- --
@ -1075,7 +1093,7 @@ begin
wb_x_state: process(system_clk) wb_x_state: process(system_clk)
begin begin
if rising_edge(system_clk) then if rising_edge(system_clk) then
if not rst then if not soc_reset then
-- Wishbone arbiter -- Wishbone arbiter
assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure; assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure; assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;

16
syscon.vhdl
Unescape Escape View File

@ -34,7 +34,8 @@ entity syscon is
-- System control ports -- System control ports
dram_at_0 : out std_ulogic; dram_at_0 : out std_ulogic;
core_reset : out std_ulogic; core_reset : out std_ulogic;
soc_reset : out std_ulogic soc_reset : out std_ulogic;
alt_reset : out std_ulogic
); );
end entity syscon; end entity syscon;


@ -76,10 +77,11 @@ architecture behaviour of syscon is
-- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits -- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits


-- CTRL register bits -- CTRL register bits
constant SYS_REG_CTRL_BITS : positive := 3; constant SYS_REG_CTRL_BITS : positive := 4;
constant SYS_REG_CTRL_DRAM_AT_0 : integer := 0; constant SYS_REG_CTRL_DRAM_AT_0 : integer := 0;
constant SYS_REG_CTRL_CORE_RESET : integer := 1; constant SYS_REG_CTRL_CORE_RESET : integer := 1;
constant SYS_REG_CTRL_SOC_RESET : integer := 2; constant SYS_REG_CTRL_SOC_RESET : integer := 2;
constant SYS_REG_CTRL_ALT_RESET : integer := 3;


-- SPI Info register bits -- SPI Info register bits
-- --
@ -102,6 +104,7 @@ architecture behaviour of syscon is
-- Ctrl register -- Ctrl register
signal reg_ctrl : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0); signal reg_ctrl : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0);
signal reg_ctrl_out : std_ulogic_vector(63 downto 0); signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
signal ctrl_init_alt_reset : std_ulogic;


-- Others -- Others
signal reg_info : std_ulogic_vector(63 downto 0); signal reg_info : std_ulogic_vector(63 downto 0);
@ -128,11 +131,12 @@ architecture behaviour of syscon is
-- Wishbone response latch -- Wishbone response latch
signal wb_rsp : wb_io_slave_out; signal wb_rsp : wb_io_slave_out;
begin begin

-- Generated output signals -- Generated output signals
dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0); dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0);
soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET); soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET);
core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET); core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET);
alt_reset <= reg_ctrl(SYS_REG_CTRL_ALT_RESET);



-- Info register is hard wired -- Info register is hard wired
info_has_uart <= '1' when HAS_UART else '0'; info_has_uart <= '1' when HAS_UART else '0';
@ -211,12 +215,16 @@ begin
end if; end if;
end process; end process;


-- Initial state
ctrl_init_alt_reset <= '1' when HAS_DRAM else '0';

-- Register writes -- Register writes
regs_write: process(clk) regs_write: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if (rst) then if (rst) then
reg_ctrl <= (others => '0'); reg_ctrl <= (SYS_REG_CTRL_ALT_RESET => ctrl_init_alt_reset,
others => '0');
else else
if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then
-- Change this if CTRL ever has more than 32 bits -- Change this if CTRL ever has more than 32 bits

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