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@ -104,6 +104,8 @@ architecture behaviour of toplevel is
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-- Reset signals:
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-- Reset signals:
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signal soc_rst : std_ulogic;
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signal soc_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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signal sw_rst : std_ulogic;
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signal periph_rst : std_ulogic;
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-- Internal clock signals:
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-- Internal clock signals:
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signal system_clk : std_ulogic;
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signal system_clk : std_ulogic;
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@ -139,9 +141,6 @@ architecture behaviour of toplevel is
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-- for conversion from non-pipelined wishbone to pipelined
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-- for conversion from non-pipelined wishbone to pipelined
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signal wb_sddma_stb_sent : std_ulogic;
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signal wb_sddma_stb_sent : std_ulogic;
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-- Control/status
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signal core_alt_reset : std_ulogic;
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-- Status LED
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-- Status LED
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signal led0_b_pwm : std_ulogic;
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signal led0_b_pwm : std_ulogic;
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signal led0_r_pwm : std_ulogic;
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signal led0_r_pwm : std_ulogic;
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@ -219,6 +218,7 @@ begin
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-- System signals
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-- System signals
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system_clk => system_clk,
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system_clk => system_clk,
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rst => soc_rst,
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rst => soc_rst,
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sw_soc_reset => sw_rst,
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-- UART signals
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-- UART signals
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uart0_txd => uart_main_tx,
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uart0_txd => uart_main_tx,
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@ -258,9 +258,7 @@ begin
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-- DMA wishbone
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-- DMA wishbone
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wishbone_dma_in => wb_sddma_in,
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wishbone_dma_in => wb_sddma_in,
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wishbone_dma_out => wb_sddma_out,
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wishbone_dma_out => wb_sddma_out
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alt_reset => core_alt_reset
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);
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);
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--uart_pmod_rts_n <= '0';
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--uart_pmod_rts_n <= '0';
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@ -304,6 +302,7 @@ begin
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nodram: if not USE_LITEDRAM generate
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nodram: if not USE_LITEDRAM generate
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signal ddram_clk_dummy : std_ulogic;
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signal ddram_clk_dummy : std_ulogic;
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signal gen_rst : std_ulogic;
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begin
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begin
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reset_controller: entity work.soc_reset
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reset_controller: entity work.soc_reset
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generic map(
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generic map(
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@ -315,9 +314,11 @@ begin
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pll_locked_in => system_clk_locked and eth_clk_locked,
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pll_locked_in => system_clk_locked and eth_clk_locked,
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ext_rst_in => ext_rst_n,
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ext_rst_in => ext_rst_n,
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pll_rst_out => pll_rst,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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rst_out => gen_rst
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);
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);
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soc_rst <= gen_rst;
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clkgen: entity work.clock_generator
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clkgen: entity work.clock_generator
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generic map(
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generic map(
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CLK_INPUT_HZ => 100000000,
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CLK_INPUT_HZ => 100000000,
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@ -333,7 +334,6 @@ begin
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led0_b_pwm <= '1';
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led0_b_pwm <= '1';
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led0_r_pwm <= '1';
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led0_r_pwm <= '1';
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led0_g_pwm <= '0';
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led0_g_pwm <= '0';
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core_alt_reset <= '0';
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-- Vivado barfs on those differential signals if left
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-- Vivado barfs on those differential signals if left
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-- unconnected. So instanciate a diff. buffer and feed
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-- unconnected. So instanciate a diff. buffer and feed
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@ -351,8 +351,7 @@ begin
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has_dram: if USE_LITEDRAM generate
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has_dram: if USE_LITEDRAM generate
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signal dram_init_done : std_ulogic;
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signal dram_init_done : std_ulogic;
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signal dram_init_error : std_ulogic;
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signal dram_init_error : std_ulogic;
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signal dram_sys_rst : std_ulogic;
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signal gen_rst : std_ulogic;
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signal rst_gen_rst : std_ulogic;
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begin
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begin
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-- Eventually dig out the frequency from the generator
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-- Eventually dig out the frequency from the generator
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@ -371,7 +370,7 @@ begin
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pll_locked_in => eth_clk_locked,
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pll_locked_in => eth_clk_locked,
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ext_rst_in => ext_rst_n,
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ext_rst_in => ext_rst_n,
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pll_rst_out => pll_rst,
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pll_rst_out => pll_rst,
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rst_out => rst_gen_rst
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rst_out => open
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);
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);
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-- Generate SoC reset
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-- Generate SoC reset
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@ -380,7 +379,7 @@ begin
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if ext_rst_n = '0' then
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if ext_rst_n = '0' then
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soc_rst <= '1';
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soc_rst <= '1';
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elsif rising_edge(system_clk) then
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elsif rising_edge(system_clk) then
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soc_rst <= dram_sys_rst or not eth_clk_locked or not system_clk_locked;
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soc_rst <= gen_rst or not eth_clk_locked or not system_clk_locked;
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end if;
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end if;
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end process;
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end process;
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@ -401,8 +400,7 @@ begin
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clk_in => ext_clk,
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clk_in => ext_clk,
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rst => pll_rst,
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rst => pll_rst,
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system_clk => system_clk,
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system_clk => system_clk,
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system_reset => dram_sys_rst,
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system_reset => gen_rst,
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core_alt_reset => core_alt_reset,
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pll_locked => system_clk_locked,
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pll_locked => system_clk_locked,
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wb_in => wb_dram_in,
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wb_in => wb_dram_in,
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@ -438,6 +436,8 @@ begin
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end generate;
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end generate;
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periph_rst <= soc_rst or sw_rst;
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has_liteeth : if USE_LITEETH generate
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has_liteeth : if USE_LITEETH generate
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component liteeth_core port (
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component liteeth_core port (
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@ -527,7 +527,7 @@ begin
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liteeth : liteeth_core
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liteeth : liteeth_core
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port map(
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port map(
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sys_clock => system_clk,
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sys_clock => system_clk,
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sys_reset => soc_rst,
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sys_reset => periph_rst,
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mii_eth_clocks_tx => eth_clocks_tx,
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mii_eth_clocks_tx => eth_clocks_tx,
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mii_eth_clocks_rx => eth_clocks_rx,
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mii_eth_clocks_rx => eth_clocks_rx,
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mii_eth_rst_n => eth_rst_n,
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mii_eth_rst_n => eth_rst_n,
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@ -615,7 +615,7 @@ begin
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litesdcard : litesdcard_core
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litesdcard : litesdcard_core
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port map (
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port map (
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clk => system_clk,
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clk => system_clk,
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rst => soc_rst,
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rst => periph_rst,
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wb_ctrl_adr => wb_sdcard_adr,
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wb_ctrl_adr => wb_sdcard_adr,
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wb_ctrl_dat_w => wb_ext_io_in.dat,
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wb_ctrl_dat_w => wb_ext_io_in.dat,
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wb_ctrl_dat_r => wb_sdcard_out.dat,
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wb_ctrl_dat_r => wb_sdcard_out.dat,
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