Commit Graph

642 Commits (1fedc7a86adedc145c8fab6f8984e38607db8e4a)
 

Author SHA1 Message Date
Paul Mackerras 1fedc7a86a
Merge pull request #207 from ozbenh/misc
Random cleanups of the SoC interfaces
4 years ago
Benjamin Herrenschmidt 67b6117ebf soc: Slight cleanup of IRQ assignments
Use a separate process to assign selected interrupts to the
interrupt array, and document them.

There's only one interrupt *for now* but that will change
and this way is clearer.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt e07b3dd6fa soc: Rename uart_dat8 to uart0_dat8
Just for consistency. Will come in handy if we ever add a second one

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt f9f18906a3 soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
This makes the control bus currently going out of "soc" towards
litedram more generic for external IO devices added by the
top-level rather than inside the SoC proper.

This is mostly renaming of signals and a small change on how the
address decoder operates, using a separate "cascaded" decode for
the external IOs.

We make the region 0xc8nn_nnnn be the "external IO" region for
now.

This will make it easier / cleaner to add more external devices.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt bf7def5503 soc: Don't require dram wishbones signals to be wired by toplevel
Currently, when not using litedram, the top level still has to hook
up "dummy" wishbones to the main dram and control dram busses coming
out of the SoC and provide ack signals.

Instead, make the SoC generate the acks internally when not using
litedram and use defaults to make the wiring entirely optional.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 1ffc89e58b soc: Add defaults for some input signals
That way the top-level's don't need to assign them

Also remove generics that are set to the default anyways

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 4244b54984 soc: Remove unused RESET_LOW generic
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Paul Mackerras 12a257f01e
Merge pull request #205 from ozbenh/timing
Timing improvements
4 years ago
Paul Mackerras bf6cc2a05a
Merge pull request #204 from ozbenh/spi
Add an SPI master flash controller
4 years ago
Benjamin Herrenschmidt 176ae5c306 syscon: Remove combinational loop on ack and stall
Those hurt timings. Instead latch the wishbone response for one cycle

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 6c3a8bf417 bram: Remove combinational loop on stall
It hurts timing and is pointless

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt e5aa0e9dc9 uart: Remove combinational loops on ack and stall signal
They hurt timing forcing signals to come from the master and back
again in one cycle. Stall isn't sampled by the master unless there
is an active cycle so masking it with cyc is pointless. Masking acks
is somewhat pointless too as we don't handle early dropping of cyc
in any of our slaves properly anyways.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 6aadad5a75 spi: Add booting from flash to litedram init
It will look for an ELF binary at the flash offset specified
for the board (currently 0x300000 on Arty but that could be
changed).

Note: litedram is regenerated in order to rebuild the init code,
which was done using a newer version of litedram from LiteX.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt a89e1469ef spi: Add simulation support
This require the s25fl128s.vhd flash model and FMF libraries,
which will be built when passed to the Makefile via the
FLASH_MODEL_PATH argument. Otherwise a dummy module is used
which ties MISO to '1'.

The model isn't included as I'm not sure its licence (GPL) is
at this point, but it can be obtained from

https://github.com/ozbenh/microspi

FLASH_MODEL_PATH=<path to microspi>/model

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Dan Horák 801bd3b8ee
flash-arty: update error message (#203)
Signed-off-by: Dan Horák <dan@danny.cz>
4 years ago
Benjamin Herrenschmidt 9b458a9aa6
dmi: Add ASYNC_REG attribute on synchronizers (#200)
This tells Vivado to keep them close among other things

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt d266c9e67d
icache: Latch PLRU victim output (#199)
This stores the output of the PLRU big mux and clears the
tags and valid bits on the next cycle.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Paul Mackerras 41d28bbdfc
Merge pull request #198 from ozbenh/litedram
Litedram: Timing improvements
4 years ago
Benjamin Herrenschmidt cc4dcb3597 spi: Add SPI Flash controller
This adds an SPI flash controller which supports direct
memory-mapped access to the flash along with a manual
mode to send commands.

The direct mode can be set via generic to default to single
wire or quad mode. The controller supports normal, dual and quad
accesses with configurable commands, clock divider, dummy clocks
etc...

The SPI clock can be an even divider of sys_clk starting at 2
(so max 50Mhz with our typical Arty designs).

A flash offset is carried via generics to syscon to tell SW about
which portion of the flash is reserved for the FPGA bitfile. There
is currently no plumbing to make the CPU reset past that address (TBD).

Note: Operating at 50Mhz has proven unreliable without adding some
delay to the sampling of the input data. I'm working in improving
this, in the meantime, I'm leaving the default set at 25 Mhz.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 15467fe536 litedram: L2 use latched refill_index
Not a huge difference since wb_req is itself a latch but
may as well

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 05bbbf0772 litedram: Pipeline store acks in L2
There is a long timing path to generate the ack signal from
the L2 cache as it's fully combinational for stores, including
signals coming from litedram.

Instead, pipeline the store acks. This will introduce a cycle
latency but should improve timing. Also the core will eventually
be smart enough not to wait for store acks to complete them anyway.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 5ae5f76558 arty/nexys-video: Update XDC
The DRAM related pins have some small changes in LiteX, so resync
and add the false path information as well.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt b58ff724f6 litedram: Add stash buffer to the L2 cache wishbone interface
This breaks the long stall signal coming back to the processor
and helps improve overall timing.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt b23fd6c5f1 litedram: Defer clearing of tags & valids to improve timing
Currently, there's a huge mux gathering the output of all the PLRUs
to select the victim way on cache miss. This is fed combinationally
into the clearing of the valid and tags.

In order to help timing, let's store it instead and perform the
clearing on the next cycle. The L2 doesn't respond to requests
when not in IDLE state so this should have no negative effects.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 7192ee825f litedram: Improve dram_tb error output
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Anton Blanchard 7577cb18fb
Merge pull request #201 from mikey/github-actions
Move from travis to github workflows
4 years ago
Michael Neuling 9653b2952f Move from travis to github workflow
Github workflow gives us longer run times and faster startup.

Major kudos for this goes to @eine for the initial version and for
pushing us in this direction.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Paul Mackerras 6bb3837b33
Merge pull request #194 from ozbenh/misc
Fix syscon registers usage and add "save" function to mw_debug
4 years ago
Benjamin Herrenschmidt 183d05de86 gitignore: Add more exlusions
litedram build directory used by the generator and the
verilator obj_dir can be taken out

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 63f10450a6 litedram: Fix DRAM init mem using too many address bits
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt a93d9e77c9 litedram: Remove remnants of riscv-inits
We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 3c99e6c31f mw_debug: Add "save" function to save memory to a file
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 3167515069 sw: Properly mask syscon register fields
Some fields might get extended with extra bits, use the appropriate
masks when reading the values.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Michael Neuling 13da4caafb
Merge pull request #196 from ozbenh/makefile-lib-fix
Makefile: Improve unisim library generation
4 years ago
Michael Neuling 0739b55bc2
Merge pull request #195 from shenki/nexys-video
Nexys video
4 years ago
Benjamin Herrenschmidt 097d19fd32 Makefile: Improve unisim library generation
The rewrite of the Makefile to use "ghdl -c" somewhat broke building
the unisim library as ghdl doesn't yet support putting files in
separate libraries from a single command line invocation.

The workaround at the time was to put the entire project in "unisim"
which is ... weird and will break if we try to add another library
such as fmf.

This fixes it by generating the library separately using "ghdl -i"

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Joel Stanley fcdc01aa05 flash-arty: Re-add support for running from any path
The changes in d3c274d01e ("flash-arty: Add support for specifying the file type")
added a local jtagspi.cfg, which meant openocd must be run from the root
of the microwatt directory.

This puts the content into the xilinx-xc7.cfg so the script can be used
from any path again.

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years ago
Joel Stanley 002858ddde flash-arty: Support Nexys Video's a200
Not an Arty but Anton tests on this board.

Signed-off-by: Joel Stanley <joel@jms.id.au>
4 years ago
Michael Neuling e46c46ab5f
Merge pull request #193 from paulusmack/master
Minor improvements and reformatting
4 years ago
Paul Mackerras cff40237c7
Merge pull request #182 from mikey/travis
Travis and testing improvements
4 years ago
Benjamin Herrenschmidt b863791e38
icache: Fix icbi potentially clobbering the icache (#192)
icbi currently just resets the icache. This has some nasty side
effects such as also clearing the TLB, but also the wishbone interface.

That means that any ongoing cycle will be dropped.

However, most of our slaves don't handle that well and will continue
sending acks for already issued requests.

Under some circumstances we can thus restart an icache load and get
spurious ack/data from the wishbone left over from the "cancelled"
sequence.

This has broken booting Linux for me.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Paul Mackerras afa82bea9c decode2: Reformat to 4-space indentation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras d5c8c33bae decode1: Reformat to 4-space indentation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Paul Mackerras af909840e6 decode1: Make ld/std and lwa not be single-issue
These were missed earlier when the single-issue flag was turned off on
the other loads and stores by commit 1a244d3470 ("Remove single-issue
constraint for most loads and stores").

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Michael Neuling a740c4b7af Improve Travis to run as a matrix job
Can now run all 999 random tests and unit tests in Travis.

Kudos for this goes to @eine. Based on his input from here:
  https://github.com/antonblanchard/microwatt/pull/182#issuecomment-637926957

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 6323f27423 Add unit tests to check and check_light
Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 809933a567 Add unit tests make target
We don't run these but we should.

The SOC tests have bit rotted. We need to fix them but leave them out
for now.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Michael Neuling 560a6f6b18 Add tests_console make target
Will use when splitting out Travis tests later

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Paul Mackerras 983f4fefe1
Merge pull request #191 from ozbenh/litedram
Litedram updates with L2 cache and sim support
4 years ago
Benjamin Herrenschmidt b0e15f2fb5 litedram: Make the L2 twice as tall
This increases the number of L2 lines from 32 to 64. The BRAM usage is the
same as they were only half used. There's an increase in LUTs and registers
due to the extra tags and valid bits, but none of it should be in a
space constrained or critical timing path.

We could make it wider instead (256 bytes lines) which would reduce usage
instead, but this increases the latency by 8 cycles. Something to consider
once the L2 is capable of early response on miss and starting reloads
from any point in a line.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago