4 Commits (6cdb8ca9f515b5b1e4d9617d8d98548d77d04546)

Author	SHA1	Message	Date
Anton Blanchard	6cdb8ca9f5	Fix clk_gen_bypass ... clk_gen_bypass needed updating after the addition of CLK_INPUT_HZ and CLK_OUTPUT_HZ. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	d89a9929fd	Fix clk_gen_bypass ... I broke clk_gen_bypass when updating the SOC reset code. Fixes 03fd06deaf ("Rework SOC reset") Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago
Anton Blanchard	03fd06deaf	Rework SOC reset ... The old reset code was overly complicated and never worked properly. Replace it with a simpler sequence that uses a couple of shift registers to assert resets: - Wait a number of external clock cycles before removing reset from the PLL. - After the PLL locks and the external reset button isn't pressed, wait a number of PLL clock cycles before removing reset from the SOC. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago
Olof Kindgren	b5bccc4c13	Add dummy clock generator	6 years ago