A number of people have tripped up on GHDL backend issues. We
require either the LLVM or gcc backend, because the mcode backend
can't link against libraries which we use for simulated memory
and UART. Make that clearer, and point people at the Docker images
if they are having issues building ghdl.
Also point at the prebuilt micropython image.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Some distros don't have a version of ghdl with the LLVM or GCC backend,
so add a Docker image as an alternative.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
A first pass at ghdl synthesis using yosys and nextpnr. It runs hello world
or micropython if the FPGA has enough block RAM (eg ECP5 85F). The hello
world testcase also loops UART rx to tx in software (ie not a hardware
loopback).
It uses Docker images, so no software needs to be installed. If you prefer
podman you can use that too. Edit Makefile.synth to configure your FPGA,
JTAG device etc.
To build:
make -f Makefile.synth
and to program:
make -f Makefile.synth prog
A few issues:
We need to add PLL support. Right now Microwatt runs at whatever the
external clock frequency is and the baud rate gets scaled by how far off
50MHz it is. This means on the ecp5-evn with a 12 MHz clock rate the baud
rate is a quite strange 27650 (115200 * 50 / 12). On my OrangeCrab with a
50MHz clock the UART is 115200.
It uses a large amount of resources, way more than it should. There are
still some ghdl/yosys issues to be sorted out.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
GHDL doesn't seem to have a way to specify the location of the object
file it writes, so right now they are all ending up in the root
directory. The Makefile rules did not reflect that, so make would
continually the files in fpga/*
Fix the rules to match what GHDL is doing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
dependencies.py was pretty terrible at actually determining
dependencies. This improves it and also adds a --synth option.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Micropython has been able to fit into 384kB for ages, so lets reduce our
simulated RAM. This is useful for testing if micropython will run on an
ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
We might want a non power of 2 amount of RAM in order to fit into an
FPGA, so create log2ceil and use it when calculating the number of
memory bits.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
The current version of micropython in tests/micropython.bin is ancient.
Bug #135 points out that more recent versions are much smaller and they
also handle restart when ctrl+D is pressed.
Save all three versions of the file (elf, bin and hex) in micropython/
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Shrink hello_world a bit (from 12kB to 8kB).
Include the built images
Add 0x10 and 0x100 entry points
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
It should never happen in practise, but ghdlsynth is complaining about
an inferred latch here. Fix it
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
From the architecture:
bits 0:31 and 35:43 are treated as reserved and return 0s when read
using mfxer
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Right now our test cases fold the SPRs into the GPRs. That makes
debugging fails more difficult than it needs to be, so print
out the CTR, LR and CR.
We still need to print the XER, but that is in two spots in microwatt
and will take some more work.
This also adds many instructions to the tests that we have added
lately including overflow instructions, CR logicals and mt/mfxer.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
I'm hitting an issue with the Fedora 31 version of GHDL that
appears to be fixed upstream:
control.vhdl:105:39:error: actual expression must be globally static
Add a signal to get rid of error.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This stores the most common SPRs in the register file.
This includes CTR and LR and a not yet final list of others.
The register file is set to 64 entries for now. Specific types
are defined that can represent a GPR index (gpr_index_t) or
a GPR/SPR index (gspr_index_t) along with conversion functions
between the two.
On order to deal with some forms of branch updating both LR and
CTR, we introduced a delayed update of LR after a branch link.
Note: We currently stall the pipeline on such a delayed branch,
but we could avoid stalling fetch in that specific case as we
know we have a branch delay. We could also limit that to the
specific case where we need to update both CTR and LR.
This allows us to make bcreg, mtspr and mfspr pipelined. decode1
will automatically force the single issue flag on mfspr/mtspr to
a "slow" SPR.
[paulus@ozlabs.org - fix direction of decode2.stall_in]
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
We will want to store some SPRs in the register file using
a set of "extra" registers. This provides a function for
doing the translation along with some SPR definitions.
This isn't used yet
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
We were copying in XER[SO] for the dot-form instructions but not the
explicit compare instructions. Fix this.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard
Paul Mackerras