A tiny Open POWER ISA softcore written in VHDL 2008

openpowerppc64leprocessorvhdl

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Branch: master

alt-reset-address

asic-3

boxarty-20211011

branch-alias

cache-tlb-parameters-2

caravel-20210105

caravel-20210114

caravel-mpw5-20220322

caravel-mpw5-20220323

caravel-mpw6-20220530

caravel-mpw7-20220822

caravel-mpw7-20221125

core_debug-init

dcache-nc-fix

dcache-unused-sig

divider-init

fix-sdcard

fpu-constant

fpu-init

fpu-typo

gitignore

icache-insn-u-state

icache-pmu-events

icache-unused-sig

icbi-issue

jtag-port

jtag-port-2

less-fpga-init

litedram-update

liteeth-update

loadstore-init

loadstore-pmu-init

log2ceil-issue

master

nia-debug

orange-crab-freq

remove-potato-uart

trace-test

unused-sig

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microwatt/litedram

History

Matt Johnston 89d8cf0788 Regenerate litedram with updated sdram init ... Using litedram c770dd62edc281c370f9e2c694fe4ac1525a0b4a litex e570b612b2a9d8f8d2002d79497bda0dc35b936a Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>		5 months ago
..
extras	Move alt_reset to syscon	5 months ago
gen-src	litedram: only run sdram init at first boot	5 months ago
generated	Regenerate litedram with updated sdram init	5 months ago
litedram.core	litedram: Add basic support for LiteX LiteDRAM	3 years ago