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37 lines
1.1 KiB
Python
37 lines
1.1 KiB
Python
#!/usr/bin/python3
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from fusesoc.capi2.generator import Generator
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import os
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import sys
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import pathlib
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class LiteDRAMGenerator(Generator):
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def run(self):
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board = self.config.get('board')
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payload = self.config.get('payload')
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# Collect a bunch of directory path
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script_dir = os.path.dirname(sys.argv[0])
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base_dir = os.path.join(script_dir, os.pardir)
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gen_dir = os.path.join(base_dir, "generated", board)
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extras_dir = os.path.join(base_dir, "extras")
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print("Adding LiteDRAM for board... ", board)
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# Add files to fusesoc
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files = []
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f = os.path.join(gen_dir, "litedram_core.v")
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files.append({f : {'file_type' : 'verilogSource'}})
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f = os.path.join(gen_dir, "litedram-initmem.vhdl")
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files.append({f : {'file_type' : 'vhdlSource-2008'}})
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f = os.path.join(gen_dir, "litedram_core.init")
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files.append({f : {'file_type' : 'user'}})
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f = os.path.join(extras_dir, "litedram-wrapper-l2.vhdl")
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files.append({f : {'file_type' : 'vhdlSource-2008'}})
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self.add_files(files)
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g = LiteDRAMGenerator()
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g.run()
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g.write()
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