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Paul Mackerras
c1f23e7417
This regenerates the verilog code from upstream litex plus a patch to generate outputs from the litesdcard module for controlling bidirectional buffers between the FPGA and SD card. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
8 months ago | |
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.. | ||
litesdcard_core.v | 8 months ago |