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6cbf456388
The memory wishbone doesn't clear ACK and move the state machine on until STB is de-asserted. This seems like it isn't compliant with the spec and results in a maximum throughput of 1 transfer every 3 cycles. Fixing this improves the situation to one transfer every 2 cycles. Signed-off-by: Anton Blanchard <anton@linux.ibm.com> |
5 years ago | |
|---|---|---|
| .. | ||
| LICENSE | ||
| arty_a7-35.xdc | 5 years ago | |
| clk_gen_bypass.vhd | 5 years ago | |
| clk_gen_mcmm.vhd | 5 years ago | |
| clk_gen_plle2.vhd | 5 years ago | |
| cmod_a7-35.xdc | 5 years ago | |
| firmware.hex | ||
| hello_world.hex | ||
| mw_soc_memory.vhdl | 5 years ago | |
| nexys-video.xdc | ||
| nexys_a7.xdc | 5 years ago | |
| nodivide.patch | ||
| pp_fifo.vhd | ||
| pp_soc_uart.vhd | ||
| pp_utilities.vhd | ||
| soc_reset.vhdl | ||
| soc_reset_tb.vhdl | ||
| toplevel.vhdl | 5 years ago | |