Paul Mackerras
2f45e545ed
At present the busy/stall signal going to decode1 depends on whether control thinks it can issue the current instruction, and that depends on completion and bypass signals coming from execute1 and writeback. To improve the timing of stall_out, this rearranges decode2 so that stall_out is asserted when we have a valid instruction that couldn't be issued in the previous cycle. This means that decode1 could give us a new instruction when we haven't issued the previous instruction. This in turn means that we can only use d_in in the first cycle of processing an instruction. After the first cycle, we get register addresses etc. from dc2 rather than d_in. Then, to avoid the need to read register operands from register_file in each cycle until the instruction issues, we bring the bypass path for data being written to the register file into decode2 explicitly rather than having it in register_file. A new process called decode2_addrs does the process of calling decode_input_reg_* and decode_output_reg and sets up the register file addresses. This was split out (and decode_input_reg_* reworked) to try to reduce the number of passes through the decode2_1 process that need to be done in simulation. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
2 years ago | |
|---|---|---|
| .github/workflows | 3 years ago | |
| constraints | 3 years ago | |
| fpga | 3 years ago | |
| hello_world | 3 years ago | |
| include | ||
| lib | ||
| litedram | 3 years ago | |
| liteeth | 3 years ago | |
| litesdcard | 3 years ago | |
| media | ||
| micropython | ||
| openocd | 3 years ago | |
| rust_lib_demo | ||
| scripts | 2 years ago | |
| sim-unisim | ||
| tests | 2 years ago | |
| uart16550 | ||
| verilator | ||
| .gitignore | 3 years ago | |
| LICENSE | ||
| Makefile | 3 years ago | |
| README.md | 3 years ago | |
| cache_ram.vhdl | ||
| common.vhdl | 2 years ago | |
| control.vhdl | 2 years ago | |
| core.vhdl | 2 years ago | |
| core_debug.vhdl | 3 years ago | |
| core_dram_tb.vhdl | 3 years ago | |
| core_flash_tb.vhdl | ||
| core_tb.vhdl | ||
| countbits.vhdl | 2 years ago | |
| countbits_tb.vhdl | 2 years ago | |
| cr_file.vhdl | 2 years ago | |
| crhelpers.vhdl | ||
| dcache.vhdl | 2 years ago | |
| dcache_tb.vhdl | ||
| decode1.vhdl | 2 years ago | |
| decode2.vhdl | 2 years ago | |
| decode_types.vhdl | 2 years ago | |
| divider.vhdl | 2 years ago | |
| divider_tb.vhdl | ||
| dmi_dtm_dummy.vhdl | ||
| dmi_dtm_ecp5.vhdl | 3 years ago | |
| dmi_dtm_tb.vhdl | ||
| dmi_dtm_xilinx.vhdl | ||
| dram_tb.vhdl | 3 years ago | |
| execute1.vhdl | 2 years ago | |
| fetch1.vhdl | 3 years ago | |
| foreign_random.vhdl | ||
| fpu.vhdl | 2 years ago | |
| glibc_random.vhdl | ||
| glibc_random_helpers.vhdl | ||
| gpio.vhdl | 3 years ago | |
| helpers.vhdl | 3 years ago | |
| icache.vhdl | 2 years ago | |
| icache_tb.vhdl | 3 years ago | |
| icache_test.bin | ||
| insn_helpers.vhdl | ||
| loadstore1.vhdl | 2 years ago | |
| logical.vhdl | 3 years ago | |
| microwatt.core | 3 years ago | |
| mmu.vhdl | ||
| multiply.vhdl | 3 years ago | |
| multiply_tb.vhdl | ||
| nonrandom.vhdl | ||
| plru.vhdl | ||
| plru_tb.vhdl | ||
| pmu.vhdl | ||
| ppc_fx_insns.vhdl | ||
| random.vhdl | ||
| register_file.vhdl | 2 years ago | |
| rotator.vhdl | ||
| rotator_tb.vhdl | ||
| run.py | ||
| sim_16550_uart.vhdl | ||
| sim_bram.vhdl | ||
| sim_bram_helpers.vhdl | ||
| sim_bram_helpers_c.c | ||
| sim_console.vhdl | ||
| sim_console_c.c | ||
| sim_jtag.vhdl | ||
| sim_jtag_socket.vhdl | ||
| sim_jtag_socket_c.c | ||
| sim_no_flash.vhdl | ||
| sim_pp_uart.vhdl | ||
| sim_vhpi_c.c | ||
| sim_vhpi_c.h | ||
| soc.vhdl | 3 years ago | |
| spi_flash_ctrl.vhdl | 3 years ago | |
| spi_rxtx.vhdl | 3 years ago | |
| sync_fifo.vhdl | ||
| syscon.vhdl | 3 years ago | |
| utils.vhdl | ||
| wishbone_arbiter.vhdl | ||
| wishbone_bram_tb.bin | ||
| wishbone_bram_tb.vhdl | 3 years ago | |
| wishbone_bram_wrapper.vhdl | 3 years ago | |
| wishbone_debug_master.vhdl | 3 years ago | |
| wishbone_types.vhdl | 3 years ago | |
| writeback.vhdl | 2 years ago | |
| xics.vhdl | 3 years ago | |
| xilinx-mult.vhdl | 3 years ago | |
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../
A prebuilt micropython image is also available in the micropython/ directory.
-
Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.
If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.
-
Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
To build using Docker:
make DOCKER=1
and to build using Podman:
make PODMAN=1
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
Or if you were using the pre-built image:
ln -s micropython/firmware.bin main_ram.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
Fedora users can get FuseSoC package via
sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
- If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
fusesoc fetch uart16550
fusesoc library add microwatt /path/to/microwatt
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Linux on Microwatt
Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested platform, but it's also been tested on the OrangeCrab and ButterStick.
-
Use buildroot to create a userspace
A small change is required to glibc in order to support the VMX/AltiVec-less Microwatt, as float128 support is mandiatory and for this in GCC requires VSX/AltiVec. This change is included in Joel's buildroot fork, along with a defconfig:
git clone -b microwatt https://github.com/shenki/buildroot cd buildroot make ppc64le_microwatt_defconfig makeThe output is
output/images/rootfs.cpio. -
Build the Linux kernel
git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git cd linux make ARCH=powerpc microwatt_defconfig make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \ CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`The output is
arch/powerpc/boot/dtbImage.microwatt.elf. -
Build gateware using FuseSoC
First configure FuseSoC as above.
fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0The output is
build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit. -
Program the flash
This operation will overwrite the contents of your flash.
For the Arty A7 A100, set
FLASH_ADDRESSto0x400000and pass-f a100.For the Arty A7 A35, set
FLASH_ADDRESSto0x300000and pass-f a35.microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS -
Connect to the second USB TTY device exposed by the FPGA
minicom -D /dev/ttyUSB1The gateware has firmware that will look at
FLASH_ADDRESSand attempt to parse an ELF there, loading it to the address specified in the ELF header and jumping to it.
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
- There are a few instructions still to be implemented:
- Vector/VMX/VSX