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A tiny Open POWER ISA softcore written in VHDL 2008
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Paul Mackerras 8da05e5331 FPU: Make an explicit exponent data path 
With this, the large case statement sets values for a set of control
signals, which then control multiplexers and adders that generate
values for v.result_exp and v.shift.  The plan is for the case
statement to turn into a microcode ROM eventually.

The value of v.result_exp is the sum of two values, either of which
can be negated (but not both).  The first value can be chosen from the
result exponent, A exponent, B exponent arithmetically shifted right
one bit, or 0.  The second value can be chosen from new_exp (which is
r.result_exp - r.shift), B exponent, C exponent or a constant.  The
choices for the constant are 0, 56, the maximum exponent (max_exp) or
the exponent bias for trap-enabled overflow conditions (bias_exp).
These choices are controlled by the signals re_sel1, re_neg1, re_sel2
and re_neg2, and the sum is written into v.result_exp if re_set_result
is 1.

For v.shift we also compute the sum of two values, either of which
can be negated (but not both).  The first value can be chosen from
new_exp, B exponent, r.shift, or 0.  The second value can be chosen
from the A exponent or a constant.  The possible constants are 0, 1,
4, 8, 32, 52, 56, 63, 64, or the minimum exponent (min_exp).  These
choices are controlled by the signals rs_sel1, rs_neg1, rs_sel2 and
rs_neg2.  After the adder there is a multiplexer which selects either
the sum or a shift count for normalization (derived from a count
leading zeroes operation on R) to be written into v.shift.  The
count-leading-zeroes result does not go through the adder for timing
reasons.

In order to simplify the logic and help improve timing, settings of
the control signals have been made unconditional in a state in many
places, even if those settings are only required when some condition
is met.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 		2 years ago
.github/workflows ci: Add new Orange Crab build 3 years ago
constraints orangecrab: add Orange Crab r0.2 target 3 years ago
fpga Extend LiteDRAM VHDL wrapper to allow more than one clock line 3 years ago
hello_world Zero BSS in hello world test 2 years ago
include arty_a7: Add litesdcard interface 4 years ago
lib console: Add support for the 16550 UART 4 years ago
litedram litedram: Regenerate 2 years ago
liteeth Regenerate litedram and liteeth 3 years ago
litesdcard litesdcard: Fix and regenerate Verilog 2 years ago
media Add title image 5 years ago
micropython tests: Add updated micropython build with 16550 support 4 years ago
openocd flash-arty: Add cable argument 3 years ago
rust_lib_demo console: Cleanup console API 4 years ago
scripts test: Add test for metavalues 2 years ago
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 5 years ago
tests test: Add test for metavalues 2 years ago
uart16550 Add uart16550 files from fusesoc 4 years ago
verilator verilator: Specify top level module 3 years ago
.gitignore Add litesdcard/build to gitignore 2 years ago
LICENSE Initial import of microwatt 5 years ago
Makefile dmi_dtm_ecp5: Use ECP5 JTAGG for DMI 3 years ago
README.md README: Add Linux on Microwatt instructions 2 years ago
cache_ram.vhdl Reformat cache_ram 4 years ago
common.vhdl loadstore1: Simplify address generation in OP_FETCH_FAILED case 2 years ago
control.vhdl Track hazards explicitly for XER overflow bits 2 years ago
core.vhdl decode1: Work out register addresses in decode1 2 years ago
core_debug.vhdl Metavalue cleanup for common.vhdl 2 years ago
core_dram_tb.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 3 years ago
core_flash_tb.vhdl Reformat testbenches 4 years ago
core_tb.vhdl Reformat testbenches 4 years ago
countbits.vhdl Allow integer instructions and load/store instructions to execute together 2 years ago
countbits_tb.vhdl Add a second execute stage to the pipeline 2 years ago
cr_file.vhdl execute1: Restructure to separate out execution of side effects 2 years ago
crhelpers.vhdl crhelpers: Constraint "crnum" integer 5 years ago
dcache.vhdl Remove leftover logic for 16-byte loads and stores 2 years ago
dcache_tb.vhdl Reformat testbenches 4 years ago
decode1.vhdl loadstore1: Simplify address generation in OP_FETCH_FAILED case 2 years ago
decode2.vhdl Metavalue cleanup for common.vhdl 2 years ago
decode_types.vhdl Finish off taking SPRs out of register file 2 years ago
divider.vhdl Add a second execute stage to the pipeline 2 years ago
divider_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl 5 years ago
dmi_dtm_ecp5.vhdl dmi_dtm_ecp5: Use ECP5 JTAGG for DMI 3 years ago
dmi_dtm_tb.vhdl Reformat testbenches 4 years ago
dmi_dtm_xilinx.vhdl Fix some whitespace issues 3 years ago
dram_tb.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 3 years ago
execute1.vhdl loadstore1: Simplify address generation in OP_FETCH_FAILED case 2 years ago
fetch1.vhdl Metavalue cleanup for fetch1.vhdl 2 years ago
foreign_random.vhdl Make core testbenches recognized by VUnit 3 years ago
fpu.vhdl FPU: Make an explicit exponent data path 2 years ago
glibc_random.vhdl Reformat glibc_random 5 years ago
glibc_random_helpers.vhdl Reformat glibc_random 5 years ago
gpio.vhdl Remove some FPGA style signal inits 2 years ago
helpers.vhdl Metavalue cleanup for helpers.vhdl 2 years ago
icache.vhdl Metavalue cleanup for icache.vhdl 2 years ago
icache_tb.vhdl fix: fix icache_tb not finishing correctly 3 years ago
icache_test.bin icache_tb: Improve test and include test file 5 years ago
insn_helpers.vhdl core: Implement quadword loads and stores 4 years ago
loadstore1.vhdl loadstore1: Simplify address generation in OP_FETCH_FAILED case 2 years ago
logical.vhdl Finish off taking SPRs out of register file 2 years ago
microwatt.core core: Make popcnt* take two cycles 3 years ago
mmu.vhdl Metavalue cleanup for mmu.vhdl 2 years ago
multiply.vhdl core: Add a short multiplier 3 years ago
multiply_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
nonrandom.vhdl Add random number generator and implement the darn instruction 4 years ago
plru.vhdl Reformat plru 4 years ago
plru_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
pmu.vhdl Metavalue cleanup for pmu.vhdl 2 years ago
ppc_fx_insns.vhdl Fix some whitespace issues 3 years ago
random.vhdl Make core testbenches recognized by VUnit 3 years ago
register_file.vhdl Metavalue cleanup for register_file.vhdl 2 years ago
rotator.vhdl Metavalue cleanup for rotator.vhdl 2 years ago
rotator_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 3 years ago
run.py VUnit: style 3 years ago
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART 4 years ago
sim_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 3 years ago
sim_bram_helpers.vhdl ram: Rework main RAM interface 5 years ago
sim_bram_helpers_c.c Consolidate VHPI code 5 years ago
sim_console.vhdl Reformat sim_console 5 years ago
sim_console_c.c sim_console: Fix polling to check for POLLIN 4 years ago
sim_jtag.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket.vhdl Add jtag support in simulation via a socket 5 years ago
sim_jtag_socket_c.c Consolidate VHPI code 5 years ago
sim_no_flash.vhdl spi: Add simulation support 4 years ago
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 4 years ago
sim_vhpi_c.c Consolidate VHPI code 5 years ago
sim_vhpi_c.h Consolidate VHPI code 5 years ago
soc.vhdl soc: Fix -Whide warning 2 years ago
spi_flash_ctrl.vhdl Remove some FPGA style signal inits 2 years ago
spi_rxtx.vhdl Remove some FPGA style signal inits 2 years ago
sync_fifo.vhdl litedram: Add an L2 cache with store queue 5 years ago
syscon.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
utils.vhdl litedram: Add support for booting without BRAM 5 years ago
wishbone_arbiter.vhdl wb_arbiter: Early master selection 5 years ago
wishbone_bram_tb.bin ram: Rework main RAM interface 5 years ago
wishbone_bram_tb.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
wishbone_bram_wrapper.vhdl wishbone_bram_wrapper ram_addr_bits is 1 bit off 3 years ago
wishbone_debug_master.vhdl Make wishbone addresses be in units of doublewords or words 3 years ago
wishbone_types.vhdl Introduce addr_to_wb() and wb_to_addr() helpers 3 years ago
writeback.vhdl writeback: Eliminate unintentional inferred latch 2 years ago
xics.vhdl xics: Fix -Whide warnings 2 years ago
xilinx-mult.vhdl core: Add a short multiplier 3 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
fusesoc fetch uart16550
fusesoc library add microwatt /path/to/microwatt
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Linux on Microwatt

Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested platform, but it's also been tested on the OrangeCrab and ButterStick.

  1. Use buildroot to create a userspace

    A small change is required to glibc in order to support the VMX/AltiVec-less Microwatt, as float128 support is mandiatory and for this in GCC requires VSX/AltiVec. This change is included in Joel's buildroot fork, along with a defconfig:

    git clone -b microwatt https://github.com/shenki/buildroot
cd buildroot
make ppc64le_microwatt_defconfig
make

    The output is output/images/rootfs.cpio.

  2. Build the Linux kernel

    git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
cd linux
make ARCH=powerpc microwatt_defconfig
make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \
  CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`

    The output is arch/powerpc/boot/dtbImage.microwatt.elf.

  3. Build gateware using FuseSoC

    First configure FuseSoC as above.

    fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0

    The output is build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit.

  4. Program the flash

    This operation will overwrite the contents of your flash.

    For the Arty A7 A100, set FLASH_ADDRESS to 0x400000 and pass -f a100.

    For the Arty A7 A35, set FLASH_ADDRESS to 0x300000 and pass -f a35.

    microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit
microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS

  5. Connect to the second USB TTY device exposed by the FPGA

    minicom -D /dev/ttyUSB1

    The gateware has firmware that will look at FLASH_ADDRESS and attempt to parse an ELF there, loading it to the address specified in the ELF header and jumping to it.

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

  • There are a few instructions still to be implemented:
    • Vector/VMX/VSX