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Organized VUnit testbenches into test cases.

Browse Source 
Several of the testbenches have stimuli code divided into sections preceded with a header comment explaining
what is being tested. These sections have been made into VUnit test cases. The default behavior of VUnit is
to run each test case in a separate simulation which comes with a number of benefits:

* A failing test case doesn't prevent other test cases to be executed
* Test cases are independent. A test case cannot fail as a side-effect to a problem with another test case
* Test execution can be more parallelized and the overall test execution time reduced

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
remove-potato-uart
Lars Asplund 4 years ago
parent 08c0c4c1b4
commit 0940b8a9d3
4 changed files with 880 additions and 913 deletions
Show Stats Download Patch File Download Diff File

10
countzero_tb.vhdl
Unescape Escape View File

@ -49,8 +49,8 @@ begin


test_runner_setup(runner, runner_cfg); test_runner_setup(runner, runner_cfg);


-- test with input = 0 while test_suite loop
report "test zero input"; if run("Test with input = 0") then
rs <= (others => '0'); rs <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
count_right <= '0'; count_right <= '0';
@ -71,7 +71,7 @@ begin
assert result = x"0000000000000020" assert result = x"0000000000000020"
report "bad cnttzw 0 = " & to_hstring(result); report "bad cnttzw 0 = " & to_hstring(result);


report "test cntlzd/w"; elsif run("Test cntlzd/w") then
count_right <= '0'; count_right <= '0';
for j in 0 to 100 loop for j in 0 to 100 loop
r := rnd.RandSlv(64); r := rnd.RandSlv(64);
@ -96,7 +96,7 @@ begin
end loop; end loop;
end loop; end loop;


report "test cnttzd/w"; elsif run("Test cnttzd/w") then
count_right <= '1'; count_right <= '1';
for j in 0 to 100 loop for j in 0 to 100 loop
r := rnd.RandSlv(64); r := rnd.RandSlv(64);
@ -119,6 +119,8 @@ begin
r := r(62 downto 0) & '0'; r := r(62 downto 0) & '0';
end loop; end loop;
end loop; end loop;
end if;
end loop;


test_runner_cleanup(runner); test_runner_cleanup(runner);
end process; end process;

74
divider_tb.vhdl
Unescape Escape View File

@ -49,18 +49,22 @@ begin


test_runner_setup(runner, runner_cfg); test_runner_setup(runner, runner_cfg);


while test_suite loop
rst <= '1'; rst <= '1';
wait for clk_period; wait for clk_period;
rst <= '0'; rst <= '0';


d1.valid <= '1';
d1.dividend <= x"0000000010001000";
d1.divisor <= x"0000000000001111";
d1.is_signed <= '0'; d1.is_signed <= '0';
d1.is_32bit <= '0'; d1.neg_result <= '0';
d1.is_extended <= '0'; d1.is_extended <= '0';
d1.is_32bit <= '0';
d1.is_modulus <= '0'; d1.is_modulus <= '0';
d1.neg_result <= '0'; d1.valid <= '0';

if run("Test interface") then
d1.valid <= '1';
d1.dividend <= x"0000000010001000";
d1.divisor <= x"0000000000001111";


wait for clk_period; wait for clk_period;
assert d2.valid = '0'; assert d2.valid = '0';
@ -100,8 +104,7 @@ begin
wait for clk_period; wait for clk_period;
assert d2.valid = '0'; assert d2.valid = '0';


-- test divd elsif run("Test divd") then
report "test divd";
divd_loop : for dlength in 1 to 8 loop divd_loop : for dlength in 1 to 8 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -135,8 +138,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test divdu elsif run("Test divdu") then
report "test divdu";
divdu_loop : for dlength in 1 to 8 loop divdu_loop : for dlength in 1 to 8 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -145,8 +147,6 @@ begin


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
d1.is_signed <= '0';
d1.neg_result <= '0';
d1.valid <= '1'; d1.valid <= '1';


wait for clk_period; wait for clk_period;
@ -170,8 +170,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test divde elsif run("Test divde") then
report "test divde";
divde_loop : for vlength in 1 to 8 loop divde_loop : for vlength in 1 to 8 loop
for dlength in 1 to vlength loop for dlength in 1 to vlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -211,8 +210,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test divdeu elsif run("Test divdeu") then
report "test divdeu";
divdeu_loop : for vlength in 1 to 8 loop divdeu_loop : for vlength in 1 to 8 loop
for dlength in 1 to vlength loop for dlength in 1 to vlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -221,8 +219,6 @@ begin


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
d1.is_signed <= '0';
d1.neg_result <= '0';
d1.is_extended <= '1'; d1.is_extended <= '1';
d1.valid <= '1'; d1.valid <= '1';


@ -249,8 +245,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test divw elsif run("Test divw") then
report "test divw";
divw_loop : for dlength in 1 to 4 loop divw_loop : for dlength in 1 to 4 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -261,7 +256,6 @@ begin
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
d1.is_signed <= '1'; d1.is_signed <= '1';
d1.neg_result <= ra(63) xor rb(63); d1.neg_result <= ra(63) xor rb(63);
d1.is_extended <= '0';
d1.is_32bit <= '1'; d1.is_32bit <= '1';
d1.valid <= '1'; d1.valid <= '1';


@ -286,8 +280,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test divwu elsif run("Test divwu") then
report "test divwu";
divwu_loop : for dlength in 1 to 4 loop divwu_loop : for dlength in 1 to 4 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -296,9 +289,6 @@ begin


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
d1.is_signed <= '0';
d1.neg_result <= '0';
d1.is_extended <= '0';
d1.is_32bit <= '1'; d1.is_32bit <= '1';
d1.valid <= '1'; d1.valid <= '1';


@ -323,8 +313,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test divwe elsif run("Test divwe") then
report "test divwe";
divwe_loop : for vlength in 1 to 4 loop divwe_loop : for vlength in 1 to 4 loop
for dlength in 1 to vlength loop for dlength in 1 to vlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -335,7 +324,6 @@ begin
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
d1.is_signed <= '1'; d1.is_signed <= '1';
d1.neg_result <= ra(63) xor rb(63); d1.neg_result <= ra(63) xor rb(63);
d1.is_extended <= '0';
d1.is_32bit <= '1'; d1.is_32bit <= '1';
d1.valid <= '1'; d1.valid <= '1';


@ -364,8 +352,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test divweu elsif run("Test divweu") then
report "test divweu";
divweu_loop : for vlength in 1 to 4 loop divweu_loop : for vlength in 1 to 4 loop
for dlength in 1 to vlength loop for dlength in 1 to vlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -374,9 +361,6 @@ begin


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
d1.is_signed <= '0';
d1.neg_result <= '0';
d1.is_extended <= '0';
d1.is_32bit <= '1'; d1.is_32bit <= '1';
d1.valid <= '1'; d1.valid <= '1';


@ -401,8 +385,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test modsd elsif run("Test modsd") then
report "test modsd";
modsd_loop : for dlength in 1 to 8 loop modsd_loop : for dlength in 1 to 8 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -413,8 +396,6 @@ begin
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
d1.is_signed <= '1'; d1.is_signed <= '1';
d1.neg_result <= ra(63); d1.neg_result <= ra(63);
d1.is_extended <= '0';
d1.is_32bit <= '0';
d1.is_modulus <= '1'; d1.is_modulus <= '1';
d1.valid <= '1'; d1.valid <= '1';


@ -439,8 +420,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test modud elsif run("Test modud") then
report "test modud";
modud_loop : for dlength in 1 to 8 loop modud_loop : for dlength in 1 to 8 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -449,10 +429,6 @@ begin


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
d1.is_signed <= '0';
d1.neg_result <= '0';
d1.is_extended <= '0';
d1.is_32bit <= '0';
d1.is_modulus <= '1'; d1.is_modulus <= '1';
d1.valid <= '1'; d1.valid <= '1';


@ -477,8 +453,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test modsw elsif run("Test modsw") then
report "test modsw";
modsw_loop : for dlength in 1 to 4 loop modsw_loop : for dlength in 1 to 4 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -489,7 +464,6 @@ begin
d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb)); d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
d1.is_signed <= '1'; d1.is_signed <= '1';
d1.neg_result <= ra(63); d1.neg_result <= ra(63);
d1.is_extended <= '0';
d1.is_32bit <= '1'; d1.is_32bit <= '1';
d1.is_modulus <= '1'; d1.is_modulus <= '1';
d1.valid <= '1'; d1.valid <= '1';
@ -520,8 +494,7 @@ begin
end loop; end loop;
end loop; end loop;


-- test moduw elsif run("Test moduw") then
report "test moduw";
moduw_loop : for dlength in 1 to 4 loop moduw_loop : for dlength in 1 to 4 loop
for vlength in 1 to dlength loop for vlength in 1 to dlength loop
for i in 0 to 100 loop for i in 0 to 100 loop
@ -530,9 +503,6 @@ begin


d1.dividend <= ra; d1.dividend <= ra;
d1.divisor <= rb; d1.divisor <= rb;
d1.is_signed <= '0';
d1.neg_result <= '0';
d1.is_extended <= '0';
d1.is_32bit <= '1'; d1.is_32bit <= '1';
d1.is_modulus <= '1'; d1.is_modulus <= '1';
d1.valid <= '1'; d1.valid <= '1';
@ -557,6 +527,8 @@ begin
end loop; end loop;
end loop; end loop;
end loop; end loop;
end if;
end loop;


test_runner_cleanup(runner); test_runner_cleanup(runner);
end process; end process;

18
multiply_tb.vhdl
Unescape Escape View File

@ -58,6 +58,8 @@ begin


test_runner_setup(runner, runner_cfg); test_runner_setup(runner, runner_cfg);


while test_suite loop
if run("Test interface") then
wait for clk_period; wait for clk_period;


m1.valid <= '1'; m1.valid <= '1';
@ -93,7 +95,7 @@ begin
assert m2.valid = '1'; assert m2.valid = '1';
assert m2.result = x"00000000000000000000000001111000"; assert m2.result = x"00000000000000000000000001111000";


-- test mulld elsif run("Test mulld") then
mulld_loop : for i in 0 to 1000 loop mulld_loop : for i in 0 to 1000 loop
ra := rnd.RandSlv(ra'length); ra := rnd.RandSlv(ra'length);
rb := rnd.RandSlv(rb'length); rb := rnd.RandSlv(rb'length);
@ -119,7 +121,7 @@ begin
report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0)); report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0));
end loop; end loop;


-- test mulhdu elsif run("Test mulhdu") then
mulhdu_loop : for i in 0 to 1000 loop mulhdu_loop : for i in 0 to 1000 loop
ra := rnd.RandSlv(ra'length); ra := rnd.RandSlv(ra'length);
rb := rnd.RandSlv(rb'length); rb := rnd.RandSlv(rb'length);
@ -144,7 +146,7 @@ begin
report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(127 downto 64)); report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(127 downto 64));
end loop; end loop;


-- test mulhd elsif run("Test mulhd") then
mulhd_loop : for i in 0 to 1000 loop mulhd_loop : for i in 0 to 1000 loop
ra := rnd.RandSlv(ra'length); ra := rnd.RandSlv(ra'length);
rb := rnd.RandSlv(rb'length); rb := rnd.RandSlv(rb'length);
@ -170,7 +172,7 @@ begin
report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(127 downto 64)); report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(127 downto 64));
end loop; end loop;


-- test mullw elsif run("Test mullw") then
mullw_loop : for i in 0 to 1000 loop mullw_loop : for i in 0 to 1000 loop
ra := rnd.RandSlv(ra'length); ra := rnd.RandSlv(ra'length);
rb := rnd.RandSlv(rb'length); rb := rnd.RandSlv(rb'length);
@ -198,7 +200,7 @@ begin
report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0)); report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0));
end loop; end loop;


-- test mulhw elsif run("Test mulhw") then
mulhw_loop : for i in 0 to 1000 loop mulhw_loop : for i in 0 to 1000 loop
ra := rnd.RandSlv(ra'length); ra := rnd.RandSlv(ra'length);
rb := rnd.RandSlv(rb'length); rb := rnd.RandSlv(rb'length);
@ -227,7 +229,7 @@ begin
to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32)); to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32));
end loop; end loop;


-- test mulhwu elsif run("Test mulhwu") then
mulhwu_loop : for i in 0 to 1000 loop mulhwu_loop : for i in 0 to 1000 loop
ra := rnd.RandSlv(ra'length); ra := rnd.RandSlv(ra'length);
rb := rnd.RandSlv(rb'length); rb := rnd.RandSlv(rb'length);
@ -255,7 +257,7 @@ begin
to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32)); to_hstring(m2.result(63 downto 32) & m2.result(63 downto 32));
end loop; end loop;


-- test mulli elsif run("Test mulli") then
mulli_loop : for i in 0 to 1000 loop mulli_loop : for i in 0 to 1000 loop
ra := rnd.RandSlv(ra'length); ra := rnd.RandSlv(ra'length);
si := rnd.RandSlv(si'length); si := rnd.RandSlv(si'length);
@ -281,6 +283,8 @@ begin
assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 0)) assert to_hstring(behave_rt) = to_hstring(m2.result(63 downto 0))
report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0)); report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.result(63 downto 0));
end loop; end loop;
end if;
end loop;


test_runner_cleanup(runner); test_runner_cleanup(runner);
wait; wait;

43
rotator_tb.vhdl
Unescape Escape View File

@ -53,8 +53,8 @@ begin


test_runner_setup(runner, runner_cfg); test_runner_setup(runner, runner_cfg);


-- rlwinm, rlwnm while test_suite loop
report "test rlw[i]nm"; if run("Test rlw[i]nm") then
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '0'; right_shift <= '0';
@ -72,8 +72,7 @@ begin
report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rlwimi elsif run("Test rlwimi") then
report "test rlwimi";
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
@ -90,8 +89,7 @@ begin
report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rldicl, rldcl elsif run("Test rld[i]cl") then
report "test rld[i]cl";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
@ -108,8 +106,7 @@ begin
report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rldicr, rldcr elsif run("Test rld[i]cr") then
report "test rld[i]cr";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
@ -131,8 +128,7 @@ begin
report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rldic elsif run("Test rldic") then
report "test rldic";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
@ -149,8 +145,7 @@ begin
report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rldimi elsif run("Test rldimi") then
report "test rldimi";
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
@ -167,8 +162,7 @@ begin
report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- slw elsif run("Test slw") then
report "test slw";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '0'; right_shift <= '0';
@ -184,8 +178,7 @@ begin
report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- sld elsif run("Test sld") then
report "test sld";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
@ -201,8 +194,7 @@ begin
report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- srw elsif run("Test srw") then
report "test srw";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '1'; right_shift <= '1';
@ -218,8 +210,7 @@ begin
report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- srd elsif run("Test srd") then
report "test srd";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '1'; right_shift <= '1';
@ -235,8 +226,7 @@ begin
report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- sraw[i] elsif run("Test sraw[i]") then
report "test sraw[i]";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '1'; right_shift <= '1';
@ -256,8 +246,7 @@ begin
report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result); report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
end loop; end loop;


-- srad[i] elsif run("Test srad[i]") then
report "test srad[i]";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '1'; right_shift <= '1';
@ -277,8 +266,7 @@ begin
report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result); report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
end loop; end loop;


-- extswsli elsif run("Test extswsli") then
report "test extswsli";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
@ -301,7 +289,8 @@ begin
assert behave_ra = result assert behave_ra = result
report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;

end if;
end loop;
test_runner_cleanup(runner); test_runner_cleanup(runner);
end process; end process;
end behave; end behave;

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