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@ -1,6 +1,9 @@
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GHDL ?= ghdl
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GHDLFLAGS=--std=08 -frelaxed
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CFLAGS=-O3 -Wall
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VERILATOR_FLAGS=-O3
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# It takes forever to build with optimisation, so disable by default
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#VERILATOR_CFLAGS=-O3
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GHDLSYNTH ?= ghdl.so
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YOSYS ?= yosys
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@ -115,8 +118,6 @@ $(soc_dram_tbs):
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$(error "Verilator is required to make this target !")
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else
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VERILATOR_CFLAGS=-O3
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VERILATOR_FLAGS=-O3
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verilated_dram: litedram/generated/sim/litedram_core.v
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verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
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make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
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@ -198,7 +199,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
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# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
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microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
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verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
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verilator $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc $< --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
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make -C obj_dir -f Vmicrowatt.mk
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@cp -f obj_dir/microwatt-verilator microwatt-verilator
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