Merge pull request #48 from antonblanchard/clk_gen_bypass

Fix clk_gen_bypass
5 years ago · 67446709ca
parent 80aa781454 d89a9929fd
commit 67446709ca
1 changed files with 1 additions and 1 deletions
--- a/fpga/clk_gen_bypass.vhd
+++ b/fpga/clk_gen_bypass.vhd
@ -14,7 +14,7 @@ architecture bypass of clock_generator is
 begin
-  pll_locked_out <= pll_rst_in;
+  pll_locked_out <= not pll_rst_in;
  pll_clk_out <= ext_clk;
 end architecture bypass;