Merge pull request #51 from antonblanchard/writeback-fix

Some writeback updates

writeback.vhdl

@@ -40,9 +40,9 @@ begin
     end process;
 
     writeback_1: process(all)
-		variable x: std_ulogic_vector(0 downto 0);
-		variable y: std_ulogic_vector(0 downto 0);
-		variable z: std_ulogic_vector(0 downto 0);
+        variable x     : std_ulogic_vector(0 downto 0);
+        variable y     : std_ulogic_vector(0 downto 0);
+        variable z     : std_ulogic_vector(0 downto 0);
         variable v     : reg_type;
         variable v_int : reg_internal_type;
     begin
@@ -52,12 +52,12 @@ begin
         x := "" & e_in.valid;
         y := "" & l_in.valid;
         z := "" & m_in.valid;
-		assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1;
+        assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
 
         x := "" & e_in.write_enable;
         y := "" & l_in.write_enable;
         z := "" & m_in.write_reg_enable;
-		assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1;
+        assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
 
         assert not(e_in.write_cr_enable = '1' and m_in.write_cr_enable = '1');