litedram: Update yaml files

Update the litedram yaml files based on latest upstream.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

litedram/gen-src/acorn-cle-215.yml

@@ -3,13 +3,11 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -2,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
     # PHY ----------------------------------------------------------------------
-    "cmd_delay":       0,             # Command additional delay (in taps)
     "cmd_latency":     0,             # Command additional latency
     "sdram_module":    "MT41K512M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 2,             # Number of byte groups
@@ -35,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }

litedram/gen-src/arty.yml

@@ -3,13 +3,11 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
     # PHY ----------------------------------------------------------------------
-    "cmd_delay":       0,             # Command additional delay (in taps)
     "cmd_latency":     0,             # Command additional latency
     "sdram_module":    "MT41K128M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 2,             # Number of byte groups
@@ -35,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }

litedram/gen-src/genesys2.yml

@@ -3,8 +3,7 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -2,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
@@ -13,7 +12,7 @@
     "sdram_module":    "MT41J256M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 4,             # Number of byte groups
     "sdram_rank_nb":   1,             # Number of ranks
-    "sdram_phy":       K7DDRPHY,      # Type of FPGA PHY
+    "sdram_phy":       "K7DDRPHY",    # Type of FPGA PHY
 
     # Electrical ---------------------------------------------------------------
     "rtt_nom": "60ohm",  # Nominal termination
@@ -34,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }

litedram/gen-src/nexys-video.yml

@@ -3,13 +3,11 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
 
     # PHY ----------------------------------------------------------------------
-    "cmd_delay":       0,             # Command additional delay (in taps)
     "cmd_latency":     0,             # Command additional latency
     "sdram_module":    "MT41K256M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 2,             # Number of byte groups
@@ -35,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }

litedram/gen-src/sim.yml

@@ -3,14 +3,11 @@
 
 {
     # General ------------------------------------------------------------------
-    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
-    "cpu_variant":"standard",
+    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
     "speedgrade": -1,          # FPGA speedgrade
     "memtype":    "DDR3",      # DRAM type
-    "sim" : "True",
 
     # PHY ----------------------------------------------------------------------
-    "cmd_delay":       0,             # Command additional delay (in taps)
     "cmd_latency":     0,             # Command additional latency
     "sdram_module":    "MT41K128M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 2,             # Number of byte groups
@@ -36,8 +33,4 @@
             "type": "native",
         },
     },
-
-    # CSR Port -----------------------------------------------------------------
-    "csr_alignment"  : 32,
-    "csr_data_width" : 32,
 }