ASIC: Reduce multiplier from 4 to 2 cycles

Our sky130 gate level multiply/adder now makes timing with a single
register stage.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

asic/behavioural/multiply_add_64x64.v

@@ -12,13 +12,11 @@ module multiply_add_64x64
     input [BITS*2-1:0] c,
     output [BITS*2-1:0] o
 );
-    reg [BITS*2-1:0] o_tmp[2:0];
+    reg [BITS*2-1:0] o_tmp;
 
     always @(posedge clk) begin
-        o_tmp[2] = o_tmp[1];
+	o_tmp = (a * b) + c;
-        o_tmp[1] = o_tmp[0];
-	o_tmp[0] = (a * b) + c;
     end
 
-    assign o = o_tmp[2];
+    assign o = o_tmp;
 endmodule

asic/multiply.vhdl

@@ -5,10 +5,9 @@ use ieee.numeric_std.all;
 library work;
 use work.common.all;
 
--- XXX We should be able to make timing with a 2 cycle multiplier
 entity multiply is
     generic (
-        PIPELINE_DEPTH : natural := 4
+        PIPELINE_DEPTH : natural := 2
         );
     port (
         clk   : in std_logic;