litedram: Regenerate from upstream litex

This adds Joel's sdcard feature reporting to the firmware. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago · c0f7f54276
parent 8cdb00652b
commit c0f7f54276
10 changed files with 6217 additions and 6198 deletions
--- a/litedram/generated/acorn-cle-215/litedram_core.init
+++ b/litedram/generated/acorn-cle-215/litedram_core.init
--- a/litedram/generated/acorn-cle-215/litedram_core.v
+++ b/litedram/generated/acorn-cle-215/litedram_core.v
@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:23
+// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:17
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
--- a/litedram/generated/arty/litedram_core.init
+++ b/litedram/generated/arty/litedram_core.init
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:20
+// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:10
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
--- a/litedram/generated/genesys2/litedram_core.init
+++ b/litedram/generated/genesys2/litedram_core.init
--- a/litedram/generated/genesys2/litedram_core.v
+++ b/litedram/generated/genesys2/litedram_core.v
@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:22
+// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:14
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
--- a/litedram/generated/nexys-video/litedram_core.init
+++ b/litedram/generated/nexys-video/litedram_core.init
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:21
+// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:12
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
--- a/litedram/generated/sim/litedram_core.init
+++ b/litedram/generated/sim/litedram_core.init
--- a/litedram/generated/sim/litedram_core.v
+++ b/litedram/generated/sim/litedram_core.v
@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-09 10:54:25
+// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:19
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire sim_trace,