microwatt

Commit Graph

Author	SHA1	Message	Date
Anton Blanchard	488c30fe91	Add log2ceil and use it in bram code We might want a non power of 2 amount of RAM in order to fit into an FPGA, so create log2ceil and use it when calculating the number of memory bits. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Benjamin Herrenschmidt	336f0e0690	ram: Ack stores early Stores only need a single cycle, so we can ack them early if there isn't an older ack already in the pipeline Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	8e0389b973	ram: Rework main RAM interface This replaces the simple_ram_behavioural and mw_soc_memory modules with a common wishbone_bram_wrapper.vhdl that interfaces the pipelined WB with a lower-level RAM module, along with an FPGA and a sim variants of the latter. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago

Author

SHA1

Message

Date

Anton Blanchard

488c30fe91

Add log2ceil and use it in bram code

We might want a non power of 2 amount of RAM in order to fit into an
FPGA, so create log2ceil and use it when calculating the number of
memory bits.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Benjamin Herrenschmidt

336f0e0690

ram: Ack stores early

Stores only need a single cycle, so we can ack them early if there
isn't an older ack already in the pipeline

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Benjamin Herrenschmidt

8e0389b973

ram: Rework main RAM interface

This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

3 Commits (caravel-20210105)