microwatt

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alt-reset-address

asic-3

boxarty-20211011

cache-tlb-parameters-2

caravel-20210105

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caravel-mpw5-20220323

caravel-mpw6-20220530

core_debug-init

dcache-nc-fix

dcache-unused-sig

divider-init

fpu-constant

fpu-init

fpu-typo

icache-insn-u-state

icache-pmu-events

icache-unused-sig

icbi-issue

jtag-port

jtag-port-2

less-fpga-init

loadstore-init

loadstore-pmu-init

log2ceil-issue

master

nia-debug

orange-crab-freq

remove-potato-uart

unused-sig

35e0dbed34

Merge pull request #353 from tianrui-wei/master master Paul Mackerras 2022-06-17 09:46:57 +1000
cd52390bf1

Merge pull request #373 from antonblanchard/icache-insn-u-state Michael Neuling 2022-06-17 09:13:49 +1000
b983d5080e

Merge pull request #376 from antonblanchard/loadstore-init Michael Neuling 2022-06-16 16:47:33 +1000
d4db331467

Merge pull request #374 from antonblanchard/icache-unused-sig Michael Neuling 2022-06-16 16:45:41 +1000
ee5e3778ed

Merge pull request #364 from shenki/readme-updates Michael Neuling 2022-06-16 14:38:12 +1000
c43692f4c7

Merge pull request #372 from antonblanchard/dcache-unused-sig Michael Neuling 2022-06-16 14:36:50 +1000
956df2c863

Merge pull request #371 from antonblanchard/unused-sig Michael Neuling 2022-06-16 14:35:10 +1000
3627f102db

Merge pull request #370 from antonblanchard/divider-init Michael Neuling 2022-06-16 14:33:45 +1000
6e1e763c02

Merge pull request #368 from antonblanchard/icache-pmu-events Paul Mackerras 2022-06-15 11:02:58 +1000
1047239a37

Merge pull request #377 from antonblanchard/fpu-init Anton Blanchard 2022-06-14 18:10:37 +1000
9d35340bb1 fpu: Reduce uninitialised signals fpu-init Anton Blanchard 2022-06-14 15:14:19 +1000
b82eea5933

Merge pull request #366 from antonblanchard/hello-world-bss Michael Neuling 2022-06-14 13:09:57 +1000
d3aff67fa7

Merge pull request #375 from antonblanchard/core_debug-init Anton Blanchard 2022-06-13 07:15:55 +1000
b47b71821e loadstore1: reduce U state being output loadstore-init Anton Blanchard 2022-06-12 22:15:11 +1000
71d4b5ed20 core_debug: Initialise gspr_index core_debug-init Anton Blanchard 2022-06-12 21:49:13 +1000
a527d9b959 core: Remove unused icache_inv signal icache-unused-sig Anton Blanchard 2022-06-12 21:04:16 +1000
e7f0a7c7ac icache: Don't output X on i_out.insn icache-insn-u-state Anton Blanchard 2022-06-12 11:42:32 +1000
39220be311 dcache: remove unused do_write signal dcache-unused-sig Anton Blanchard 2022-06-12 11:39:31 +1000
843361f2be execute1: sub_mux_sel and result_mux_sel are unused unused-sig Anton Blanchard 2022-06-12 10:49:26 +1000
d3a7517318 divider: Fix d_out.overflow U state issue divider-init Anton Blanchard 2022-06-12 10:34:20 +1000
1ff852b012

Merge pull request #369 from antonblanchard/loadstore-pmu-init Anton Blanchard 2022-06-12 10:24:54 +1000
e2438071a1 loadstore1: Initialise PMU events loadstore-pmu-init Anton Blanchard 2022-06-12 09:29:46 +1000
b7c4d3c5c3

Merge pull request #367 from antonblanchard/fpu-typo Anton Blanchard 2022-06-12 09:32:59 +1000
f06abb67ad icache: Hook up PMU events icache-pmu-events Anton Blanchard 2022-06-12 09:21:56 +1000
64d2def0c6 fpu: Fix capitalisation of Execute1ToFPUType fpu-typo Anton Blanchard 2022-06-10 08:10:27 +1000
ff442d1bdb Zero BSS in hello world test Anton Blanchard 2022-06-08 15:20:07 +1000
b8fc5636a4

Merge pull request #365 from antonblanchard/less-fpga-init Anton Blanchard 2022-06-08 14:54:48 +1000
ebdddcc402 Remove some FPGA style signal inits less-fpga-init Anton Blanchard 2022-06-07 20:01:14 +1000
a750365ffa Remove some FPGA style signal inits Anton Blanchard 2022-06-07 17:38:24 +1000
9ec22af256 README: Add Linux on Microwatt instructions Joel Stanley 2022-06-07 12:50:03 +0930
a31725d989 README: Add uart to fusesoc instructions Joel Stanley 2022-06-07 12:48:42 +0930
2083bc3ed0 ASIC: Fix multiplier power caravel-mpw6-20220530 Anton Blanchard 2022-06-07 08:50:35 +1000
ace41e5153 ASIC: Reduce multiplier from 4 to 2 cycles Anton Blanchard 2022-05-30 14:34:21 +1000
907c833521 Move register stage back after the RAM caravel-mpw5-20220323 Anton Blanchard 2022-03-23 17:43:09 +1100
f5e06c2d4b

Merge pull request #361 from antonblanchard/alt-reset-address Michael Neuling 2022-03-22 11:55:54 +1100
5c40143754 Add a script to post process the Microwatt verilog for caravel caravel-mpw5-20220322 Anton Blanchard 2020-12-17 15:14:54 +1100
d0ced7441f Add simplebus verilog Anton Blanchard 2022-03-21 06:35:38 +1100
606359cce3 Add simplebus Anton Blanchard 2022-03-15 15:19:13 +1100
49b332e17f Hook up JTAG to ASIC top level Anton Blanchard 2021-10-26 15:15:02 +1100
d5e3be80fe Set a unique PVR for caravel MPW5 Anton Blanchard 2021-01-14 10:21:33 +1100
d504ae63f6 Update JTAG TAP controller for Microwatt Anton Blanchard 2020-12-08 18:55:08 +1100
15bb4aa90a First pass at an external JTAG port Anton Blanchard 2022-02-01 08:44:00 +1100
c2577b5446 Add ASIC target Anton Blanchard 2021-03-24 22:00:27 +1100
5249d633cf Move register stage from after RAM to before RAM Anton Blanchard 2022-02-24 10:18:28 +1100
8ecb30da05 Add arrays for ASIC flow Anton Blanchard 2021-03-23 19:44:16 +1100
747c96b100 Cut down hello_world to fit in 4kB Anton Blanchard 2021-10-26 12:21:26 +1100
faab169307 Allow ALT_RESET_ADDRESS to be overridden Anton Blanchard 2022-02-01 20:06:57 +1100
948f6f43a7 Allow ALT_RESET_ADDRESS to be overridden alt-reset-address Anton Blanchard 2022-03-22 09:35:17 +1100
8bf48ac094

Merge pull request #360 from antonblanchard/log2ceil-issue Michael Neuling 2022-03-18 18:28:34 +1100
b5accb78b2 wishbone_bram_wrapper ram_addr_bits is 1 bit off log2ceil-issue Anton Blanchard 2022-03-17 18:03:29 +1100
30fd936c12

Merge pull request #358 from antonblanchard/unused-sig Michael Neuling 2022-03-16 10:49:47 +1100
af1b76d944

Merge pull request #356 from antonblanchard/fpu-constant Michael Neuling 2022-03-16 10:49:29 +1100
9b96ab730c

Merge pull request #357 from antonblanchard/xics-warning Michael Neuling 2022-03-16 10:48:59 +1100
0b39947f8d Remove unused sequential signal from Fetch1ToIcacheType Anton Blanchard 2022-03-15 18:27:48 +1100
00bf0af21c xics: Fix warning when comparing two std_ulogic_vectors Anton Blanchard 2022-03-15 16:04:18 +1100
50b4cb9423 fpu: Make inverse_table a constant fpu-constant Anton Blanchard 2022-03-15 16:03:34 +1100
844ca0e6b5

fix: fix icache_tb not finishing correctly Tianrui Wei 2022-03-01 23:51:35 +0800
f01f3d233a

Merge pull request #352 from mkj/static-urjtag Michael Neuling 2022-02-28 08:17:50 +1100
c0c00d05bc mw_debug: Add STATIC_URJTAG flag Matt Johnston 2022-02-25 17:43:28 +0800
ffcdaaa92d

Update the README Issues (#350) Michael Neuling 2022-02-25 13:18:38 +1100
b4770197a2

Merge pull request #349 from madscientist159/master Michael Neuling 2022-02-25 11:08:57 +1100
fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line Raptor Engineering Development Team 2022-02-22 11:49:33 -0600
2b97fb0bf3

Merge pull request #348 from paulusmack/reduce Michael Neuling 2022-02-23 12:03:59 +1100
0aa898c7a6 xics: Rework the irq_gen process Paul Mackerras 2021-10-19 15:13:31 +1100
1720a0584a Use alternative count-leading-zeroes algorithm in the FPU and LSU Paul Mackerras 2022-02-21 12:06:11 +1100
1086988883 countzero: Use alternative algorithm for higher bits Paul Mackerras 2022-02-21 09:58:07 +1100
4cf2921b0b soc: Re-do peripheral address decode to improve timing Paul Mackerras 2021-10-11 17:46:44 +1100
27b660ef76

Merge pull request #346 from mkj/dmi_ecp5 Michael Neuling 2022-02-08 09:09:22 +1100
5a5a082601

Merge pull request #343 from mikey/orange-crab-ci Anton Blanchard 2022-02-07 17:57:08 +1100
9c64f8a98b mw_debug: Add Lattice ECP5 support Matt Johnston 2022-02-04 15:29:40 +0800
3775650df3 dmi_dtm_ecp5: Use ECP5 JTAGG for DMI Matt Johnston 2021-11-26 10:47:07 +0800
eb20195a10 mw_debug: Link urjtag statically Matt Johnston 2022-02-04 14:40:42 +0800
763138798e mw_debug: use isxdigit for hex arguments Matt Johnston 2022-02-04 12:08:07 +0800
04cc4a842c mw_debug: Add -s frequency argument Matt Johnston 2021-11-26 10:43:06 +0800
e05ae0c8cb mw_debug: pass target parameters to urjtag Matt Johnston 2021-11-25 14:12:13 +0800
49ec80ac3e fetch1/icache1: Remove the use_previous logic Paul Mackerras 2021-10-11 17:23:08 +1100
cef3660e74

Merge pull request #345 from antonblanchard/popcnt-go-fast Paul Mackerras 2022-02-04 11:43:42 +1100
2491aa7fc5 core: Make popcnt* take two cycles Paul Mackerras 2021-10-19 12:22:10 +1100
11c5ac68e8 Fix caravel script asic-3 Anton Blanchard 2022-02-01 21:03:56 +1100
c7ef75b55c Forgot multiply.vhdl Anton Blanchard 2022-02-01 20:52:58 +1100
e70d7f0a60 Make caches 1 way Anton Blanchard 2022-01-07 11:36:12 +1100
7da4977028 Disable FPU Anton Blanchard 2021-12-30 12:17:25 +1100
1383bbb8be Add GPIOs Anton Blanchard 2021-10-29 20:05:19 +1100
46a85cb274 Add asic alternate reset address Anton Blanchard 2022-02-01 19:55:56 +1100
4e9001ba19 Hook up JTAG to asic top level Anton Blanchard 2021-10-26 15:15:02 +1100
09c8b0332e Cut down hello_world to fit in 4kB Anton Blanchard 2021-10-26 12:21:26 +1100
f4a52fdc1f Add a script to post process the microwatt verilog for caravel Anton Blanchard 2020-12-17 15:14:54 +1100
125cd4bc97 Update PVR Anton Blanchard 2021-01-14 10:21:33 +1100
0f864ae8b9 Update JTAG TAP controller for Microwatt Anton Blanchard 2020-12-08 18:55:08 +1100
fd9350c3b5 First pass at an external JTAG port Anton Blanchard 2022-02-01 08:44:00 +1100
18503732d7 Add ASIC target Anton Blanchard 2021-03-24 22:00:27 +1100
5ac715d932 Fix multiplier behavioural Anton Blanchard 2022-02-01 20:22:31 +1100
537a0aac1d Add arrays for ASIC flow Anton Blanchard 2021-03-23 19:44:16 +1100
ef641dcc28 Allow ALT_RESET_ADDRESS to be overridden Anton Blanchard 2022-02-01 20:06:57 +1100
286757f0f7 ci: Add new Orange Crab build Michael Neuling 2022-01-18 12:41:03 +1100
6ff3b2499c

Merge pull request #342 from mkj/orangecrab-merge Michael Neuling 2022-01-18 13:27:27 +1100
cdd661d844

Merge branch 'master' into orangecrab-merge Michael Neuling 2022-01-18 12:03:46 +1100
fda8879e2f

Merge pull request #341 from mkj/progtools Michael Neuling 2022-01-18 11:51:54 +1100
ffbf2f9964

Merge pull request #340 from mkj/orangecrab-ghdl-plugin Michael Neuling 2022-01-18 11:50:22 +1100
049f0549d8 orangecrab: Fix sdcard wishbone addressing Matt Johnston 2021-11-19 13:13:15 +0800