A tiny Open POWER ISA softcore written in VHDL 2008
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Anton Blanchard d3a7517318 divider: Fix d_out.overflow U state issue 10 months ago
.github/workflows ci: Add new Orange Crab build 1 year ago
constraints orangecrab: add Orange Crab r0.2 target 1 year ago
fpga Extend LiteDRAM VHDL wrapper to allow more than one clock line 1 year ago
hello_world Reduce hello_world footprint to fit in 8kB 2 years ago
include arty_a7: Add litesdcard interface 2 years ago
lib console: Add support for the 16550 UART 3 years ago
litedram Extend LiteDRAM VHDL wrapper to allow more than one clock line 1 year ago
liteeth Regenerate litedram and liteeth 2 years ago
litesdcard litesdcard: add lattice, regenerate 1 year ago
media Add title image 4 years ago
micropython tests: Add updated micropython build with 16550 support 3 years ago
openocd flash-arty: Add cable argument 2 years ago
rust_lib_demo console: Cleanup console API 3 years ago
scripts mw_debug: Add STATIC_URJTAG flag 1 year ago
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 4 years ago
tests tests/misc: Add a store/dcbz test 2 years ago
uart16550 Add uart16550 files from fusesoc 3 years ago
verilator verilator: Specify top level module 2 years ago
.gitignore Add liteeth/build to gitignore 2 years ago
LICENSE Initial import of microwatt 4 years ago
Makefile dmi_dtm_ecp5: Use ECP5 JTAGG for DMI 1 year ago
README.md Update the README Issues (#350) 1 year ago
cache_ram.vhdl Reformat cache_ram 2 years ago
common.vhdl Remove unused sequential signal from Fetch1ToIcacheType 1 year ago
control.vhdl Remove some FPGA style signal inits 10 months ago
core.vhdl Remove some FPGA style signal inits 10 months ago
core_debug.vhdl Fix some whitespace issues 2 years ago
core_dram_tb.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 1 year ago
core_flash_tb.vhdl Reformat testbenches 2 years ago
core_tb.vhdl Reformat testbenches 2 years ago
countbits.vhdl Use alternative count-leading-zeroes algorithm in the FPU and LSU 1 year ago
countbits_tb.vhdl core: Make popcnt* take two cycles 1 year ago
cr_file.vhdl Reformat cr_file 2 years ago
crhelpers.vhdl crhelpers: Constraint "crnum" integer 4 years ago
dcache.vhdl Introduce addr_to_wb() and wb_to_addr() helpers 2 years ago
dcache_tb.vhdl Reformat testbenches 2 years ago
decode1.vhdl decode1: Conditional trap instructions don't need to be single-issue 2 years ago
decode2.vhdl core: Make popcnt* take two cycles 1 year ago
decode_types.vhdl core: Crack update-form loads into two internal ops 2 years ago
divider.vhdl divider: Fix d_out.overflow U state issue 10 months ago
divider_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 2 years ago
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl 4 years ago
dmi_dtm_ecp5.vhdl dmi_dtm_ecp5: Use ECP5 JTAGG for DMI 1 year ago
dmi_dtm_tb.vhdl Reformat testbenches 2 years ago
dmi_dtm_xilinx.vhdl Fix some whitespace issues 2 years ago
dram_tb.vhdl Extend LiteDRAM VHDL wrapper to allow more than one clock line 1 year ago
execute1.vhdl Remove some FPGA style signal inits 10 months ago
fetch1.vhdl fetch1/icache1: Remove the use_previous logic 1 year ago
foreign_random.vhdl Make core testbenches recognized by VUnit 2 years ago
fpu.vhdl fpu: Fix capitalisation of Execute1ToFPUType 10 months ago
glibc_random.vhdl Reformat glibc_random 4 years ago
glibc_random_helpers.vhdl Reformat glibc_random 4 years ago
gpio.vhdl Remove some FPGA style signal inits 10 months ago
helpers.vhdl xics: Rework the irq_gen process 1 year ago
icache.vhdl fetch1/icache1: Remove the use_previous logic 1 year ago
icache_tb.vhdl Reformat testbenches 2 years ago
icache_test.bin icache_tb: Improve test and include test file 4 years ago
insn_helpers.vhdl core: Implement quadword loads and stores 2 years ago
loadstore1.vhdl loadstore1: Initialise PMU events 10 months ago
logical.vhdl core: Make popcnt* take two cycles 1 year ago
microwatt.core core: Make popcnt* take two cycles 1 year ago
mmu.vhdl MMU: Implement a vestigial partition table 2 years ago
multiply.vhdl core: Add a short multiplier 2 years ago
multiply_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 2 years ago
nonrandom.vhdl Add random number generator and implement the darn instruction 3 years ago
plru.vhdl Reformat plru 2 years ago
plru_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 2 years ago
pmu.vhdl PMU: Add several more events 2 years ago
ppc_fx_insns.vhdl Fix some whitespace issues 2 years ago
random.vhdl Make core testbenches recognized by VUnit 2 years ago
register_file.vhdl Reformat register_file 2 years ago
rotator.vhdl Reformat rotator 2 years ago
rotator_tb.vhdl Replaced VHDL assert and report with VUnit checking and logging 2 years ago
run.py VUnit: style 2 years ago
sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART 3 years ago
sim_bram.vhdl Rename 'do' signal to avoid verilator System Verilog warning 2 years ago
sim_bram_helpers.vhdl ram: Rework main RAM interface 3 years ago
sim_bram_helpers_c.c Consolidate VHPI code 3 years ago
sim_console.vhdl Reformat sim_console 4 years ago
sim_console_c.c sim_console: Fix polling to check for POLLIN 3 years ago
sim_jtag.vhdl Add jtag support in simulation via a socket 4 years ago
sim_jtag_socket.vhdl Add jtag support in simulation via a socket 4 years ago
sim_jtag_socket_c.c Consolidate VHPI code 3 years ago
sim_no_flash.vhdl spi: Add simulation support 3 years ago
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl 3 years ago
sim_vhpi_c.c Consolidate VHPI code 3 years ago
sim_vhpi_c.h Consolidate VHPI code 3 years ago
soc.vhdl Remove some FPGA style signal inits 10 months ago
spi_flash_ctrl.vhdl Remove some FPGA style signal inits 10 months ago
spi_rxtx.vhdl Remove some FPGA style signal inits 10 months ago
sync_fifo.vhdl litedram: Add an L2 cache with store queue 3 years ago
syscon.vhdl Make wishbone addresses be in units of doublewords or words 2 years ago
utils.vhdl litedram: Add support for booting without BRAM 3 years ago
wishbone_arbiter.vhdl wb_arbiter: Early master selection 3 years ago
wishbone_bram_tb.bin ram: Rework main RAM interface 3 years ago
wishbone_bram_tb.vhdl Make wishbone addresses be in units of doublewords or words 2 years ago
wishbone_bram_wrapper.vhdl wishbone_bram_wrapper ram_addr_bits is 1 bit off 1 year ago
wishbone_debug_master.vhdl Make wishbone addresses be in units of doublewords or words 2 years ago
wishbone_types.vhdl Introduce addr_to_wb() and wb_to_addr() helpers 2 years ago
writeback.vhdl PMU: Add several more events 2 years ago
xics.vhdl xics: Fix warning when comparing two std_ulogic_vectors 1 year ago
xilinx-mult.vhdl core: Add a short multiplier 2 years ago

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • If this is your first time using fusesoc, initialize fusesoc. This is needed to be able to pull down fussoc library components referenced by microwatt. Run
fusesoc init
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100): You may wish to ensure you have installed Digilent Board files or appropriate files for your board first.
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

  • There are a few instructions still to be implemented:
    • Vector/VMX/VSX