microwatt

Commit Graph

Author	SHA1	Message	Date
Raptor Engineering Development Team	fcb783a0fb	Extend LiteDRAM VHDL wrapper to allow more than one clock line This is necessary for the upcoming Arctic Tern system enablement, since Arctic Tern uses two DRAM devices and a separate clock line is routed to each device. LiteX handles this behavior correctly, therefore we assume other hardware exists that uses a similar DRAM clock design. Updates from Mikey to fix some compile issues. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Michael Neuling <mikey@neuling.org>	3 years ago
Boris Shingarov	679c547e5f	fpga: Add support for Genesys2 Signed-off-by: Boris Shingarov <shingarov@labware.com>	4 years ago

Author

SHA1

Message

Date

Raptor Engineering Development Team

fcb783a0fb

Extend LiteDRAM VHDL wrapper to allow more than one clock line

This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device.  LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.

Updates from Mikey to fix some compile issues.

Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>

Boris Shingarov

679c547e5f

fpga: Add support for Genesys2

Signed-off-by: Boris Shingarov <shingarov@labware.com>

2 Commits (icache-insn-u-state)