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fpu-init
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icache-unused-sig
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dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
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less-fpga-init
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alt-reset-address
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fpu-constant
asic-3
boxarty-20211011
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remove-potato-uart
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caravel-20210114
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2 Commits (less-fpga-init)

Author SHA1 Message Date
Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line 
This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device.  LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.

Updates from Mikey to fix some compile issues.

Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
 3 years ago
Benjamin Herrenschmidt da0189af1e Add support for QMTech Wukong v2 board 
For now only the V2 of the board (slightly different pinout)
and only the A100T variant. I also haven't added GPIOs or anything
else on the PMODs really.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 3 years ago