8 Commits (1249a11349af27a7b013713a17da6b823d1c7951)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	8e0389b973	ram: Rework main RAM interface ... This replaces the simple_ram_behavioural and mw_soc_memory modules with a common wishbone_bram_wrapper.vhdl that interfaces the pipelined WB with a lower-level RAM module, along with an FPGA and a sim variants of the latter. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	98f0994698	Add core debug module ... This module adds some simple core controls: reset, stop, start, step along with icache clear and reading the NIA and core status bits Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org	5 years ago
Anton Blanchard	89849a6856	Add a simple direct mapped icache ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Benjamin Herrenschmidt	3ac1dbc737	Share soc.vhdl between FPGA and sim ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	c97b080d8c	Move wishbone arbiter out of the core ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	8bfd6e5eae	Use simulated UART in core test bench ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	1fa0b332ca	micropython only requires 512kB of BRAM ... Mikey points out that our stack grows down from 512kB and our heap is below that too, so we can reduce our BRAM requirements, which allowing some smaller FPGA boards to work. Not sure why I thought we were using memory between 512kB and 1MB. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	5a29cb4699	Initial import of microwatt ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago