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microwatt
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852 Commits
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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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Commit Graph

2 Commits (185bcba6bbb5beb640c36e725cdbf3e82b8ec968)

Author SHA1 Message Date
Anton Blanchard d1f0ac2e0b Disable second uart since we aren't using it 3 years ago
Anton Blanchard 17d93d504a Add a toplevel file for caravel 3 years ago