5 Commits (1d09daae030835c673e2fe35c07f88f9ca736b85)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	cc4dcb3597	spi: Add SPI Flash controller ... This adds an SPI flash controller which supports direct memory-mapped access to the flash along with a manual mode to send commands. The direct mode can be set via generic to default to single wire or quad mode. The controller supports normal, dual and quad accesses with configurable commands, clock divider, dummy clocks etc... The SPI clock can be an even divider of sys_clk starting at 2 (so max 50Mhz with our typical Arty designs). A flash offset is carried via generics to syscon to tell SW about which portion of the flash is reserved for the FPGA bitfile. There is currently no plumbing to make the CPU reset past that address (TBD). Note: Operating at 50Mhz has proven unreliable without adding some delay to the sampling of the input data. I'm working in improving this, in the meantime, I'm leaving the default set at 25 Mhz. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	5ae5f76558	arty/nexys-video: Update XDC ... The DRAM related pins have some small changes in LiteX, so resync and add the false path information as well. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	3ac815823c	fpga: Hookup Arty to litedram ... The old toplevel.vhdl becomes top-generic.vhdl, which is to be used by platforms that do not have a litedram option. Arty has its own top-arty.vhdl which supports litedram and is now hooked up Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Anton Blanchard	20674e0d65	Add SPI configuration to Xilinx constraint files ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Benjamin Herrenschmidt	ab5c6ab9ac	fpga: Arty A7's don't need multiple filesets ... the XDC is identical between variants, so is the fileset Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago