matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
942 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '2031c6d2d2'
${ noResults }
Commit Graph

1 Commits (2031c6d2d22a43cff869c5716ee7e06f4fb26334)

Author SHA1 Message Date
Paul Mackerras e7a08f33eb tests: Add a test for the load-reserve and store-conditional instructions 
This checks that the instructions seem to update memory as expected,
and also that they generate alignment interrupts when necessary.
We don't check whether the memory update is atomic as we don't have
SMP yet.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago