matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1,109 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '3627f102db'
${ noResults }
Commit Graph

4 Commits (3627f102dbea804e43030b10c3f99a7d0328da21)

Author SHA1 Message Date
Paul Mackerras f3c6119cf6 tests/mmu: Add a test of PTE refetching on permission error 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago
Paul Mackerras 8ff8b2f256 tests/mmu: Add a test for dcbz with translation on 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago
Paul Mackerras b342312e4e tests: mmu: Add tests for instruction translation 
This adds tests of instruction translation to the mmu test.

This also clears the BSS and improves the linker script.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago
Paul Mackerras 882a5a0dc0 tests: Add a test for the MMU radix page table walks 
This adds tests to check that the MMU and dTLB are translating
addresses and checking permissions correctly.

We use a simple 2-level radix tree.  The radix tree maps 2GB of
address space and has a 1024-entry page directory pointing to
512-entry page table pages.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago