microwatt

Commit Graph

Author	SHA1	Message	Date
Benjamin Herrenschmidt	d21ef5836d	Pass wishbone record to bram memory module (And rename it to mw_soc_memory). This makes soc.vhdl simpler and provides the same interface as the simulated memory, which will help when sharing soc.vhdl with sim later Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago

Author

SHA1

Message

Date

Benjamin Herrenschmidt

d21ef5836d

Pass wishbone record to bram memory module

(And rename it to mw_soc_memory).

This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 Commits (3b32abcb5d57f7514b0f1452b49ca81143883915)