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microwatt
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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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Commit Graph

3 Commits (46a85cb274d3bb790c29b58322a638d31846c01c)

Author SHA1 Message Date
Anton Blanchard 46a85cb274 Add asic alternate reset address 2 years ago
Anton Blanchard 4e9001ba19 Hook up JTAG to asic top level 2 years ago
Anton Blanchard 18503732d7 Add ASIC target 2 years ago