2 Commits (49a4d9f67a21438a4af703027baa72211409857a)

Author	SHA1	Message	Date
Benjamin Herrenschmidt	599fad117b	litedram: Remove old "VexRiscV" based initializations ... Support for this has bitrotted and would require refactoring of L2 to be brought back. It's also not really needed anymore now that we ship pre-generated litedram and that LiteX supports what we do. So take it out, which simplifies some of the scripts as well. This also fixes up CSR alignment the sim model. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	6fe077910b	litedram: Add simulation support ... This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago