matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1,026 Commits
31 Branches
0 Tags
65 MiB
master
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '4b1a413a2f'
${ noResults }
Commit Graph

2 Commits (4b1a413a2fe7ac6657295a4a7a7d10b4596d61b4)

Author SHA1 Message Date
Paul Mackerras ec5730a75a tests: Add tests for lq/stq and lqarx/stqcx. 
Lq and stq are tested in both BE and LE modes (though only 64-bit
mode) by the 'modes' test.

Lqarx and stqcx. are tested by the 'reservation' test in LE mode mode
(64-bit).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago
Paul Mackerras 371fd4cc20 tests: Add tests for 32-bit and big-endian modes 
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 4 years ago