Anton Blanchard
5a6f8d26d1
Rename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE
...
These were somewhat badly named.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard
6d85920068
execute1 no longer needs sim_console
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Michael Neuling
1e1b799382
Remove FIXME comment
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This was mistakenly left behind in 4d5abfb430
("Remove dynamic
ranges from code")
Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Anton Blanchard
a2df2a10a2
Remove sim console
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We can force all existing code to use the UART console
by passing 0 in bit zero of the sim config register.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard
a8f8c54b77
Move debug execute output into decode2
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This covers all units, and we avoid double printing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard
92a7152370
Rework pipeline, add stall and flush signals
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This adds stall and flush signals to the pipeline.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Michael Neuling
4d5abfb430
Remove dynamic ranges from code
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Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.
Also add basic script to run verific and generate verilog.
1. https://www.verific.com/
Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Anton Blanchard
0fd18c2455
Add srd and srw
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard
73daacbcd4
Add sim only divw
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard
5a29cb4699
Initial import of microwatt
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago